1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; REQUIRES: asserts 3; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(loop-simplifycfg)' -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s 4; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -verify-memoryssa -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s 5 6target triple = "x86_64-unknown-linux-gnu" 7 8define void @test() { 9; CHECK-LABEL: @test( 10; CHECK-NEXT: br label [[BB1:%.*]] 11; CHECK: bb1.loopexit: 12; CHECK-NEXT: br label [[BB1]] 13; CHECK: bb1: 14; CHECK-NEXT: br label [[BB2:%.*]] 15; CHECK: bb2.loopexit: 16; CHECK-NEXT: br label [[BB2]] 17; CHECK: bb2: 18; CHECK-NEXT: switch i32 0, label [[BB2_SPLIT:%.*]] [ 19; CHECK-NEXT: i32 1, label [[BB1_LOOPEXIT:%.*]] 20; CHECK-NEXT: i32 2, label [[BB2_LOOPEXIT:%.*]] 21; CHECK-NEXT: ] 22; CHECK: bb2.split: 23; CHECK-NEXT: br label [[BB3:%.*]] 24; CHECK: bb3: 25; CHECK-NEXT: br label [[BB3]] 26; 27 28 br label %bb1 29 30bb1: ; preds = %bb4, %0 31 br label %bb2 32 33bb2: ; preds = %bb6, %bb1 34 br label %bb3 35 36bb3: ; preds = %bb8, %bb3, %bb2 37 br i1 false, label %bb4, label %bb3 38 39bb4: ; preds = %bb8, %bb3 40 br i1 undef, label %bb1, label %bb6 41 42bb6: ; preds = %bb4 43 br i1 undef, label %bb2, label %bb8 44 45bb8: ; preds = %bb6 46 br i1 true, label %bb4, label %bb3 47} 48 49define void @test_many_subloops(i1 %c) { 50; CHECK-LABEL: @test_many_subloops( 51; CHECK-NEXT: br label [[BB1:%.*]] 52; CHECK: bb1.loopexit: 53; CHECK-NEXT: br label [[BB1]] 54; CHECK: bb1: 55; CHECK-NEXT: br label [[BB2:%.*]] 56; CHECK: bb2.loopexit: 57; CHECK-NEXT: br label [[BB2]] 58; CHECK: bb2: 59; CHECK-NEXT: switch i32 0, label [[BB2_SPLIT:%.*]] [ 60; CHECK-NEXT: i32 1, label [[BB1_LOOPEXIT:%.*]] 61; CHECK-NEXT: i32 2, label [[BB2_LOOPEXIT:%.*]] 62; CHECK-NEXT: ] 63; CHECK: bb2.split: 64; CHECK-NEXT: br label [[BB3:%.*]] 65; CHECK: bb3: 66; CHECK-NEXT: br label [[BB3]] 67; 68 69 br label %bb1 70 71bb1: 72 br label %bb2 73 74bb2: 75 br label %bb3 76 77bb3: 78 br i1 false, label %bb4, label %bb3 79 80bb4: 81 br i1 undef, label %bb1, label %subloop1 82 83subloop1: 84 br i1 %c, label %subloop2, label %subloop11 85 86subloop11: 87 br i1 %c, label %subloop11, label %subloop12 88 89subloop12: 90 br i1 %c, label %subloop12, label %subloop13 91 92subloop13: 93 br i1 %c, label %subloop13, label %subloop1_latch 94 95subloop1_latch: 96 br label %subloop1 97 98subloop2: 99 br i1 %c, label %bb6, label %subloop21 100 101subloop21: 102 br i1 %c, label %subloop21, label %subloop22 103 104subloop22: 105 br i1 %c, label %subloop22, label %subloop23 106 107subloop23: 108 br i1 %c, label %subloop23, label %subloop2_latch 109 110subloop2_latch: 111 br label %subloop2 112 113bb6: 114 br i1 undef, label %bb2, label %bb8 115 116bb8: 117 br i1 true, label %bb4, label %bb3 118} 119