1; REQUIRES: amdgpu-registered-target && x86-registered-target
2; RUN: opt < %s -mtriple=amdgcn -jump-threading -S | FileCheck %s  -check-prefixes=CHECK,DIVERGENT
3; RUN: opt < %s -mtriple=amdgcn -passes=jump-threading -S | FileCheck %s  -check-prefixes=CHECK,DIVERGENT
4; RUN: opt < %s -mtriple=x86_64 -jump-threading -S | FileCheck %s  -check-prefixes=CHECK,UNIFORM
5; RUN: opt < %s -mtriple=x86_64 -passes=jump-threading -S | FileCheck %s  -check-prefixes=CHECK,UNIFORM
6
7; Here we assure that for the target with no branch divergence usual Jump Threading optimization performed
8; For target with branch divergence - no optimization, so the IR is unchanged.
9
10declare i32 @f1()
11declare i32 @f2()
12declare void @f3()
13
14define i32 @test(i1 %cond) {
15; CHECK: test
16	br i1 %cond, label %T1, label %F1
17
18; DIVERGENT:   T1
19; UNIFORM-NOT: T1
20T1:
21	%v1 = call i32 @f1()
22	br label %Merge
23; DIVERGENT:   F1
24; UNIFORM-NOT: F1
25F1:
26	%v2 = call i32 @f2()
27	br label %Merge
28; DIVERGENT:   Merge
29; UNIFORM-NOT: Merge
30Merge:
31	%A = phi i1 [true, %T1], [false, %F1]
32	%B = phi i32 [%v1, %T1], [%v2, %F1]
33	br i1 %A, label %T2, label %F2
34
35; DIVERGENT:   T2
36T2:
37; UNIFORM: T2:
38; UNIFORM: %v1 = call i32 @f1()
39; UNIFORM: call void @f3()
40; UNIFORM: ret i32 %v1
41	call void @f3()
42	ret i32 %B
43; DIVERGENT:   F2
44F2:
45; UNIFORM: F2:
46; UNIFORM: %v2 = call i32 @f2()
47; UNIFORM: ret i32 %v2
48	ret i32 %B
49}
50