1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=instcombine -S | FileCheck %s
3
4; Test that the reverse is eliminated if the output and all the inputs
5; of the instruction are calls to reverse.
6define <vscale x 4 x i32> @binop_reverse(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
7; CHECK-LABEL: @binop_reverse(
8; CHECK-NEXT:    [[ADD1:%.*]] = add <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
9; CHECK-NEXT:    ret <vscale x 4 x i32> [[ADD1]]
10;
11  %reva = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
12  %revb = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %b)
13  %add = add <vscale x 4 x i32> %reva, %revb
14  %revadd = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %add)
15  ret <vscale x 4 x i32> %revadd
16}
17
18define <vscale x 4 x i32> @binop_reverse_splat_RHS(<vscale x 4 x i32> %a, i32 %b) {
19; CHECK-LABEL: @binop_reverse_splat_RHS(
20; CHECK-NEXT:    [[SPLAT_INSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[B:%.*]], i64 0
21; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[SPLAT_INSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
22; CHECK-NEXT:    [[UDIV1:%.*]] = udiv <vscale x 4 x i32> [[A:%.*]], [[SPLAT]]
23; CHECK-NEXT:    ret <vscale x 4 x i32> [[UDIV1]]
24;
25  %reva = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
26  %splat_insert = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
27  %splat = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
28  %udiv = udiv <vscale x 4 x i32> %reva, %splat
29  %revadd = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %udiv)
30  ret <vscale x 4 x i32> %revadd
31}
32
33define <vscale x 4 x i32> @binop_reverse_splat_LHS(<vscale x 4 x i32> %a, i32 %b) {
34; CHECK-LABEL: @binop_reverse_splat_LHS(
35; CHECK-NEXT:    [[SPLAT_INSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[B:%.*]], i64 0
36; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[SPLAT_INSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
37; CHECK-NEXT:    [[UDIV1:%.*]] = udiv <vscale x 4 x i32> [[SPLAT]], [[A:%.*]]
38; CHECK-NEXT:    ret <vscale x 4 x i32> [[UDIV1]]
39;
40  %reva = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
41  %splat_insert = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
42  %splat = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
43  %udiv = udiv <vscale x 4 x i32> %splat, %reva
44  %revadd = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %udiv)
45  ret <vscale x 4 x i32> %revadd
46}
47
48define <vscale x 4 x float> @unop_reverse(<vscale x 4 x float> %a) {
49; CHECK-LABEL: @unop_reverse(
50; CHECK-NEXT:    [[NEG1:%.*]] = fneg fast <vscale x 4 x float> [[A:%.*]]
51; CHECK-NEXT:    ret <vscale x 4 x float> [[NEG1]]
52;
53  %reva = tail call <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float> %a)
54  %neg = fneg fast <vscale x 4 x float> %reva
55  %revneg = tail call <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float> %neg)
56  ret <vscale x 4 x float> %revneg
57}
58
59declare <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float>)
60declare <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32>)
61
62
63