1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instcombine -S | FileCheck %s 3 4define <4 x i32> @lshr_non_splat_vector(<4 x i32> %A) { 5; CHECK-LABEL: @lshr_non_splat_vector( 6; CHECK-NEXT: [[B:%.*]] = lshr <4 x i32> [[A:%.*]], <i32 32, i32 1, i32 2, i32 3> 7; CHECK-NEXT: ret <4 x i32> [[B]] 8; 9 %B = lshr <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 10 ret <4 x i32> %B 11} 12 13define <4 x i32> @shl_non_splat_vector(<4 x i32> %A) { 14; CHECK-LABEL: @shl_non_splat_vector( 15; CHECK-NEXT: [[B:%.*]] = shl <4 x i32> [[A:%.*]], <i32 32, i32 1, i32 2, i32 3> 16; CHECK-NEXT: ret <4 x i32> [[B]] 17; 18 %B = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 19 ret <4 x i32> %B 20} 21 22define i32 @test6(i32 %A) { 23; CHECK-LABEL: @test6( 24; CHECK-NEXT: [[C:%.*]] = mul i32 [[A:%.*]], 6 25; CHECK-NEXT: ret i32 [[C]] 26; 27 %B = shl i32 %A, 1 ;; convert to an mul instruction 28 %C = mul i32 %B, 3 29 ret i32 %C 30} 31 32define i32 @test6a(i32 %A) { 33; CHECK-LABEL: @test6a( 34; CHECK-NEXT: [[C:%.*]] = mul i32 [[A:%.*]], 6 35; CHECK-NEXT: ret i32 [[C]] 36; 37 %B = mul i32 %A, 3 38 %C = shl i32 %B, 1 ;; convert to an mul instruction 39 ret i32 %C 40} 41 42;; (A << 5) << 3 === A << 8 == 0 43define i8 @test8(i8 %A) { 44; CHECK-LABEL: @test8( 45; CHECK-NEXT: ret i8 0 46; 47 %B = shl i8 %A, 5 48 %C = shl i8 %B, 3 49 ret i8 %C 50} 51 52;; (A << 7) >> 7 === A & 1 53define i8 @test9(i8 %A) { 54; CHECK-LABEL: @test9( 55; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], 1 56; CHECK-NEXT: ret i8 [[B]] 57; 58 %B = shl i8 %A, 7 59 %C = lshr i8 %B, 7 60 ret i8 %C 61} 62 63;; (A >> 7) << 7 === A & 128 64 65define i8 @test10(i8 %A) { 66; CHECK-LABEL: @test10( 67; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], -128 68; CHECK-NEXT: ret i8 [[B]] 69; 70 %B = lshr i8 %A, 7 71 %C = shl i8 %B, 7 72 ret i8 %C 73} 74 75;; Allow the simplification when the lshr shift is exact. 76define i8 @test10a(i8 %A) { 77; CHECK-LABEL: @test10a( 78; CHECK-NEXT: ret i8 [[A:%.*]] 79; 80 %B = lshr exact i8 %A, 7 81 %C = shl i8 %B, 7 82 ret i8 %C 83} 84 85;; (A >> 3) << 4 === (A & 0x1F) << 1 86define i8 @test11(i8 %x) { 87; CHECK-LABEL: @test11( 88; CHECK-NEXT: [[TMP1:%.*]] = mul i8 [[X:%.*]], 6 89; CHECK-NEXT: [[C:%.*]] = and i8 [[TMP1]], -16 90; CHECK-NEXT: ret i8 [[C]] 91; 92 %a = mul i8 %x, 3 93 %B = lshr i8 %a, 3 94 %C = shl i8 %B, 4 95 ret i8 %C 96} 97 98;; Allow the simplification in InstCombine when the lshr shift is exact. 99define i8 @test11a(i8 %A) { 100; CHECK-LABEL: @test11a( 101; CHECK-NEXT: [[C:%.*]] = mul i8 [[A:%.*]], 6 102; CHECK-NEXT: ret i8 [[C]] 103; 104 %a = mul i8 %A, 3 105 %B = lshr exact i8 %a, 3 106 %C = shl i8 %B, 4 107 ret i8 %C 108} 109 110;; (A >> 8) << 8 === A & -256 111define i32 @test12(i32 %A) { 112; CHECK-LABEL: @test12( 113; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -256 114; CHECK-NEXT: ret i32 [[TMP1]] 115; 116 %B = ashr i32 %A, 8 117 %C = shl i32 %B, 8 118 ret i32 %C 119} 120 121;; ((A >>s 6) << 6 === (A & FFFFFFC0) 122define i8 @shishi(i8 %x) { 123; CHECK-LABEL: @shishi( 124; CHECK-NEXT: [[A:%.*]] = ashr i8 [[X:%.*]], 6 125; CHECK-NEXT: [[B:%.*]] = and i8 [[X]], -64 126; CHECK-NEXT: [[EXTRA_USE_OF_A:%.*]] = mul nsw i8 [[A]], 5 127; CHECK-NEXT: [[R:%.*]] = sdiv i8 [[EXTRA_USE_OF_A]], [[B]] 128; CHECK-NEXT: ret i8 [[R]] 129; 130 %a = ashr i8 %x, 6 131 %b = shl i8 %a, 6 132 %extra_use_of_a = mul i8 %a, 5 133 %r = sdiv i8 %extra_use_of_a, %b 134 ret i8 %r 135} 136 137;; (A >> 3) << 4 === (A & -8) * 2 138define i8 @test13(i8 %x) { 139; CHECK-LABEL: @test13( 140; CHECK-NEXT: [[TMP1:%.*]] = mul i8 [[X:%.*]], 6 141; CHECK-NEXT: [[C:%.*]] = and i8 [[TMP1]], -16 142; CHECK-NEXT: ret i8 [[C]] 143; 144 %a = mul i8 %x, 3 145 %B = ashr i8 %a, 3 146 %C = shl i8 %B, 4 147 ret i8 %C 148} 149 150define i8 @test13a(i8 %A) { 151; CHECK-LABEL: @test13a( 152; CHECK-NEXT: [[C:%.*]] = mul i8 [[A:%.*]], 6 153; CHECK-NEXT: ret i8 [[C]] 154; 155 %a = mul i8 %A, 3 156 %B = ashr exact i8 %a, 3 157 %C = shl i8 %B, 4 158 ret i8 %C 159} 160 161;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4) 162define i32 @test14(i32 %A) { 163; CHECK-LABEL: @test14( 164; CHECK-NEXT: [[B:%.*]] = and i32 [[A:%.*]], -19760 165; CHECK-NEXT: [[C:%.*]] = or i32 [[B]], 19744 166; CHECK-NEXT: ret i32 [[C]] 167; 168 %B = lshr i32 %A, 4 169 %C = or i32 %B, 1234 170 %D = shl i32 %C, 4 171 ret i32 %D 172} 173 174;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4) 175define i32 @test14a(i32 %A) { 176; CHECK-LABEL: @test14a( 177; CHECK-NEXT: [[C:%.*]] = and i32 [[A:%.*]], 77 178; CHECK-NEXT: ret i32 [[C]] 179; 180 %B = shl i32 %A, 4 181 %C = and i32 %B, 1234 182 %D = lshr i32 %C, 4 183 ret i32 %D 184} 185 186define i32 @test15(i1 %C) { 187; CHECK-LABEL: @test15( 188; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], i32 12, i32 4 189; CHECK-NEXT: ret i32 [[A]] 190; 191 %A = select i1 %C, i32 3, i32 1 192 %V = shl i32 %A, 2 193 ret i32 %V 194} 195 196define i32 @test15a(i1 %C) { 197; CHECK-LABEL: @test15a( 198; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], i32 512, i32 128 199; CHECK-NEXT: ret i32 [[V]] 200; 201 %A = select i1 %C, i8 3, i8 1 202 %shift.upgrd.4 = zext i8 %A to i32 203 %V = shl i32 64, %shift.upgrd.4 204 ret i32 %V 205} 206 207define i1 @test16(i32 %X) { 208; CHECK-LABEL: @test16( 209; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 16 210; CHECK-NEXT: [[I_7:%.*]] = icmp ne i32 [[TMP1]], 0 211; CHECK-NEXT: ret i1 [[I_7]] 212; 213 %i.3 = ashr i32 %X, 4 214 %i.6 = and i32 %i.3, 1 215 %i.7 = icmp ne i32 %i.6, 0 216 ret i1 %i.7 217} 218 219define i1 @test17(i32 %A) { 220; CHECK-LABEL: @test17( 221; CHECK-NEXT: [[B_MASK:%.*]] = and i32 [[A:%.*]], -8 222; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[B_MASK]], 9872 223; CHECK-NEXT: ret i1 [[C]] 224; 225 %B = lshr i32 %A, 3 226 %C = icmp eq i32 %B, 1234 227 ret i1 %C 228} 229 230define <2 x i1> @test17vec(<2 x i32> %A) { 231; CHECK-LABEL: @test17vec( 232; CHECK-NEXT: [[B_MASK:%.*]] = and <2 x i32> [[A:%.*]], <i32 -8, i32 -8> 233; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i32> [[B_MASK]], <i32 9872, i32 9872> 234; CHECK-NEXT: ret <2 x i1> [[C]] 235; 236 %B = lshr <2 x i32> %A, <i32 3, i32 3> 237 %C = icmp eq <2 x i32> %B, <i32 1234, i32 1234> 238 ret <2 x i1> %C 239} 240 241define i1 @test18(i8 %A) { 242; CHECK-LABEL: @test18( 243; CHECK-NEXT: ret i1 false 244; 245 %B = lshr i8 %A, 7 246 ;; false 247 %C = icmp eq i8 %B, 123 248 ret i1 %C 249} 250 251define i1 @test19(i32 %A) { 252; CHECK-LABEL: @test19( 253; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A:%.*]], 4 254; CHECK-NEXT: ret i1 [[C]] 255; 256 %B = ashr i32 %A, 2 257 ;; (X & -4) == 0 258 %C = icmp eq i32 %B, 0 259 ret i1 %C 260} 261 262define <2 x i1> @test19vec(<2 x i32> %A) { 263; CHECK-LABEL: @test19vec( 264; CHECK-NEXT: [[C:%.*]] = icmp ult <2 x i32> [[A:%.*]], <i32 4, i32 4> 265; CHECK-NEXT: ret <2 x i1> [[C]] 266; 267 %B = ashr <2 x i32> %A, <i32 2, i32 2> 268 %C = icmp eq <2 x i32> %B, zeroinitializer 269 ret <2 x i1> %C 270} 271 272;; X >u ~4 273define i1 @test19a(i32 %A) { 274; CHECK-LABEL: @test19a( 275; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A:%.*]], -5 276; CHECK-NEXT: ret i1 [[C]] 277; 278 %B = ashr i32 %A, 2 279 %C = icmp eq i32 %B, -1 280 ret i1 %C 281} 282 283define <2 x i1> @test19a_vec(<2 x i32> %A) { 284; CHECK-LABEL: @test19a_vec( 285; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> [[A:%.*]], <i32 -5, i32 -5> 286; CHECK-NEXT: ret <2 x i1> [[C]] 287; 288 %B = ashr <2 x i32> %A, <i32 2, i32 2> 289 %C = icmp eq <2 x i32> %B, <i32 -1, i32 -1> 290 ret <2 x i1> %C 291} 292 293define i1 @test20(i8 %A) { 294; CHECK-LABEL: @test20( 295; CHECK-NEXT: ret i1 false 296; 297 %B = ashr i8 %A, 7 298 ;; false 299 %C = icmp eq i8 %B, 123 300 ret i1 %C 301} 302 303define i1 @test21(i8 %A) { 304; CHECK-LABEL: @test21( 305; CHECK-NEXT: [[B_MASK:%.*]] = and i8 [[A:%.*]], 15 306; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 8 307; CHECK-NEXT: ret i1 [[C]] 308; 309 %B = shl i8 %A, 4 310 %C = icmp eq i8 %B, -128 311 ret i1 %C 312} 313 314define i1 @test22(i8 %A) { 315; CHECK-LABEL: @test22( 316; CHECK-NEXT: [[B_MASK:%.*]] = and i8 [[A:%.*]], 15 317; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 0 318; CHECK-NEXT: ret i1 [[C]] 319; 320 %B = shl i8 %A, 4 321 %C = icmp eq i8 %B, 0 322 ret i1 %C 323} 324 325define i8 @test23(i32 %A) { 326; CHECK-LABEL: @test23( 327; CHECK-NEXT: [[D:%.*]] = trunc i32 [[A:%.*]] to i8 328; CHECK-NEXT: ret i8 [[D]] 329; 330 ;; casts not needed 331 %B = shl i32 %A, 24 332 %C = ashr i32 %B, 24 333 %D = trunc i32 %C to i8 334 ret i8 %D 335} 336 337define i8 @test24(i8 %X) { 338; CHECK-LABEL: @test24( 339; CHECK-NEXT: [[Z:%.*]] = and i8 [[X:%.*]], 3 340; CHECK-NEXT: ret i8 [[Z]] 341; 342 %Y = and i8 %X, -5 343 %Z = shl i8 %Y, 5 344 %Q = ashr i8 %Z, 5 345 ret i8 %Q 346} 347 348;; handle casts between shifts. 349define i32 @test26(i32 %A) { 350; CHECK-LABEL: @test26( 351; CHECK-NEXT: [[B:%.*]] = and i32 [[A:%.*]], -2 352; CHECK-NEXT: ret i32 [[B]] 353; 354 %B = lshr i32 %A, 1 355 %C = bitcast i32 %B to i32 356 %D = shl i32 %C, 1 357 ret i32 %D 358} 359 360 361define i1 @test27(i32 %x) nounwind { 362; CHECK-LABEL: @test27( 363; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 8 364; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[TMP1]], 0 365; CHECK-NEXT: ret i1 [[Z]] 366; 367 %y = lshr i32 %x, 3 368 %z = trunc i32 %y to i1 369 ret i1 %z 370} 371 372define i1 @test28(i8 %x) { 373; CHECK-LABEL: @test28( 374; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0 375; CHECK-NEXT: ret i1 [[CMP]] 376; 377 %shr = lshr i8 %x, 7 378 %cmp = icmp ne i8 %shr, 0 379 ret i1 %cmp 380} 381 382define <2 x i1> @test28vec(<2 x i8> %x) { 383; CHECK-LABEL: @test28vec( 384; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer 385; CHECK-NEXT: ret <2 x i1> [[CMP]] 386; 387 %shr = lshr <2 x i8> %x, <i8 7, i8 7> 388 %cmp = icmp ne <2 x i8> %shr, zeroinitializer 389 ret <2 x i1> %cmp 390} 391 392define i8 @test28a(i8 %x, i8 %y) { 393; CHECK-LABEL: @test28a( 394; CHECK-NEXT: entry: 395; CHECK-NEXT: [[I1:%.*]] = lshr i8 [[X:%.*]], 7 396; CHECK-NEXT: [[COND1_NOT:%.*]] = icmp sgt i8 [[X]], -1 397; CHECK-NEXT: br i1 [[COND1_NOT]], label [[BB2:%.*]], label [[BB1:%.*]] 398; CHECK: bb1: 399; CHECK-NEXT: ret i8 [[I1]] 400; CHECK: bb2: 401; CHECK-NEXT: [[I2:%.*]] = add i8 [[I1]], [[Y:%.*]] 402; CHECK-NEXT: ret i8 [[I2]] 403; 404entry: 405; This shouldn't be transformed. 406 %i1 = lshr i8 %x, 7 407 %cond1 = icmp ne i8 %i1, 0 408 br i1 %cond1, label %bb1, label %bb2 409bb1: 410 ret i8 %i1 411bb2: 412 %i2 = add i8 %i1, %y 413 ret i8 %i2 414} 415 416define i32 @test29(i64 %d18) { 417; CHECK-LABEL: @test29( 418; CHECK-NEXT: entry: 419; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i64 [[D18:%.*]], 63 420; CHECK-NEXT: [[I101:%.*]] = trunc i64 [[SUM_SHIFT]] to i32 421; CHECK-NEXT: ret i32 [[I101]] 422; 423entry: 424 %i916 = lshr i64 %d18, 32 425 %i917 = trunc i64 %i916 to i32 426 %i10 = lshr i32 %i917, 31 427 ret i32 %i10 428} 429 430define <2 x i32> @test29_uniform(<2 x i64> %d18) { 431; CHECK-LABEL: @test29_uniform( 432; CHECK-NEXT: entry: 433; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr <2 x i64> [[D18:%.*]], <i64 63, i64 63> 434; CHECK-NEXT: [[I101:%.*]] = trunc <2 x i64> [[SUM_SHIFT]] to <2 x i32> 435; CHECK-NEXT: ret <2 x i32> [[I101]] 436; 437entry: 438 %i916 = lshr <2 x i64> %d18, <i64 32, i64 32> 439 %i917 = trunc <2 x i64> %i916 to <2 x i32> 440 %i10 = lshr <2 x i32> %i917, <i32 31, i32 31> 441 ret <2 x i32> %i10 442} 443 444define <2 x i32> @test29_nonuniform(<2 x i64> %d18) { 445; CHECK-LABEL: @test29_nonuniform( 446; CHECK-NEXT: entry: 447; CHECK-NEXT: [[I916:%.*]] = lshr <2 x i64> [[D18:%.*]], <i64 32, i64 15> 448; CHECK-NEXT: [[I917:%.*]] = trunc <2 x i64> [[I916]] to <2 x i32> 449; CHECK-NEXT: [[I10:%.*]] = lshr <2 x i32> [[I917]], <i32 31, i32 22> 450; CHECK-NEXT: ret <2 x i32> [[I10]] 451; 452entry: 453 %i916 = lshr <2 x i64> %d18, <i64 32, i64 15> 454 %i917 = trunc <2 x i64> %i916 to <2 x i32> 455 %i10 = lshr <2 x i32> %i917, <i32 31, i32 22> 456 ret <2 x i32> %i10 457} 458 459define <2 x i32> @test29_undef(<2 x i64> %d18) { 460; CHECK-LABEL: @test29_undef( 461; CHECK-NEXT: entry: 462; CHECK-NEXT: [[I916:%.*]] = lshr <2 x i64> [[D18:%.*]], <i64 32, i64 undef> 463; CHECK-NEXT: [[I917:%.*]] = trunc <2 x i64> [[I916]] to <2 x i32> 464; CHECK-NEXT: [[I10:%.*]] = lshr <2 x i32> [[I917]], <i32 31, i32 undef> 465; CHECK-NEXT: ret <2 x i32> [[I10]] 466; 467entry: 468 %i916 = lshr <2 x i64> %d18, <i64 32, i64 undef> 469 %i917 = trunc <2 x i64> %i916 to <2 x i32> 470 %i10 = lshr <2 x i32> %i917, <i32 31, i32 undef> 471 ret <2 x i32> %i10 472} 473 474define i32 @test30(i32 %A, i32 %B, i32 %C) { 475; CHECK-LABEL: @test30( 476; CHECK-NEXT: [[X1:%.*]] = and i32 [[A:%.*]], [[B:%.*]] 477; CHECK-NEXT: [[Z:%.*]] = shl i32 [[X1]], [[C:%.*]] 478; CHECK-NEXT: ret i32 [[Z]] 479; 480 %X = shl i32 %A, %C 481 %Y = shl i32 %B, %C 482 %Z = and i32 %X, %Y 483 ret i32 %Z 484} 485 486define i32 @test31(i32 %A, i32 %B, i32 %C) { 487; CHECK-LABEL: @test31( 488; CHECK-NEXT: [[X1:%.*]] = or i32 [[A:%.*]], [[B:%.*]] 489; CHECK-NEXT: [[Z:%.*]] = lshr i32 [[X1]], [[C:%.*]] 490; CHECK-NEXT: ret i32 [[Z]] 491; 492 %X = lshr i32 %A, %C 493 %Y = lshr i32 %B, %C 494 %Z = or i32 %X, %Y 495 ret i32 %Z 496} 497 498define i32 @test32(i32 %A, i32 %B, i32 %C) { 499; CHECK-LABEL: @test32( 500; CHECK-NEXT: [[X1:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] 501; CHECK-NEXT: [[Z:%.*]] = ashr i32 [[X1]], [[C:%.*]] 502; CHECK-NEXT: ret i32 [[Z]] 503; 504 %X = ashr i32 %A, %C 505 %Y = ashr i32 %B, %C 506 %Z = xor i32 %X, %Y 507 ret i32 %Z 508} 509 510define i1 @test33(i32 %X) { 511; CHECK-LABEL: @test33( 512; CHECK-NEXT: [[I1_MASK:%.*]] = and i32 [[X:%.*]], 16777216 513; CHECK-NEXT: [[I2:%.*]] = icmp ne i32 [[I1_MASK]], 0 514; CHECK-NEXT: ret i1 [[I2]] 515; 516 %i1 = shl i32 %X, 7 517 %i2 = icmp slt i32 %i1, 0 518 ret i1 %i2 519} 520 521define <2 x i1> @test33vec(<2 x i32> %X) { 522; CHECK-LABEL: @test33vec( 523; CHECK-NEXT: [[I1_MASK:%.*]] = and <2 x i32> [[X:%.*]], <i32 16777216, i32 16777216> 524; CHECK-NEXT: [[I2:%.*]] = icmp ne <2 x i32> [[I1_MASK]], zeroinitializer 525; CHECK-NEXT: ret <2 x i1> [[I2]] 526; 527 %i1 = shl <2 x i32> %X, <i32 7, i32 7> 528 %i2 = icmp slt <2 x i32> %i1, zeroinitializer 529 ret <2 x i1> %i2 530} 531 532define i1 @test34(i32 %X) { 533; CHECK-LABEL: @test34( 534; CHECK-NEXT: ret i1 false 535; 536 %i1 = lshr i32 %X, 7 537 %i2 = icmp slt i32 %i1, 0 538 ret i1 %i2 539} 540 541define i1 @test35(i32 %X) { 542; CHECK-LABEL: @test35( 543; CHECK-NEXT: [[I2:%.*]] = icmp slt i32 [[X:%.*]], 0 544; CHECK-NEXT: ret i1 [[I2]] 545; 546 %i1 = ashr i32 %X, 7 547 %i2 = icmp slt i32 %i1, 0 548 ret i1 %i2 549} 550 551define <2 x i1> @test35vec(<2 x i32> %X) { 552; CHECK-LABEL: @test35vec( 553; CHECK-NEXT: [[I2:%.*]] = icmp slt <2 x i32> [[X:%.*]], zeroinitializer 554; CHECK-NEXT: ret <2 x i1> [[I2]] 555; 556 %i1 = ashr <2 x i32> %X, <i32 7, i32 7> 557 %i2 = icmp slt <2 x i32> %i1, zeroinitializer 558 ret <2 x i1> %i2 559} 560 561define i128 @test36(i128 %A, i128 %B) { 562; CHECK-LABEL: @test36( 563; CHECK-NEXT: [[I231:%.*]] = or i128 [[B:%.*]], [[A:%.*]] 564; CHECK-NEXT: [[INS:%.*]] = and i128 [[I231]], 18446744073709551615 565; CHECK-NEXT: ret i128 [[INS]] 566; 567 %i27 = shl i128 %A, 64 568 %i23 = shl i128 %B, 64 569 %ins = or i128 %i23, %i27 570 %i45 = lshr i128 %ins, 64 571 ret i128 %i45 572} 573 574define i64 @test37(i128 %A, i32 %B) { 575; CHECK-LABEL: @test37( 576; CHECK-NEXT: [[I22:%.*]] = zext i32 [[B:%.*]] to i128 577; CHECK-NEXT: [[I23:%.*]] = shl nuw nsw i128 [[I22]], 32 578; CHECK-NEXT: [[INS:%.*]] = or i128 [[I23]], [[A:%.*]] 579; CHECK-NEXT: [[I46:%.*]] = trunc i128 [[INS]] to i64 580; CHECK-NEXT: ret i64 [[I46]] 581; 582 %i27 = shl i128 %A, 64 583 %i22 = zext i32 %B to i128 584 %i23 = shl i128 %i22, 96 585 %ins = or i128 %i23, %i27 586 %i45 = lshr i128 %ins, 64 587 %i46 = trunc i128 %i45 to i64 588 ret i64 %i46 589} 590 591define <2 x i32> @shl_nuw_nsw_splat_vec(<2 x i8> %x) { 592; CHECK-LABEL: @shl_nuw_nsw_splat_vec( 593; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32> 594; CHECK-NEXT: [[T3:%.*]] = shl nuw nsw <2 x i32> [[T2]], <i32 17, i32 17> 595; CHECK-NEXT: ret <2 x i32> [[T3]] 596; 597 %t2 = zext <2 x i8> %x to <2 x i32> 598 %t3 = shl <2 x i32> %t2, <i32 17, i32 17> 599 ret <2 x i32> %t3 600} 601 602define i32 @test38(i32 %x) nounwind readnone { 603; CHECK-LABEL: @test38( 604; CHECK-NEXT: [[REM1:%.*]] = and i32 [[X:%.*]], 31 605; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[REM1]] 606; CHECK-NEXT: ret i32 [[SHL]] 607; 608 %rem = srem i32 %x, 32 609 %shl = shl i32 1, %rem 610 ret i32 %shl 611} 612 613define <2 x i32> @test38_uniform(<2 x i32> %x) nounwind readnone { 614; CHECK-LABEL: @test38_uniform( 615; CHECK-NEXT: [[REM1:%.*]] = and <2 x i32> [[X:%.*]], <i32 31, i32 31> 616; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[REM1]] 617; CHECK-NEXT: ret <2 x i32> [[SHL]] 618; 619 %rem = srem <2 x i32> %x, <i32 32, i32 32> 620 %shl = shl <2 x i32> <i32 1, i32 1>, %rem 621 ret <2 x i32> %shl 622} 623 624define <3 x i32> @test38_nonuniform(<3 x i32> %x) nounwind readnone { 625; CHECK-LABEL: @test38_nonuniform( 626; CHECK-NEXT: [[REM1:%.*]] = and <3 x i32> [[X:%.*]], <i32 31, i32 15, i32 0> 627; CHECK-NEXT: [[SHL:%.*]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[REM1]] 628; CHECK-NEXT: ret <3 x i32> [[SHL]] 629; 630 %rem = srem <3 x i32> %x, <i32 32, i32 16, i32 1> 631 %shl = shl <3 x i32> <i32 1, i32 1, i32 1>, %rem 632 ret <3 x i32> %shl 633} 634 635define <2 x i32> @test38_undef(<2 x i32> %x) nounwind readnone { 636; CHECK-LABEL: @test38_undef( 637; CHECK-NEXT: ret <2 x i32> poison 638; 639 %rem = srem <2 x i32> %x, <i32 32, i32 undef> 640 %shl = shl <2 x i32> <i32 1, i32 1>, %rem 641 ret <2 x i32> %shl 642} 643 644; <rdar://problem/8756731> 645define i8 @test39(i32 %a0) { 646; CHECK-LABEL: @test39( 647; CHECK-NEXT: entry: 648; CHECK-NEXT: [[I4:%.*]] = trunc i32 [[A0:%.*]] to i8 649; CHECK-NEXT: [[I5:%.*]] = shl i8 [[I4]], 5 650; CHECK-NEXT: [[I49:%.*]] = shl i8 [[I4]], 6 651; CHECK-NEXT: [[I50:%.*]] = and i8 [[I49]], 64 652; CHECK-NEXT: [[I51:%.*]] = xor i8 [[I50]], [[I5]] 653; CHECK-NEXT: [[TMP0:%.*]] = shl i8 [[I4]], 2 654; CHECK-NEXT: [[I54:%.*]] = and i8 [[TMP0]], 16 655; CHECK-NEXT: [[I551:%.*]] = or i8 [[I54]], [[I51]] 656; CHECK-NEXT: ret i8 [[I551]] 657; 658entry: 659 %i4 = trunc i32 %a0 to i8 660 %i5 = shl i8 %i4, 5 661 %i48 = and i8 %i5, 32 662 %i49 = lshr i8 %i48, 5 663 %i50 = mul i8 %i49, 64 664 %i51 = xor i8 %i50, %i5 665 %i52 = and i8 %i51, -128 666 %i53 = lshr i8 %i52, 7 667 %i54 = mul i8 %i53, 16 668 %i55 = xor i8 %i54, %i51 669 ret i8 %i55 670} 671 672; PR9809 673define i32 @test40(i32 %a, i32 %b) nounwind { 674; CHECK-LABEL: @test40( 675; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[B:%.*]], 2 676; CHECK-NEXT: [[DIV:%.*]] = lshr i32 [[A:%.*]], [[TMP1]] 677; CHECK-NEXT: ret i32 [[DIV]] 678; 679 %shl1 = shl i32 1, %b 680 %shl2 = shl i32 %shl1, 2 681 %div = udiv i32 %a, %shl2 682 ret i32 %div 683} 684 685define i32 @test41(i32 %a, i32 %b) nounwind { 686; CHECK-LABEL: @test41( 687; CHECK-NEXT: [[TMP1:%.*]] = shl i32 8, [[B:%.*]] 688; CHECK-NEXT: ret i32 [[TMP1]] 689; 690 %1 = shl i32 1, %b 691 %2 = shl i32 %1, 3 692 ret i32 %2 693} 694 695define i32 @test42(i32 %a, i32 %b) nounwind { 696; CHECK-LABEL: @test42( 697; CHECK-NEXT: [[DIV:%.*]] = lshr exact i32 4096, [[B:%.*]] 698; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 [[A:%.*]], [[DIV]] 699; CHECK-NEXT: ret i32 [[DIV2]] 700; 701 %div = lshr i32 4096, %b ; must be exact otherwise we'd divide by zero 702 %div2 = udiv i32 %a, %div 703 ret i32 %div2 704} 705 706define <2 x i32> @test42vec(<2 x i32> %a, <2 x i32> %b) { 707; CHECK-LABEL: @test42vec( 708; CHECK-NEXT: [[DIV:%.*]] = lshr exact <2 x i32> <i32 4096, i32 4096>, [[B:%.*]] 709; CHECK-NEXT: [[DIV2:%.*]] = udiv <2 x i32> [[A:%.*]], [[DIV]] 710; CHECK-NEXT: ret <2 x i32> [[DIV2]] 711; 712 %div = lshr <2 x i32> <i32 4096, i32 4096>, %b ; must be exact otherwise we'd divide by zero 713 %div2 = udiv <2 x i32> %a, %div 714 ret <2 x i32> %div2 715} 716 717define i32 @test43(i32 %a, i32 %b) nounwind { 718; CHECK-LABEL: @test43( 719; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[B:%.*]], 12 720; CHECK-NEXT: [[DIV2:%.*]] = lshr i32 [[A:%.*]], [[TMP1]] 721; CHECK-NEXT: ret i32 [[DIV2]] 722; 723 %div = shl i32 4096, %b ; must be exact otherwise we'd divide by zero 724 %div2 = udiv i32 %a, %div 725 ret i32 %div2 726} 727 728define i32 @test44(i32 %a) nounwind { 729; CHECK-LABEL: @test44( 730; CHECK-NEXT: [[Y:%.*]] = shl i32 [[A:%.*]], 5 731; CHECK-NEXT: ret i32 [[Y]] 732; 733 %y = shl nuw i32 %a, 1 734 %z = shl i32 %y, 4 735 ret i32 %z 736} 737 738define i32 @test45(i32 %a) nounwind { 739; CHECK-LABEL: @test45( 740; CHECK-NEXT: [[Y:%.*]] = lshr i32 [[A:%.*]], 5 741; CHECK-NEXT: ret i32 [[Y]] 742; 743 %y = lshr exact i32 %a, 1 744 %z = lshr i32 %y, 4 745 ret i32 %z 746} 747 748; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 749 750define i32 @test46(i32 %a) { 751; CHECK-LABEL: @test46( 752; CHECK-NEXT: [[Z:%.*]] = ashr exact i32 [[A:%.*]], 2 753; CHECK-NEXT: ret i32 [[Z]] 754; 755 %y = ashr exact i32 %a, 3 756 %z = shl i32 %y, 1 757 ret i32 %z 758} 759 760; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 761 762define <2 x i32> @test46_splat_vec(<2 x i32> %a) { 763; CHECK-LABEL: @test46_splat_vec( 764; CHECK-NEXT: [[Z:%.*]] = ashr exact <2 x i32> [[A:%.*]], <i32 2, i32 2> 765; CHECK-NEXT: ret <2 x i32> [[Z]] 766; 767 %y = ashr exact <2 x i32> %a, <i32 3, i32 3> 768 %z = shl <2 x i32> %y, <i32 1, i32 1> 769 ret <2 x i32> %z 770} 771 772; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 773 774define i8 @test47(i8 %a) { 775; CHECK-LABEL: @test47( 776; CHECK-NEXT: [[Z:%.*]] = lshr exact i8 [[A:%.*]], 2 777; CHECK-NEXT: ret i8 [[Z]] 778; 779 %y = lshr exact i8 %a, 3 780 %z = shl i8 %y, 1 781 ret i8 %z 782} 783 784; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 785 786define <2 x i8> @test47_splat_vec(<2 x i8> %a) { 787; CHECK-LABEL: @test47_splat_vec( 788; CHECK-NEXT: [[Z:%.*]] = lshr exact <2 x i8> [[A:%.*]], <i8 2, i8 2> 789; CHECK-NEXT: ret <2 x i8> [[Z]] 790; 791 %y = lshr exact <2 x i8> %a, <i8 3, i8 3> 792 %z = shl <2 x i8> %y, <i8 1, i8 1> 793 ret <2 x i8> %z 794} 795 796; (X >>u,exact C1) << C2 --> X << (C2-C1) when C2 > C1 797 798define i32 @test48(i32 %x) { 799; CHECK-LABEL: @test48( 800; CHECK-NEXT: [[B:%.*]] = shl i32 [[X:%.*]], 2 801; CHECK-NEXT: ret i32 [[B]] 802; 803 %A = lshr exact i32 %x, 1 804 %B = shl i32 %A, 3 805 ret i32 %B 806} 807 808; Verify that wrap flags are preserved from the original 'shl'. 809 810define i32 @test48_nuw_nsw(i32 %x) { 811; CHECK-LABEL: @test48_nuw_nsw( 812; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 [[X:%.*]], 2 813; CHECK-NEXT: ret i32 [[B]] 814; 815 %A = lshr exact i32 %x, 1 816 %B = shl nuw nsw i32 %A, 3 817 ret i32 %B 818} 819 820; (X >>u,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1 821 822define <2 x i32> @test48_splat_vec(<2 x i32> %x) { 823; CHECK-LABEL: @test48_splat_vec( 824; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> [[X:%.*]], <i32 2, i32 2> 825; CHECK-NEXT: ret <2 x i32> [[B]] 826; 827 %A = lshr exact <2 x i32> %x, <i32 1, i32 1> 828 %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3> 829 ret <2 x i32> %B 830} 831 832; (X >>s,exact C1) << C2 --> X << (C2-C1) when C2 > C1 833 834define i32 @test49(i32 %x) { 835; CHECK-LABEL: @test49( 836; CHECK-NEXT: [[B:%.*]] = shl i32 [[X:%.*]], 2 837; CHECK-NEXT: ret i32 [[B]] 838; 839 %A = ashr exact i32 %x, 1 840 %B = shl i32 %A, 3 841 ret i32 %B 842} 843 844; Verify that wrap flags are preserved from the original 'shl'. 845 846define i32 @test49_nuw_nsw(i32 %x) { 847; CHECK-LABEL: @test49_nuw_nsw( 848; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 [[X:%.*]], 2 849; CHECK-NEXT: ret i32 [[B]] 850; 851 %A = ashr exact i32 %x, 1 852 %B = shl nuw nsw i32 %A, 3 853 ret i32 %B 854} 855 856; (X >>s,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1 857 858define <2 x i32> @test49_splat_vec(<2 x i32> %x) { 859; CHECK-LABEL: @test49_splat_vec( 860; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> [[X:%.*]], <i32 2, i32 2> 861; CHECK-NEXT: ret <2 x i32> [[B]] 862; 863 %A = ashr exact <2 x i32> %x, <i32 1, i32 1> 864 %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3> 865 ret <2 x i32> %B 866} 867 868; (X <<nsw C1) >>s C2 --> X >>s (C2-C1) 869 870define i32 @test50(i32 %x) { 871; CHECK-LABEL: @test50( 872; CHECK-NEXT: [[B:%.*]] = ashr i32 [[X:%.*]], 2 873; CHECK-NEXT: ret i32 [[B]] 874; 875 %A = shl nsw i32 %x, 1 876 %B = ashr i32 %A, 3 877 ret i32 %B 878} 879 880; (X <<nsw C1) >>s C2 --> X >>s (C2-C1) 881; Also, check that exact is propagated. 882 883define <2 x i32> @test50_splat_vec(<2 x i32> %x) { 884; CHECK-LABEL: @test50_splat_vec( 885; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i32> [[X:%.*]], <i32 2, i32 2> 886; CHECK-NEXT: ret <2 x i32> [[B]] 887; 888 %A = shl nsw <2 x i32> %x, <i32 1, i32 1> 889 %B = ashr exact <2 x i32> %A, <i32 3, i32 3> 890 ret <2 x i32> %B 891} 892 893; (X <<nuw C1) >>u C2 --> X >>u (C2-C1) 894 895define i32 @test51(i32 %x) { 896; CHECK-LABEL: @test51( 897; CHECK-NEXT: [[B:%.*]] = lshr i32 [[X:%.*]], 2 898; CHECK-NEXT: ret i32 [[B]] 899; 900 %A = shl nuw i32 %x, 1 901 %B = lshr i32 %A, 3 902 ret i32 %B 903} 904 905; (X <<nuw C1) >>u C2 --> X >>u (C2-C1) with splats 906; Also, check that exact is propagated. 907 908define <2 x i32> @test51_splat_vec(<2 x i32> %x) { 909; CHECK-LABEL: @test51_splat_vec( 910; CHECK-NEXT: [[B:%.*]] = lshr exact <2 x i32> [[X:%.*]], <i32 2, i32 2> 911; CHECK-NEXT: ret <2 x i32> [[B]] 912; 913 %A = shl nuw <2 x i32> %x, <i32 1, i32 1> 914 %B = lshr exact <2 x i32> %A, <i32 3, i32 3> 915 ret <2 x i32> %B 916} 917 918; (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2) 919; Also, check that exact is propagated. 920 921define i32 @test51_no_nuw(i32 %x) { 922; CHECK-LABEL: @test51_no_nuw( 923; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[X:%.*]], 2 924; CHECK-NEXT: [[B:%.*]] = and i32 [[TMP1]], 536870911 925; CHECK-NEXT: ret i32 [[B]] 926; 927 %A = shl i32 %x, 1 928 %B = lshr exact i32 %A, 3 929 ret i32 %B 930} 931 932; (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2) 933 934define <2 x i32> @test51_no_nuw_splat_vec(<2 x i32> %x) { 935; CHECK-LABEL: @test51_no_nuw_splat_vec( 936; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 2, i32 2> 937; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[TMP1]], <i32 536870911, i32 536870911> 938; CHECK-NEXT: ret <2 x i32> [[B]] 939; 940 %A = shl <2 x i32> %x, <i32 1, i32 1> 941 %B = lshr <2 x i32> %A, <i32 3, i32 3> 942 ret <2 x i32> %B 943} 944 945; (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2) 946 947define i32 @test52(i32 %x) { 948; CHECK-LABEL: @test52( 949; CHECK-NEXT: [[B:%.*]] = shl nsw i32 [[X:%.*]], 2 950; CHECK-NEXT: ret i32 [[B]] 951; 952 %A = shl nsw i32 %x, 3 953 %B = ashr i32 %A, 1 954 ret i32 %B 955} 956 957; (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2) 958 959define <2 x i32> @test52_splat_vec(<2 x i32> %x) { 960; CHECK-LABEL: @test52_splat_vec( 961; CHECK-NEXT: [[B:%.*]] = shl nsw <2 x i32> [[X:%.*]], <i32 2, i32 2> 962; CHECK-NEXT: ret <2 x i32> [[B]] 963; 964 %A = shl nsw <2 x i32> %x, <i32 3, i32 3> 965 %B = ashr <2 x i32> %A, <i32 1, i32 1> 966 ret <2 x i32> %B 967} 968 969; (X <<nuw C1) >>u C2 --> X <<nuw (C1 - C2) 970 971define i32 @test53(i32 %x) { 972; CHECK-LABEL: @test53( 973; CHECK-NEXT: [[B:%.*]] = shl nuw i32 [[X:%.*]], 2 974; CHECK-NEXT: ret i32 [[B]] 975; 976 %A = shl nuw i32 %x, 3 977 %B = lshr i32 %A, 1 978 ret i32 %B 979} 980 981; (X <<nuw C1) >>u C2 --> X <<nuw (C1 - C2) 982 983define <2 x i32> @test53_splat_vec(<2 x i32> %x) { 984; CHECK-LABEL: @test53_splat_vec( 985; CHECK-NEXT: [[B:%.*]] = shl nuw <2 x i32> [[X:%.*]], <i32 2, i32 2> 986; CHECK-NEXT: ret <2 x i32> [[B]] 987; 988 %A = shl nuw <2 x i32> %x, <i32 3, i32 3> 989 %B = lshr <2 x i32> %A, <i32 1, i32 1> 990 ret <2 x i32> %B 991} 992 993; (X << C1) >>u C2 --> X << (C1 - C2) & (-1 >> C2) 994 995define i8 @test53_no_nuw(i8 %x) { 996; CHECK-LABEL: @test53_no_nuw( 997; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[X:%.*]], 2 998; CHECK-NEXT: [[B:%.*]] = and i8 [[TMP1]], 124 999; CHECK-NEXT: ret i8 [[B]] 1000; 1001 %A = shl i8 %x, 3 1002 %B = lshr i8 %A, 1 1003 ret i8 %B 1004} 1005 1006; (X << C1) >>u C2 --> X << (C1 - C2) & (-1 >> C2) 1007 1008define <2 x i8> @test53_no_nuw_splat_vec(<2 x i8> %x) { 1009; CHECK-LABEL: @test53_no_nuw_splat_vec( 1010; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i8> [[X:%.*]], <i8 2, i8 2> 1011; CHECK-NEXT: [[B:%.*]] = and <2 x i8> [[TMP1]], <i8 124, i8 124> 1012; CHECK-NEXT: ret <2 x i8> [[B]] 1013; 1014 %A = shl <2 x i8> %x, <i8 3, i8 3> 1015 %B = lshr <2 x i8> %A, <i8 1, i8 1> 1016 ret <2 x i8> %B 1017} 1018 1019define i32 @test54(i32 %x) { 1020; CHECK-LABEL: @test54( 1021; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3 1022; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP1]], 16 1023; CHECK-NEXT: ret i32 [[AND]] 1024; 1025 %shr2 = lshr i32 %x, 1 1026 %shl = shl i32 %shr2, 4 1027 %and = and i32 %shl, 16 1028 ret i32 %and 1029} 1030 1031define <2 x i32> @test54_splat_vec(<2 x i32> %x) { 1032; CHECK-LABEL: @test54_splat_vec( 1033; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 3, i32 3> 1034; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[TMP1]], <i32 16, i32 16> 1035; CHECK-NEXT: ret <2 x i32> [[AND]] 1036; 1037 %shr2 = lshr <2 x i32> %x, <i32 1, i32 1> 1038 %shl = shl <2 x i32> %shr2, <i32 4, i32 4> 1039 %and = and <2 x i32> %shl, <i32 16, i32 16> 1040 ret <2 x i32> %and 1041} 1042 1043define i32 @test55(i32 %x) { 1044; CHECK-LABEL: @test55( 1045; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3 1046; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 8 1047; CHECK-NEXT: ret i32 [[OR]] 1048; 1049 %shr2 = lshr i32 %x, 1 1050 %shl = shl i32 %shr2, 4 1051 %or = or i32 %shl, 8 1052 ret i32 %or 1053} 1054 1055define i32 @test56(i32 %x) { 1056; CHECK-LABEL: @test56( 1057; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3 1058; CHECK-NEXT: [[SHL:%.*]] = and i32 [[TMP1]], -16 1059; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7 1060; CHECK-NEXT: ret i32 [[OR]] 1061; 1062 %shr2 = lshr i32 %x, 1 1063 %shl = shl i32 %shr2, 4 1064 %or = or i32 %shl, 7 1065 ret i32 %or 1066} 1067 1068define i32 @test57(i32 %x) { 1069; CHECK-LABEL: @test57( 1070; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3 1071; CHECK-NEXT: [[SHL:%.*]] = and i32 [[TMP1]], -16 1072; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7 1073; CHECK-NEXT: ret i32 [[OR]] 1074; 1075 %shr = ashr i32 %x, 1 1076 %shl = shl i32 %shr, 4 1077 %or = or i32 %shl, 7 1078 ret i32 %or 1079} 1080 1081define i32 @test58(i32 %x) { 1082; CHECK-LABEL: @test58( 1083; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 3 1084; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 1 1085; CHECK-NEXT: ret i32 [[OR]] 1086; 1087 %shr = ashr i32 %x, 4 1088 %shl = shl i32 %shr, 1 1089 %or = or i32 %shl, 1 1090 ret i32 %or 1091} 1092 1093define <2 x i32> @test58_splat_vec(<2 x i32> %x) { 1094; CHECK-LABEL: @test58_splat_vec( 1095; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 3, i32 3> 1096; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[TMP1]], <i32 1, i32 1> 1097; CHECK-NEXT: ret <2 x i32> [[OR]] 1098; 1099 %shr = ashr <2 x i32> %x, <i32 4, i32 4> 1100 %shl = shl <2 x i32> %shr, <i32 1, i32 1> 1101 %or = or <2 x i32> %shl, <i32 1, i32 1> 1102 ret <2 x i32> %or 1103} 1104 1105define i32 @test59(i32 %x) { 1106; CHECK-LABEL: @test59( 1107; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 3 1108; CHECK-NEXT: [[SHL:%.*]] = and i32 [[TMP1]], -4 1109; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 2 1110; CHECK-NEXT: ret i32 [[OR]] 1111; 1112 %shr = ashr i32 %x, 4 1113 %shl = shl i32 %shr, 1 1114 %or = or i32 %shl, 2 1115 ret i32 %or 1116} 1117 1118; propagate "exact" trait 1119define i32 @test60(i32 %x) { 1120; CHECK-LABEL: @test60( 1121; CHECK-NEXT: [[SHL:%.*]] = ashr exact i32 [[X:%.*]], 3 1122; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 1 1123; CHECK-NEXT: ret i32 [[OR]] 1124; 1125 %shr = ashr exact i32 %x, 4 1126 %shl = shl i32 %shr, 1 1127 %or = or i32 %shl, 1 1128 ret i32 %or 1129} 1130 1131; PR17026 1132define void @test61(i128 %arg) { 1133; CHECK-LABEL: @test61( 1134; CHECK-NEXT: bb: 1135; CHECK-NEXT: br i1 undef, label [[BB1:%.*]], label [[BB12:%.*]] 1136; CHECK: bb1: 1137; CHECK-NEXT: br label [[BB2:%.*]] 1138; CHECK: bb2: 1139; CHECK-NEXT: br i1 undef, label [[BB3:%.*]], label [[BB7:%.*]] 1140; CHECK: bb3: 1141; CHECK-NEXT: br label [[BB8:%.*]] 1142; CHECK: bb7: 1143; CHECK-NEXT: br i1 undef, label [[BB8]], label [[BB2]] 1144; CHECK: bb8: 1145; CHECK-NEXT: br i1 undef, label [[BB11:%.*]], label [[BB12]] 1146; CHECK: bb11: 1147; CHECK-NEXT: br i1 undef, label [[BB1]], label [[BB12]] 1148; CHECK: bb12: 1149; CHECK-NEXT: ret void 1150; 1151bb: 1152 br i1 undef, label %bb1, label %bb12 1153 1154bb1: ; preds = %bb11, %bb 1155 br label %bb2 1156 1157bb2: ; preds = %bb7, %bb1 1158 br i1 undef, label %bb3, label %bb7 1159 1160bb3: ; preds = %bb2 1161 %i = lshr i128 %arg, 36893488147419103232 1162 %i4 = shl i128 %i, 0 1163 %i5 = or i128 %i4, undef 1164 %i6 = trunc i128 %i5 to i16 1165 br label %bb8 1166 1167bb7: ; preds = %bb2 1168 br i1 undef, label %bb8, label %bb2 1169 1170bb8: ; preds = %bb7, %bb3 1171 %i9 = phi i16 [ %i6, %bb3 ], [ undef, %bb7 ] 1172 %i10 = icmp eq i16 %i9, 0 1173 br i1 %i10, label %bb11, label %bb12 1174 1175bb11: ; preds = %bb8 1176 br i1 undef, label %bb1, label %bb12 1177 1178bb12: ; preds = %bb11, %bb8, %bb 1179 ret void 1180} 1181 1182define i32 @test62(i32 %a) { 1183; CHECK-LABEL: @test62( 1184; CHECK-NEXT: ret i32 poison 1185; 1186 %b = ashr i32 %a, 32 ; shift all bits out 1187 ret i32 %b 1188} 1189 1190define <4 x i32> @test62_splat_vector(<4 x i32> %a) { 1191; CHECK-LABEL: @test62_splat_vector( 1192; CHECK-NEXT: ret <4 x i32> poison 1193; 1194 %b = ashr <4 x i32> %a, <i32 32, i32 32, i32 32, i32 32> ; shift all bits out 1195 ret <4 x i32> %b 1196} 1197 1198define <4 x i32> @test62_non_splat_vector(<4 x i32> %a) { 1199; CHECK-LABEL: @test62_non_splat_vector( 1200; CHECK-NEXT: [[B:%.*]] = ashr <4 x i32> [[A:%.*]], <i32 32, i32 0, i32 1, i32 2> 1201; CHECK-NEXT: ret <4 x i32> [[B]] 1202; 1203 %b = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> ; shift all bits out 1204 ret <4 x i32> %b 1205} 1206 1207define <2 x i65> @test_63(<2 x i64> %t) { 1208; CHECK-LABEL: @test_63( 1209; CHECK-NEXT: [[A:%.*]] = zext <2 x i64> [[T:%.*]] to <2 x i65> 1210; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i65> [[A]], <i65 33, i65 33> 1211; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i65> [[SEXT]], <i65 33, i65 33> 1212; CHECK-NEXT: ret <2 x i65> [[B]] 1213; 1214 %a = zext <2 x i64> %t to <2 x i65> 1215 %sext = shl <2 x i65> %a, <i65 33, i65 33> 1216 %b = ashr <2 x i65> %sext, <i65 33, i65 33> 1217 ret <2 x i65> %b 1218} 1219 1220define i32 @test_shl_zext_bool(i1 %t) { 1221; CHECK-LABEL: @test_shl_zext_bool( 1222; CHECK-NEXT: [[SHL:%.*]] = select i1 [[T:%.*]], i32 4, i32 0 1223; CHECK-NEXT: ret i32 [[SHL]] 1224; 1225 %ext = zext i1 %t to i32 1226 %shl = shl i32 %ext, 2 1227 ret i32 %shl 1228} 1229 1230define <2 x i32> @test_shl_zext_bool_splat(<2 x i1> %t) { 1231; CHECK-LABEL: @test_shl_zext_bool_splat( 1232; CHECK-NEXT: [[SHL:%.*]] = select <2 x i1> [[T:%.*]], <2 x i32> <i32 8, i32 8>, <2 x i32> zeroinitializer 1233; CHECK-NEXT: ret <2 x i32> [[SHL]] 1234; 1235 %ext = zext <2 x i1> %t to <2 x i32> 1236 %shl = shl <2 x i32> %ext, <i32 3, i32 3> 1237 ret <2 x i32> %shl 1238} 1239 1240define <2 x i32> @test_shl_zext_bool_vec(<2 x i1> %t) { 1241; CHECK-LABEL: @test_shl_zext_bool_vec( 1242; CHECK-NEXT: [[SHL:%.*]] = select <2 x i1> [[T:%.*]], <2 x i32> <i32 4, i32 8>, <2 x i32> zeroinitializer 1243; CHECK-NEXT: ret <2 x i32> [[SHL]] 1244; 1245 %ext = zext <2 x i1> %t to <2 x i32> 1246 %shl = shl <2 x i32> %ext, <i32 2, i32 3> 1247 ret <2 x i32> %shl 1248} 1249 1250define i32 @test_shl_zext_bool_not_constant(i1 %cmp, i32 %shamt) { 1251; CHECK-LABEL: @test_shl_zext_bool_not_constant( 1252; CHECK-NEXT: [[CONV3:%.*]] = zext i1 [[CMP:%.*]] to i32 1253; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV3]], [[SHAMT:%.*]] 1254; CHECK-NEXT: ret i32 [[SHL]] 1255; 1256 %conv3 = zext i1 %cmp to i32 1257 %shl = shl i32 %conv3, %shamt 1258 ret i32 %shl 1259} 1260 1261define i64 @shl_zext(i32 %t) { 1262; CHECK-LABEL: @shl_zext( 1263; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[T:%.*]], 8 1264; CHECK-NEXT: [[SHL:%.*]] = zext i32 [[TMP1]] to i64 1265; CHECK-NEXT: ret i64 [[SHL]] 1266; 1267 %and = and i32 %t, 16777215 1268 %ext = zext i32 %and to i64 1269 %shl = shl i64 %ext, 8 1270 ret i64 %shl 1271} 1272 1273declare void @use(i64) 1274 1275define i64 @shl_zext_extra_use(i32 %t) { 1276; CHECK-LABEL: @shl_zext_extra_use( 1277; CHECK-NEXT: [[AND:%.*]] = and i32 [[T:%.*]], 16777215 1278; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[AND]] to i64 1279; CHECK-NEXT: call void @use(i64 [[EXT]]) 1280; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i64 [[EXT]], 8 1281; CHECK-NEXT: ret i64 [[SHL]] 1282; 1283 %and = and i32 %t, 16777215 1284 %ext = zext i32 %and to i64 1285 call void @use(i64 %ext) 1286 %shl = shl i64 %ext, 8 1287 ret i64 %shl 1288} 1289 1290 1291define <2 x i64> @shl_zext_splat_vec(<2 x i32> %t) { 1292; CHECK-LABEL: @shl_zext_splat_vec( 1293; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[T:%.*]], <i32 8, i32 8> 1294; CHECK-NEXT: [[SHL:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> 1295; CHECK-NEXT: ret <2 x i64> [[SHL]] 1296; 1297 %and = and <2 x i32> %t, <i32 16777215, i32 16777215> 1298 %ext = zext <2 x i32> %and to <2 x i64> 1299 %shl = shl <2 x i64> %ext, <i64 8, i64 8> 1300 ret <2 x i64> %shl 1301} 1302 1303define i64 @shl_zext_mul(i32 %t) { 1304; CHECK-LABEL: @shl_zext_mul( 1305; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215 1306; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64 1307; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[EXT]], 32 1308; CHECK-NEXT: ret i64 [[SHL]] 1309; 1310 %mul = mul i32 %t, 16777215 1311 %ext = zext i32 %mul to i64 1312 %shl = shl i64 %ext, 32 1313 ret i64 %shl 1314} 1315 1316define <3 x i17> @shl_zext_mul_splat(<3 x i5> %t) { 1317; CHECK-LABEL: @shl_zext_mul_splat( 1318; CHECK-NEXT: [[MUL:%.*]] = mul <3 x i5> [[T:%.*]], <i5 13, i5 13, i5 13> 1319; CHECK-NEXT: [[EXT:%.*]] = zext <3 x i5> [[MUL]] to <3 x i17> 1320; CHECK-NEXT: [[SHL:%.*]] = shl nuw <3 x i17> [[EXT]], <i17 12, i17 12, i17 12> 1321; CHECK-NEXT: ret <3 x i17> [[SHL]] 1322; 1323 %mul = mul <3 x i5> %t, <i5 13, i5 13, i5 13> 1324 %ext = zext <3 x i5> %mul to <3 x i17> 1325 %shl = shl <3 x i17> %ext, <i17 12, i17 12, i17 12> 1326 ret <3 x i17> %shl 1327} 1328 1329define i64 @shl_zext_mul_low_shift_amount(i32 %t) { 1330; CHECK-LABEL: @shl_zext_mul_low_shift_amount( 1331; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215 1332; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64 1333; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i64 [[EXT]], 31 1334; CHECK-NEXT: ret i64 [[SHL]] 1335; 1336 %mul = mul i32 %t, 16777215 1337 %ext = zext i32 %mul to i64 1338 %shl = shl i64 %ext, 31 1339 ret i64 %shl 1340} 1341 1342define i64 @shl_zext_mul_extra_use1(i32 %t) { 1343; CHECK-LABEL: @shl_zext_mul_extra_use1( 1344; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215 1345; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64 1346; CHECK-NEXT: call void @use(i64 [[EXT]]) 1347; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[EXT]], 32 1348; CHECK-NEXT: ret i64 [[SHL]] 1349; 1350 %mul = mul i32 %t, 16777215 1351 %ext = zext i32 %mul to i64 1352 call void @use(i64 %ext) 1353 %shl = shl i64 %ext, 32 1354 ret i64 %shl 1355} 1356 1357declare void @use_i32(i32) 1358 1359define i64 @shl_zext_mul_extra_use2(i32 %t) { 1360; CHECK-LABEL: @shl_zext_mul_extra_use2( 1361; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215 1362; CHECK-NEXT: call void @use_i32(i32 [[MUL]]) 1363; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64 1364; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[EXT]], 32 1365; CHECK-NEXT: ret i64 [[SHL]] 1366; 1367 %mul = mul i32 %t, 16777215 1368 call void @use_i32(i32 %mul) 1369 %ext = zext i32 %mul to i64 1370 %shl = shl i64 %ext, 32 1371 ret i64 %shl 1372} 1373 1374define <2 x i8> @ashr_demanded_bits_splat(<2 x i8> %x) { 1375; CHECK-LABEL: @ashr_demanded_bits_splat( 1376; CHECK-NEXT: [[SHR:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 7, i8 7> 1377; CHECK-NEXT: ret <2 x i8> [[SHR]] 1378; 1379 %and = and <2 x i8> %x, <i8 128, i8 128> 1380 %shr = ashr <2 x i8> %and, <i8 7, i8 7> 1381 ret <2 x i8> %shr 1382} 1383 1384define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) { 1385; CHECK-LABEL: @lshr_demanded_bits_splat( 1386; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 7, i8 7> 1387; CHECK-NEXT: ret <2 x i8> [[SHR]] 1388; 1389 %and = and <2 x i8> %x, <i8 128, i8 128> 1390 %shr = lshr <2 x i8> %and, <i8 7, i8 7> 1391 ret <2 x i8> %shr 1392} 1393 1394; Make sure known bits works correctly with non power of 2 bit widths. 1395define i7 @test65(i7 %a, i7 %b) { 1396; CHECK-LABEL: @test65( 1397; CHECK-NEXT: ret i7 0 1398; 1399 %shiftamt = and i7 %b, 6 ; this ensures the shift amount is even and less than the bit width. 1400 %x = lshr i7 42, %shiftamt ; 42 has a zero in every even numbered bit and a one in every odd bit. 1401 %y = and i7 %x, 1 ; this extracts the lsb which should be 0 because we shifted an even number of bits and all even bits of the shift input are 0. 1402 ret i7 %y 1403} 1404 1405define i32 @shl_select_add_true(i32 %x, i1 %cond) { 1406; CHECK-LABEL: @shl_select_add_true( 1407; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1408; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14 1409; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1410; CHECK-NEXT: ret i32 [[TMP3]] 1411; 1412 %1 = add i32 %x, 7 1413 %2 = select i1 %cond, i32 %1, i32 %x 1414 %3 = shl i32 %2, 1 1415 ret i32 %3 1416} 1417 1418define i32 @shl_select_add_false(i32 %x, i1 %cond) { 1419; CHECK-LABEL: @shl_select_add_false( 1420; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1421; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14 1422; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1423; CHECK-NEXT: ret i32 [[TMP3]] 1424; 1425 %1 = add i32 %x, 7 1426 %2 = select i1 %cond, i32 %x, i32 %1 1427 %3 = shl i32 %2, 1 1428 ret i32 %3 1429} 1430 1431define i32 @shl_select_and_true(i32 %x, i1 %cond) { 1432; CHECK-LABEL: @shl_select_and_true( 1433; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1434; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14 1435; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1436; CHECK-NEXT: ret i32 [[TMP3]] 1437; 1438 %1 = and i32 %x, 7 1439 %2 = select i1 %cond, i32 %1, i32 %x 1440 %3 = shl i32 %2, 1 1441 ret i32 %3 1442} 1443 1444define i32 @shl_select_and_false(i32 %x, i1 %cond) { 1445; CHECK-LABEL: @shl_select_and_false( 1446; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1447; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14 1448; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1449; CHECK-NEXT: ret i32 [[TMP3]] 1450; 1451 %1 = and i32 %x, 7 1452 %2 = select i1 %cond, i32 %x, i32 %1 1453 %3 = shl i32 %2, 1 1454 ret i32 %3 1455} 1456 1457define i32 @lshr_select_and_true(i32 %x, i1 %cond) { 1458; CHECK-LABEL: @lshr_select_and_true( 1459; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1460; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3 1461; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1462; CHECK-NEXT: ret i32 [[TMP3]] 1463; 1464 %1 = and i32 %x, 7 1465 %2 = select i1 %cond, i32 %1, i32 %x 1466 %3 = lshr i32 %2, 1 1467 ret i32 %3 1468} 1469 1470define i32 @lshr_select_and_false(i32 %x, i1 %cond) { 1471; CHECK-LABEL: @lshr_select_and_false( 1472; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1473; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3 1474; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1475; CHECK-NEXT: ret i32 [[TMP3]] 1476; 1477 %1 = and i32 %x, 7 1478 %2 = select i1 %cond, i32 %x, i32 %1 1479 %3 = lshr i32 %2, 1 1480 ret i32 %3 1481} 1482 1483define i32 @ashr_select_and_true(i32 %x, i1 %cond) { 1484; CHECK-LABEL: @ashr_select_and_true( 1485; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1486; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821 1487; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1488; CHECK-NEXT: ret i32 [[TMP3]] 1489; 1490 %1 = and i32 %x, 2147483655 1491 %2 = select i1 %cond, i32 %1, i32 %x 1492 %3 = ashr i32 %2, 1 1493 ret i32 %3 1494} 1495 1496define i32 @ashr_select_and_false(i32 %x, i1 %cond) { 1497; CHECK-LABEL: @ashr_select_and_false( 1498; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1499; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821 1500; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1501; CHECK-NEXT: ret i32 [[TMP3]] 1502; 1503 %1 = and i32 %x, 2147483655 1504 %2 = select i1 %cond, i32 %x, i32 %1 1505 %3 = ashr i32 %2, 1 1506 ret i32 %3 1507} 1508 1509define i32 @shl_select_or_true(i32 %x, i1 %cond) { 1510; CHECK-LABEL: @shl_select_or_true( 1511; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1512; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14 1513; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1514; CHECK-NEXT: ret i32 [[TMP3]] 1515; 1516 %1 = or i32 %x, 7 1517 %2 = select i1 %cond, i32 %1, i32 %x 1518 %3 = shl i32 %2, 1 1519 ret i32 %3 1520} 1521 1522define i32 @shl_select_or_false(i32 %x, i1 %cond) { 1523; CHECK-LABEL: @shl_select_or_false( 1524; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1525; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14 1526; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1527; CHECK-NEXT: ret i32 [[TMP3]] 1528; 1529 %1 = or i32 %x, 7 1530 %2 = select i1 %cond, i32 %x, i32 %1 1531 %3 = shl i32 %2, 1 1532 ret i32 %3 1533} 1534 1535define i32 @lshr_select_or_true(i32 %x, i1 %cond) { 1536; CHECK-LABEL: @lshr_select_or_true( 1537; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1538; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1539; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1540; CHECK-NEXT: ret i32 [[TMP3]] 1541; 1542 %1 = or i32 %x, 7 1543 %2 = select i1 %cond, i32 %1, i32 %x 1544 %3 = lshr i32 %2, 1 1545 ret i32 %3 1546} 1547 1548define i32 @lshr_select_or_false(i32 %x, i1 %cond) { 1549; CHECK-LABEL: @lshr_select_or_false( 1550; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1551; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1552; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1553; CHECK-NEXT: ret i32 [[TMP3]] 1554; 1555 %1 = or i32 %x, 7 1556 %2 = select i1 %cond, i32 %x, i32 %1 1557 %3 = lshr i32 %2, 1 1558 ret i32 %3 1559} 1560 1561define i32 @ashr_select_or_true(i32 %x, i1 %cond) { 1562; CHECK-LABEL: @ashr_select_or_true( 1563; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1564; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1565; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1566; CHECK-NEXT: ret i32 [[TMP3]] 1567; 1568 %1 = or i32 %x, 7 1569 %2 = select i1 %cond, i32 %1, i32 %x 1570 %3 = ashr i32 %2, 1 1571 ret i32 %3 1572} 1573 1574define i32 @ashr_select_or_false(i32 %x, i1 %cond) { 1575; CHECK-LABEL: @ashr_select_or_false( 1576; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1577; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1578; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1579; CHECK-NEXT: ret i32 [[TMP3]] 1580; 1581 %1 = or i32 %x, 7 1582 %2 = select i1 %cond, i32 %x, i32 %1 1583 %3 = ashr i32 %2, 1 1584 ret i32 %3 1585} 1586 1587define i32 @shl_select_xor_true(i32 %x, i1 %cond) { 1588; CHECK-LABEL: @shl_select_xor_true( 1589; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1590; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14 1591; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1592; CHECK-NEXT: ret i32 [[TMP3]] 1593; 1594 %1 = xor i32 %x, 7 1595 %2 = select i1 %cond, i32 %1, i32 %x 1596 %3 = shl i32 %2, 1 1597 ret i32 %3 1598} 1599 1600define i32 @shl_select_xor_false(i32 %x, i1 %cond) { 1601; CHECK-LABEL: @shl_select_xor_false( 1602; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1603; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14 1604; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1605; CHECK-NEXT: ret i32 [[TMP3]] 1606; 1607 %1 = xor i32 %x, 7 1608 %2 = select i1 %cond, i32 %x, i32 %1 1609 %3 = shl i32 %2, 1 1610 ret i32 %3 1611} 1612 1613define i32 @lshr_select_xor_true(i32 %x, i1 %cond) { 1614; CHECK-LABEL: @lshr_select_xor_true( 1615; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1616; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1617; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1618; CHECK-NEXT: ret i32 [[TMP3]] 1619; 1620 %1 = xor i32 %x, 7 1621 %2 = select i1 %cond, i32 %1, i32 %x 1622 %3 = lshr i32 %2, 1 1623 ret i32 %3 1624} 1625 1626define i32 @lshr_select_xor_false(i32 %x, i1 %cond) { 1627; CHECK-LABEL: @lshr_select_xor_false( 1628; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1629; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1630; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1631; CHECK-NEXT: ret i32 [[TMP3]] 1632; 1633 %1 = xor i32 %x, 7 1634 %2 = select i1 %cond, i32 %x, i32 %1 1635 %3 = lshr i32 %2, 1 1636 ret i32 %3 1637} 1638 1639define i32 @ashr_select_xor_true(i32 %x, i1 %cond) { 1640; CHECK-LABEL: @ashr_select_xor_true( 1641; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1642; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1643; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1644; CHECK-NEXT: ret i32 [[TMP3]] 1645; 1646 %1 = xor i32 %x, 7 1647 %2 = select i1 %cond, i32 %1, i32 %x 1648 %3 = ashr i32 %2, 1 1649 ret i32 %3 1650} 1651 1652define i32 @ashr_select_xor_false(i32 %x, i1 %cond) { 1653; CHECK-LABEL: @ashr_select_xor_false( 1654; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1655; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1656; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1657; CHECK-NEXT: ret i32 [[TMP3]] 1658; 1659 %1 = xor i32 %x, 7 1660 %2 = select i1 %cond, i32 %x, i32 %1 1661 %3 = ashr i32 %2, 1 1662 ret i32 %3 1663} 1664 1665; OSS Fuzz #4871 1666; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=4871 1667define i177 @lshr_out_of_range(i177 %Y, i177** %A2) { 1668; CHECK-LABEL: @lshr_out_of_range( 1669; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i177 [[Y:%.*]], -1 1670; CHECK-NEXT: [[B4:%.*]] = sext i1 [[TMP1]] to i177 1671; CHECK-NEXT: [[C8:%.*]] = icmp ult i177 [[B4]], [[Y]] 1672; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[C8]] to i64 1673; CHECK-NEXT: [[G18:%.*]] = getelementptr i177*, i177** [[A2:%.*]], i64 [[TMP2]] 1674; CHECK-NEXT: store i177** [[G18]], i177*** undef, align 8 1675; CHECK-NEXT: ret i177 0 1676; 1677 %B5 = udiv i177 %Y, -1 1678 %B4 = add i177 %B5, -1 1679 %B2 = add i177 %B4, -1 1680 %B6 = mul i177 %B5, %B2 1681 %B3 = add i177 %B2, %B2 1682 %B10 = sub i177 %B5, %B3 1683 %B12 = lshr i177 %Y, %B6 1684 %C8 = icmp ugt i177 %B12, %B4 1685 %G18 = getelementptr i177*, i177** %A2, i1 %C8 1686 store i177** %G18, i177*** undef 1687 %B1 = udiv i177 %B10, %B6 1688 ret i177 %B1 1689} 1690 1691; OSS Fuzz #26716 1692; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=26716 1693define i177 @lshr_out_of_range2(i177 %Y, i177** %A2) { 1694; CHECK-LABEL: @lshr_out_of_range2( 1695; CHECK-NEXT: ret i177 0 1696; 1697 %B5 = udiv i177 %Y, -1 1698 %B = sdiv i177 %B5, -1 1699 %B4 = add i177 %B5, %B 1700 %B2 = add i177 %B4, -1 1701 %B6 = mul i177 %B5, %B2 1702 %B12 = lshr i177 %Y, %B6 1703 %C8 = icmp ugt i177 %B12, %B4 1704 %G18 = getelementptr i177*, i177** %A2, i1 %C8 1705 store i177** %G18, i177*** undef, align 8 1706 %B1 = udiv i177 %B5, %B6 1707 ret i177 %B1 1708} 1709 1710; OSS Fuzz #5032 1711; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=5032 1712define void @ashr_out_of_range(i177* %A) { 1713; CHECK-LABEL: @ashr_out_of_range( 1714; CHECK-NEXT: [[L:%.*]] = load i177, i177* [[A:%.*]], align 4 1715; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i177 [[L]], -1 1716; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i64 -1, i64 -2 1717; CHECK-NEXT: [[G11:%.*]] = getelementptr i177, i177* [[A]], i64 [[TMP2]] 1718; CHECK-NEXT: [[L7:%.*]] = load i177, i177* [[G11]], align 4 1719; CHECK-NEXT: [[B36:%.*]] = select i1 [[TMP1]], i177 0, i177 [[L7]] 1720; CHECK-NEXT: [[C17:%.*]] = icmp sgt i177 [[B36]], [[L7]] 1721; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[C17]] to i64 1722; CHECK-NEXT: [[G62:%.*]] = getelementptr i177, i177* [[G11]], i64 [[TMP3]] 1723; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i177 [[L7]], -1 1724; CHECK-NEXT: [[B28:%.*]] = select i1 [[TMP4]], i177 0, i177 [[L7]] 1725; CHECK-NEXT: store i177 [[B28]], i177* [[G62]], align 4 1726; CHECK-NEXT: ret void 1727; 1728 %L = load i177, i177* %A 1729 %B5 = udiv i177 %L, -1 1730 %B4 = add i177 %B5, -1 1731 %B2 = add i177 %B4, -1 1732 %G11 = getelementptr i177, i177* %A, i177 %B2 1733 %L7 = load i177, i177* %G11 1734 %B6 = mul i177 %B5, %B2 1735 %B24 = ashr i177 %L7, %B6 1736 %B36 = and i177 %L7, %B4 1737 %C17 = icmp sgt i177 %B36, %B24 1738 %G62 = getelementptr i177, i177* %G11, i1 %C17 1739 %B28 = urem i177 %B24, %B6 1740 store i177 %B28, i177* %G62 1741 ret void 1742} 1743 1744; OSS Fuzz #26135 1745; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=26135 1746define void @ashr_out_of_range_1(i177* %A) { 1747; CHECK-LABEL: @ashr_out_of_range_1( 1748; CHECK-NEXT: [[L:%.*]] = load i177, i177* [[A:%.*]], align 4 1749; CHECK-NEXT: [[G11:%.*]] = getelementptr i177, i177* [[A]], i64 -1 1750; CHECK-NEXT: [[B24_LOBIT:%.*]] = ashr i177 [[L]], 175 1751; CHECK-NEXT: [[TMP1:%.*]] = trunc i177 [[B24_LOBIT]] to i64 1752; CHECK-NEXT: [[G62:%.*]] = getelementptr i177, i177* [[G11]], i64 [[TMP1]] 1753; CHECK-NEXT: store i177 0, i177* [[G62]], align 4 1754; CHECK-NEXT: ret void 1755; 1756 %L = load i177, i177* %A, align 4 1757 %B5 = udiv i177 %L, -1 1758 %B4 = add i177 %B5, -1 1759 %B = and i177 %B4, %L 1760 %B2 = add i177 %B, -1 1761 %G11 = getelementptr i177, i177* %A, i177 %B2 1762 %B6 = mul i177 %B5, %B2 1763 %B24 = ashr i177 %L, %B6 1764 %C17 = icmp sgt i177 %B, %B24 1765 %G62 = getelementptr i177, i177* %G11, i1 %C17 1766 %B28 = urem i177 %B24, %B6 1767 store i177 %B28, i177* %G62, align 4 1768 ret void 1769} 1770 1771; OSS Fuzz #38078 1772; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=38078 1773define void @ossfuzz_38078(i32 %arg, i32 %arg1) { 1774; CHECK-LABEL: @ossfuzz_38078( 1775; CHECK-NEXT: bb: 1776; CHECK-NEXT: [[I2:%.*]] = sub i32 0, [[ARG1:%.*]] 1777; CHECK-NEXT: [[I5:%.*]] = icmp eq i32 [[I2]], [[ARG:%.*]] 1778; CHECK-NEXT: call void @llvm.assume(i1 [[I5]]) 1779; CHECK-NEXT: store volatile i32 undef, i32* undef, align 4 1780; CHECK-NEXT: br label [[BB:%.*]] 1781; CHECK: BB: 1782; CHECK-NEXT: unreachable 1783; 1784bb: 1785 %i = or i32 0, -1 1786 %B24 = urem i32 %i, -2147483648 1787 %B21 = or i32 %i, %i 1788 %i2 = add nsw i32 %arg, %arg1 1789 %B7 = or i32 %i, %i2 1790 %B8 = and i32 %i, %i2 1791 %B12 = sdiv i32 %i2, %B7 1792 %B3 = add i32 %i2, %B24 1793 %B5 = and i32 %i, %B3 1794 %B18 = and i32 %i, %B8 1795 %i3 = xor i32 %i2, %B3 1796 %C1 = icmp ne i32 %B8, %B5 1797 %i4 = lshr i32 %B5, %i3 1798 %B29 = shl nuw i32 %B8, %i3 1799 %B2 = lshr i32 %B12, %i2 1800 %B16 = add i32 %B2, %i3 1801 %B = sdiv i32 %B29, %B5 1802 %B15 = sub i32 %i2, %B5 1803 %B22 = or i32 %B21, %B29 1804 %B23 = mul i32 %B15, %B 1805 %C2 = icmp sge i1 %C1, false 1806 %C7 = icmp sle i32 %i3, %B16 1807 %B20 = xor i32 %B21, %B22 1808 %G1 = getelementptr i32, i32* undef, i32 %B22 1809 %B1 = sub i32 %B, undef 1810 %B26 = ashr i32 %B29, undef 1811 %B4 = add i32 undef, %B5 1812 %B27 = srem i32 %B12, %B21 1813 %i5 = icmp eq i32 %B20, %B18 1814 %C11 = icmp ugt i32 %i4, %B4 1815 call void @llvm.assume(i1 %i5) 1816 store volatile i32 %B4, i32* %G1, align 4 1817 %B11 = or i32 undef, %B23 1818 br label %BB 1819 1820BB: 1821 store i1 %C7, i1* undef, align 1 1822 store i32 %B11, i32* undef, align 4 1823 store i1 %C11, i1* undef, align 1 1824 store i32 %B1, i32* undef, align 4 1825 store i32 %B27, i32* undef, align 4 1826 %C = icmp ne i32 %B26, undef 1827 %B17 = or i1 %C, %C2 1828 store i1 %B17, i1* undef, align 1 1829 unreachable 1830} 1831declare void @llvm.assume(i1 noundef) 1832 1833define i8 @lshr_mask_demand(i8 %x) { 1834; CHECK-LABEL: @lshr_mask_demand( 1835; CHECK-NEXT: [[S:%.*]] = lshr i8 63, [[X:%.*]] 1836; CHECK-NEXT: [[R:%.*]] = and i8 [[S]], 32 1837; CHECK-NEXT: ret i8 [[R]] 1838; 1839 %s = lshr i8 63, %x ; 0b00111111 1840 %r = and i8 %s, 224 ; 0b11100000 1841 ret i8 %r 1842} 1843 1844define i8 @shl_mask_demand(i8 %x) { 1845; CHECK-LABEL: @shl_mask_demand( 1846; CHECK-NEXT: [[S:%.*]] = shl i8 12, [[X:%.*]] 1847; CHECK-NEXT: [[R:%.*]] = and i8 [[S]], 4 1848; CHECK-NEXT: ret i8 [[R]] 1849; 1850 %s = shl i8 12, %x ; 0b00001100 1851 %r = and i8 %s, 7 ; 0b00000111 1852 ret i8 %r 1853} 1854