1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instcombine -S | FileCheck %s 3 4define i32 @test1(i32 %A) { 5; CHECK-LABEL: @test1( 6; CHECK-NEXT: ret i32 %A 7; 8 %B = shl i32 %A, 0 9 ret i32 %B 10} 11 12define i32 @test2(i8 %A) { 13; CHECK-LABEL: @test2( 14; CHECK-NEXT: ret i32 0 15; 16 %shift.upgrd.1 = zext i8 %A to i32 17 %B = shl i32 0, %shift.upgrd.1 18 ret i32 %B 19} 20 21define i32 @test3(i32 %A) { 22; CHECK-LABEL: @test3( 23; CHECK-NEXT: ret i32 %A 24; 25 %B = ashr i32 %A, 0 26 ret i32 %B 27} 28 29define i32 @test4(i8 %A) { 30; CHECK-LABEL: @test4( 31; CHECK-NEXT: ret i32 0 32; 33 %shift.upgrd.2 = zext i8 %A to i32 34 %B = ashr i32 0, %shift.upgrd.2 35 ret i32 %B 36} 37 38define i32 @test5(i32 %A) { 39; CHECK-LABEL: @test5( 40; CHECK-NEXT: ret i32 undef 41; 42 %B = lshr i32 %A, 32 ;; shift all bits out 43 ret i32 %B 44} 45 46define <4 x i32> @test5_splat_vector(<4 x i32> %A) { 47; CHECK-LABEL: @test5_splat_vector( 48; CHECK-NEXT: ret <4 x i32> undef 49; 50 %B = lshr <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out 51 ret <4 x i32> %B 52} 53 54define <4 x i32> @test5_zero_vector(<4 x i32> %A) { 55; CHECK-LABEL: @test5_zero_vector( 56; CHECK-NEXT: ret <4 x i32> %A 57; 58 %B = lshr <4 x i32> %A, zeroinitializer 59 ret <4 x i32> %B 60} 61 62define <4 x i32> @test5_non_splat_vector(<4 x i32> %A) { 63; CHECK-LABEL: @test5_non_splat_vector( 64; CHECK-NEXT: [[B:%.*]] = lshr <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 65; CHECK-NEXT: ret <4 x i32> [[B]] 66; 67 %B = lshr <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 68 ret <4 x i32> %B 69} 70 71define i32 @test5a(i32 %A) { 72; CHECK-LABEL: @test5a( 73; CHECK-NEXT: ret i32 undef 74; 75 %B = shl i32 %A, 32 ;; shift all bits out 76 ret i32 %B 77} 78 79define <4 x i32> @test5a_splat_vector(<4 x i32> %A) { 80; CHECK-LABEL: @test5a_splat_vector( 81; CHECK-NEXT: ret <4 x i32> undef 82; 83 %B = shl <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out 84 ret <4 x i32> %B 85} 86 87define <4 x i32> @test5a_non_splat_vector(<4 x i32> %A) { 88; CHECK-LABEL: @test5a_non_splat_vector( 89; CHECK-NEXT: [[B:%.*]] = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 90; CHECK-NEXT: ret <4 x i32> [[B]] 91; 92 %B = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 93 ret <4 x i32> %B 94} 95 96define i32 @test5b() { 97; CHECK-LABEL: @test5b( 98; CHECK-NEXT: ret i32 0 99; 100 %B = ashr i32 undef, 2 ;; top two bits must be equal, so not undef 101 ret i32 %B 102} 103 104define i32 @test5b2(i32 %A) { 105; CHECK-LABEL: @test5b2( 106; CHECK-NEXT: ret i32 0 107; 108 %B = ashr i32 undef, %A ;; top %A bits must be equal, so not undef 109 ret i32 %B 110} 111 112define i32 @test6(i32 %A) { 113; CHECK-LABEL: @test6( 114; CHECK-NEXT: [[C:%.*]] = mul i32 %A, 6 115; CHECK-NEXT: ret i32 [[C]] 116; 117 %B = shl i32 %A, 1 ;; convert to an mul instruction 118 %C = mul i32 %B, 3 119 ret i32 %C 120} 121 122define i32 @test6a(i32 %A) { 123; CHECK-LABEL: @test6a( 124; CHECK-NEXT: [[C:%.*]] = mul i32 %A, 6 125; CHECK-NEXT: ret i32 [[C]] 126; 127 %B = mul i32 %A, 3 128 %C = shl i32 %B, 1 ;; convert to an mul instruction 129 ret i32 %C 130} 131 132define i32 @test7(i8 %A) { 133; CHECK-LABEL: @test7( 134; CHECK-NEXT: ret i32 -1 135; 136 %shift.upgrd.3 = zext i8 %A to i32 137 %B = ashr i32 -1, %shift.upgrd.3 ;; Always equal to -1 138 ret i32 %B 139} 140 141;; (A << 5) << 3 === A << 8 == 0 142define i8 @test8(i8 %A) { 143; CHECK-LABEL: @test8( 144; CHECK-NEXT: ret i8 0 145; 146 %B = shl i8 %A, 5 147 %C = shl i8 %B, 3 148 ret i8 %C 149} 150 151;; (A << 7) >> 7 === A & 1 152define i8 @test9(i8 %A) { 153; CHECK-LABEL: @test9( 154; CHECK-NEXT: [[B:%.*]] = and i8 %A, 1 155; CHECK-NEXT: ret i8 [[B]] 156; 157 %B = shl i8 %A, 7 158 %C = lshr i8 %B, 7 159 ret i8 %C 160} 161 162;; (A >> 7) << 7 === A & 128 163 164define i8 @test10(i8 %A) { 165; CHECK-LABEL: @test10( 166; CHECK-NEXT: [[B:%.*]] = and i8 %A, -128 167; CHECK-NEXT: ret i8 [[B]] 168; 169 %B = lshr i8 %A, 7 170 %C = shl i8 %B, 7 171 ret i8 %C 172} 173 174;; Allow the simplification when the lshr shift is exact. 175define i8 @test10a(i8 %A) { 176; CHECK-LABEL: @test10a( 177; CHECK-NEXT: ret i8 %A 178; 179 %B = lshr exact i8 %A, 7 180 %C = shl i8 %B, 7 181 ret i8 %C 182} 183 184;; This transformation is deferred to DAGCombine: 185;; (A >> 3) << 4 === (A & 0x1F) << 1 186;; The shl may be valuable to scalar evolution. 187define i8 @test11(i8 %A) { 188; CHECK-LABEL: @test11( 189; CHECK-NEXT: [[A:%.*]] = mul i8 %A, 3 190; CHECK-NEXT: [[B:%.*]] = lshr i8 [[A]], 3 191; CHECK-NEXT: [[C:%.*]] = shl i8 [[B]], 4 192; CHECK-NEXT: ret i8 [[C]] 193; 194 %a = mul i8 %A, 3 195 %B = lshr i8 %a, 3 196 %C = shl i8 %B, 4 197 ret i8 %C 198} 199 200;; Allow the simplification in InstCombine when the lshr shift is exact. 201define i8 @test11a(i8 %A) { 202; CHECK-LABEL: @test11a( 203; CHECK-NEXT: [[C:%.*]] = mul i8 %A, 6 204; CHECK-NEXT: ret i8 [[C]] 205; 206 %a = mul i8 %A, 3 207 %B = lshr exact i8 %a, 3 208 %C = shl i8 %B, 4 209 ret i8 %C 210} 211 212;; This is deferred to DAGCombine unless %B is single-use. 213;; (A >> 8) << 8 === A & -256 214define i32 @test12(i32 %A) { 215; CHECK-LABEL: @test12( 216; CHECK-NEXT: [[B1:%.*]] = and i32 %A, -256 217; CHECK-NEXT: ret i32 [[B1]] 218; 219 %B = ashr i32 %A, 8 220 %C = shl i32 %B, 8 221 ret i32 %C 222} 223 224;; ((A >>s 6) << 6 === (A & FFFFFFC0) 225define i8 @shishi(i8 %x) { 226; CHECK-LABEL: @shishi( 227; CHECK-NEXT: [[A:%.*]] = ashr i8 [[X:%.*]], 6 228; CHECK-NEXT: [[B:%.*]] = and i8 [[X]], -64 229; CHECK-NEXT: [[EXTRA_USE_OF_A:%.*]] = mul nsw i8 [[A]], 5 230; CHECK-NEXT: [[R:%.*]] = sdiv i8 [[EXTRA_USE_OF_A]], [[B]] 231; CHECK-NEXT: ret i8 [[R]] 232; 233 %a = ashr i8 %x, 6 234 %b = shl i8 %a, 6 235 %extra_use_of_a = mul i8 %a, 5 236 %r = sdiv i8 %extra_use_of_a, %b 237 ret i8 %r 238} 239 240;; This transformation is deferred to DAGCombine: 241;; (A >> 3) << 4 === (A & -8) * 2 242;; The shl may be valuable to scalar evolution. 243define i8 @test13(i8 %A) { 244; CHECK-LABEL: @test13( 245; CHECK-NEXT: [[A:%.*]] = mul i8 %A, 3 246; CHECK-NEXT: [[B1:%.*]] = lshr i8 [[A]], 3 247; CHECK-NEXT: [[C:%.*]] = shl i8 [[B1]], 4 248; CHECK-NEXT: ret i8 [[C]] 249; 250 %a = mul i8 %A, 3 251 %B = ashr i8 %a, 3 252 %C = shl i8 %B, 4 253 ret i8 %C 254} 255 256define i8 @test13a(i8 %A) { 257; CHECK-LABEL: @test13a( 258; CHECK-NEXT: [[C:%.*]] = mul i8 %A, 6 259; CHECK-NEXT: ret i8 [[C]] 260; 261 %a = mul i8 %A, 3 262 %B = ashr exact i8 %a, 3 263 %C = shl i8 %B, 4 264 ret i8 %C 265} 266 267;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4) 268define i32 @test14(i32 %A) { 269; CHECK-LABEL: @test14( 270; CHECK-NEXT: [[B:%.*]] = and i32 %A, -19760 271; CHECK-NEXT: [[C:%.*]] = or i32 [[B]], 19744 272; CHECK-NEXT: ret i32 [[C]] 273; 274 %B = lshr i32 %A, 4 275 %C = or i32 %B, 1234 276 %D = shl i32 %C, 4 277 ret i32 %D 278} 279 280;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4) 281define i32 @test14a(i32 %A) { 282; CHECK-LABEL: @test14a( 283; CHECK-NEXT: [[C:%.*]] = and i32 %A, 77 284; CHECK-NEXT: ret i32 [[C]] 285; 286 %B = shl i32 %A, 4 287 %C = and i32 %B, 1234 288 %D = lshr i32 %C, 4 289 ret i32 %D 290} 291 292define i32 @test15(i1 %C) { 293; CHECK-LABEL: @test15( 294; CHECK-NEXT: [[A:%.*]] = select i1 %C, i32 12, i32 4 295; CHECK-NEXT: ret i32 [[A]] 296; 297 %A = select i1 %C, i32 3, i32 1 298 %V = shl i32 %A, 2 299 ret i32 %V 300} 301 302define i32 @test15a(i1 %C) { 303; CHECK-LABEL: @test15a( 304; CHECK-NEXT: [[V:%.*]] = select i1 %C, i32 512, i32 128 305; CHECK-NEXT: ret i32 [[V]] 306; 307 %A = select i1 %C, i8 3, i8 1 308 %shift.upgrd.4 = zext i8 %A to i32 309 %V = shl i32 64, %shift.upgrd.4 310 ret i32 %V 311} 312 313define i1 @test16(i32 %X) { 314; CHECK-LABEL: @test16( 315; CHECK-NEXT: [[TMP_6:%.*]] = and i32 %X, 16 316; CHECK-NEXT: [[TMP_7:%.*]] = icmp ne i32 [[TMP_6]], 0 317; CHECK-NEXT: ret i1 [[TMP_7]] 318; 319 %tmp.3 = ashr i32 %X, 4 320 %tmp.6 = and i32 %tmp.3, 1 321 %tmp.7 = icmp ne i32 %tmp.6, 0 322 ret i1 %tmp.7 323} 324 325define i1 @test17(i32 %A) { 326; CHECK-LABEL: @test17( 327; CHECK-NEXT: [[B_MASK:%.*]] = and i32 %A, -8 328; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[B_MASK]], 9872 329; CHECK-NEXT: ret i1 [[C]] 330; 331 %B = lshr i32 %A, 3 332 %C = icmp eq i32 %B, 1234 333 ret i1 %C 334} 335 336define <2 x i1> @test17vec(<2 x i32> %A) { 337; CHECK-LABEL: @test17vec( 338; CHECK-NEXT: [[B_MASK:%.*]] = and <2 x i32> %A, <i32 -8, i32 -8> 339; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i32> [[B_MASK]], <i32 9872, i32 9872> 340; CHECK-NEXT: ret <2 x i1> [[C]] 341; 342 %B = lshr <2 x i32> %A, <i32 3, i32 3> 343 %C = icmp eq <2 x i32> %B, <i32 1234, i32 1234> 344 ret <2 x i1> %C 345} 346 347define i1 @test18(i8 %A) { 348; CHECK-LABEL: @test18( 349; CHECK-NEXT: ret i1 false 350; 351 %B = lshr i8 %A, 7 352 ;; false 353 %C = icmp eq i8 %B, 123 354 ret i1 %C 355} 356 357define i1 @test19(i32 %A) { 358; CHECK-LABEL: @test19( 359; CHECK-NEXT: [[C:%.*]] = icmp ult i32 %A, 4 360; CHECK-NEXT: ret i1 [[C]] 361; 362 %B = ashr i32 %A, 2 363 ;; (X & -4) == 0 364 %C = icmp eq i32 %B, 0 365 ret i1 %C 366} 367 368define <2 x i1> @test19vec(<2 x i32> %A) { 369; CHECK-LABEL: @test19vec( 370; CHECK-NEXT: [[C:%.*]] = icmp ult <2 x i32> %A, <i32 4, i32 4> 371; CHECK-NEXT: ret <2 x i1> [[C]] 372; 373 %B = ashr <2 x i32> %A, <i32 2, i32 2> 374 %C = icmp eq <2 x i32> %B, zeroinitializer 375 ret <2 x i1> %C 376} 377 378;; X >u ~4 379define i1 @test19a(i32 %A) { 380; CHECK-LABEL: @test19a( 381; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 %A, -5 382; CHECK-NEXT: ret i1 [[C]] 383; 384 %B = ashr i32 %A, 2 385 %C = icmp eq i32 %B, -1 386 ret i1 %C 387} 388 389define <2 x i1> @test19a_vec(<2 x i32> %A) { 390; CHECK-LABEL: @test19a_vec( 391; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> %A, <i32 -5, i32 -5> 392; CHECK-NEXT: ret <2 x i1> [[C]] 393; 394 %B = ashr <2 x i32> %A, <i32 2, i32 2> 395 %C = icmp eq <2 x i32> %B, <i32 -1, i32 -1> 396 ret <2 x i1> %C 397} 398 399define i1 @test20(i8 %A) { 400; CHECK-LABEL: @test20( 401; CHECK-NEXT: ret i1 false 402; 403 %B = ashr i8 %A, 7 404 ;; false 405 %C = icmp eq i8 %B, 123 406 ret i1 %C 407} 408 409define i1 @test21(i8 %A) { 410; CHECK-LABEL: @test21( 411; CHECK-NEXT: [[B_MASK:%.*]] = and i8 %A, 15 412; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 8 413; CHECK-NEXT: ret i1 [[C]] 414; 415 %B = shl i8 %A, 4 416 %C = icmp eq i8 %B, -128 417 ret i1 %C 418} 419 420define i1 @test22(i8 %A) { 421; CHECK-LABEL: @test22( 422; CHECK-NEXT: [[B_MASK:%.*]] = and i8 %A, 15 423; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 0 424; CHECK-NEXT: ret i1 [[C]] 425; 426 %B = shl i8 %A, 4 427 %C = icmp eq i8 %B, 0 428 ret i1 %C 429} 430 431define i8 @test23(i32 %A) { 432; CHECK-LABEL: @test23( 433; CHECK-NEXT: [[D:%.*]] = trunc i32 %A to i8 434; CHECK-NEXT: ret i8 [[D]] 435; 436 ;; casts not needed 437 %B = shl i32 %A, 24 438 %C = ashr i32 %B, 24 439 %D = trunc i32 %C to i8 440 ret i8 %D 441} 442 443define i8 @test24(i8 %X) { 444; CHECK-LABEL: @test24( 445; CHECK-NEXT: [[Z:%.*]] = and i8 %X, 3 446; CHECK-NEXT: ret i8 [[Z]] 447; 448 %Y = and i8 %X, -5 449 %Z = shl i8 %Y, 5 450 %Q = ashr i8 %Z, 5 451 ret i8 %Q 452} 453 454define i32 @test25(i32 %tmp.2, i32 %AA) { 455; CHECK-LABEL: @test25( 456; CHECK-NEXT: [[TMP_3:%.*]] = and i32 %tmp.2, -131072 457; CHECK-NEXT: [[X2:%.*]] = add i32 [[TMP_3]], %AA 458; CHECK-NEXT: [[TMP_6:%.*]] = and i32 [[X2]], -131072 459; CHECK-NEXT: ret i32 [[TMP_6]] 460; 461 %x = lshr i32 %AA, 17 462 %tmp.3 = lshr i32 %tmp.2, 17 463 %tmp.5 = add i32 %tmp.3, %x 464 %tmp.6 = shl i32 %tmp.5, 17 465 ret i32 %tmp.6 466} 467 468define <2 x i32> @test25_vector(<2 x i32> %tmp.2, <2 x i32> %AA) { 469; CHECK-LABEL: @test25_vector( 470; CHECK-NEXT: [[TMP_3:%.*]] = and <2 x i32> %tmp.2, <i32 -131072, i32 -131072> 471; CHECK-NEXT: [[X2:%.*]] = add <2 x i32> [[TMP_3]], %AA 472; CHECK-NEXT: [[TMP_6:%.*]] = and <2 x i32> [[X2]], <i32 -131072, i32 -131072> 473; CHECK-NEXT: ret <2 x i32> [[TMP_6]] 474; 475 %x = lshr <2 x i32> %AA, <i32 17, i32 17> 476 %tmp.3 = lshr <2 x i32> %tmp.2, <i32 17, i32 17> 477 %tmp.5 = add <2 x i32> %tmp.3, %x 478 %tmp.6 = shl <2 x i32> %tmp.5, <i32 17, i32 17> 479 ret <2 x i32> %tmp.6 480} 481 482;; handle casts between shifts. 483define i32 @test26(i32 %A) { 484; CHECK-LABEL: @test26( 485; CHECK-NEXT: [[B:%.*]] = and i32 %A, -2 486; CHECK-NEXT: ret i32 [[B]] 487; 488 %B = lshr i32 %A, 1 489 %C = bitcast i32 %B to i32 490 %D = shl i32 %C, 1 491 ret i32 %D 492} 493 494 495define i1 @test27(i32 %x) nounwind { 496; CHECK-LABEL: @test27( 497; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 8 498; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[TMP1]], 0 499; CHECK-NEXT: ret i1 [[Z]] 500; 501 %y = lshr i32 %x, 3 502 %z = trunc i32 %y to i1 503 ret i1 %z 504} 505 506define i1 @test28(i8 %x) { 507; CHECK-LABEL: @test28( 508; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 %x, 0 509; CHECK-NEXT: ret i1 [[CMP]] 510; 511 %shr = lshr i8 %x, 7 512 %cmp = icmp ne i8 %shr, 0 513 ret i1 %cmp 514} 515 516define <2 x i1> @test28vec(<2 x i8> %x) { 517; CHECK-LABEL: @test28vec( 518; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> %x, zeroinitializer 519; CHECK-NEXT: ret <2 x i1> [[CMP]] 520; 521 %shr = lshr <2 x i8> %x, <i8 7, i8 7> 522 %cmp = icmp ne <2 x i8> %shr, zeroinitializer 523 ret <2 x i1> %cmp 524} 525 526define i8 @test28a(i8 %x, i8 %y) { 527; CHECK-LABEL: @test28a( 528; CHECK-NEXT: entry: 529; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 %x, 7 530; CHECK-NEXT: [[COND1:%.*]] = icmp eq i8 [[TMP1]], 0 531; CHECK-NEXT: br i1 [[COND1]], label %bb2, label %bb1 532; CHECK: bb1: 533; CHECK-NEXT: ret i8 [[TMP1]] 534; CHECK: bb2: 535; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], %y 536; CHECK-NEXT: ret i8 [[TMP2]] 537; 538entry: 539; This shouldn't be transformed. 540 %tmp1 = lshr i8 %x, 7 541 %cond1 = icmp ne i8 %tmp1, 0 542 br i1 %cond1, label %bb1, label %bb2 543bb1: 544 ret i8 %tmp1 545bb2: 546 %tmp2 = add i8 %tmp1, %y 547 ret i8 %tmp2 548} 549 550 551define i32 @test29(i64 %d18) { 552; CHECK-LABEL: @test29( 553; CHECK-NEXT: entry: 554; CHECK-NEXT: [[TMP916:%.*]] = lshr i64 %d18, 63 555; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP916]] to i32 556; CHECK-NEXT: ret i32 [[TMP10]] 557; 558entry: 559 %tmp916 = lshr i64 %d18, 32 560 %tmp917 = trunc i64 %tmp916 to i32 561 %tmp10 = lshr i32 %tmp917, 31 562 ret i32 %tmp10 563} 564 565 566define i32 @test30(i32 %A, i32 %B, i32 %C) { 567; CHECK-LABEL: @test30( 568; CHECK-NEXT: [[X1:%.*]] = and i32 %A, %B 569; CHECK-NEXT: [[Z:%.*]] = shl i32 [[X1]], %C 570; CHECK-NEXT: ret i32 [[Z]] 571; 572 %X = shl i32 %A, %C 573 %Y = shl i32 %B, %C 574 %Z = and i32 %X, %Y 575 ret i32 %Z 576} 577 578define i32 @test31(i32 %A, i32 %B, i32 %C) { 579; CHECK-LABEL: @test31( 580; CHECK-NEXT: [[X1:%.*]] = or i32 %A, %B 581; CHECK-NEXT: [[Z:%.*]] = lshr i32 [[X1]], %C 582; CHECK-NEXT: ret i32 [[Z]] 583; 584 %X = lshr i32 %A, %C 585 %Y = lshr i32 %B, %C 586 %Z = or i32 %X, %Y 587 ret i32 %Z 588} 589 590define i32 @test32(i32 %A, i32 %B, i32 %C) { 591; CHECK-LABEL: @test32( 592; CHECK-NEXT: [[X1:%.*]] = xor i32 %A, %B 593; CHECK-NEXT: [[Z:%.*]] = ashr i32 [[X1]], %C 594; CHECK-NEXT: ret i32 [[Z]] 595; 596 %X = ashr i32 %A, %C 597 %Y = ashr i32 %B, %C 598 %Z = xor i32 %X, %Y 599 ret i32 %Z 600} 601 602define i1 @test33(i32 %X) { 603; CHECK-LABEL: @test33( 604; CHECK-NEXT: [[TMP1_MASK:%.*]] = and i32 %X, 16777216 605; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1_MASK]], 0 606; CHECK-NEXT: ret i1 [[TMP2]] 607; 608 %tmp1 = shl i32 %X, 7 609 %tmp2 = icmp slt i32 %tmp1, 0 610 ret i1 %tmp2 611} 612 613define <2 x i1> @test33vec(<2 x i32> %X) { 614; CHECK-LABEL: @test33vec( 615; CHECK-NEXT: [[TMP1_MASK:%.*]] = and <2 x i32> %X, <i32 16777216, i32 16777216> 616; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1_MASK]], zeroinitializer 617; CHECK-NEXT: ret <2 x i1> [[TMP2]] 618; 619 %tmp1 = shl <2 x i32> %X, <i32 7, i32 7> 620 %tmp2 = icmp slt <2 x i32> %tmp1, zeroinitializer 621 ret <2 x i1> %tmp2 622} 623 624define i1 @test34(i32 %X) { 625; CHECK-LABEL: @test34( 626; CHECK-NEXT: ret i1 false 627; 628 %tmp1 = lshr i32 %X, 7 629 %tmp2 = icmp slt i32 %tmp1, 0 630 ret i1 %tmp2 631} 632 633define i1 @test35(i32 %X) { 634; CHECK-LABEL: @test35( 635; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 %X, 0 636; CHECK-NEXT: ret i1 [[TMP2]] 637; 638 %tmp1 = ashr i32 %X, 7 639 %tmp2 = icmp slt i32 %tmp1, 0 640 ret i1 %tmp2 641} 642 643define <2 x i1> @test35vec(<2 x i32> %X) { 644; CHECK-LABEL: @test35vec( 645; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> %X, zeroinitializer 646; CHECK-NEXT: ret <2 x i1> [[TMP2]] 647; 648 %tmp1 = ashr <2 x i32> %X, <i32 7, i32 7> 649 %tmp2 = icmp slt <2 x i32> %tmp1, zeroinitializer 650 ret <2 x i1> %tmp2 651} 652 653define i128 @test36(i128 %A, i128 %B) { 654; CHECK-LABEL: @test36( 655; CHECK-NEXT: [[TMP231:%.*]] = or i128 %B, %A 656; CHECK-NEXT: [[INS:%.*]] = and i128 [[TMP231]], 18446744073709551615 657; CHECK-NEXT: ret i128 [[INS]] 658; 659 %tmp27 = shl i128 %A, 64 660 %tmp23 = shl i128 %B, 64 661 %ins = or i128 %tmp23, %tmp27 662 %tmp45 = lshr i128 %ins, 64 663 ret i128 %tmp45 664} 665 666define i64 @test37(i128 %A, i32 %B) { 667; CHECK-LABEL: @test37( 668; CHECK-NEXT: [[TMP22:%.*]] = zext i32 %B to i128 669; CHECK-NEXT: [[TMP23:%.*]] = shl nuw nsw i128 [[TMP22]], 32 670; CHECK-NEXT: [[INS:%.*]] = or i128 [[TMP23]], %A 671; CHECK-NEXT: [[TMP46:%.*]] = trunc i128 [[INS]] to i64 672; CHECK-NEXT: ret i64 [[TMP46]] 673; 674 %tmp27 = shl i128 %A, 64 675 %tmp22 = zext i32 %B to i128 676 %tmp23 = shl i128 %tmp22, 96 677 %ins = or i128 %tmp23, %tmp27 678 %tmp45 = lshr i128 %ins, 64 679 %tmp46 = trunc i128 %tmp45 to i64 680 ret i64 %tmp46 681} 682 683define <2 x i32> @shl_nuw_nsw_splat_vec(<2 x i8> %x) { 684; CHECK-LABEL: @shl_nuw_nsw_splat_vec( 685; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> %x to <2 x i32> 686; CHECK-NEXT: [[T3:%.*]] = shl nuw nsw <2 x i32> [[T2]], <i32 17, i32 17> 687; CHECK-NEXT: ret <2 x i32> [[T3]] 688; 689 %t2 = zext <2 x i8> %x to <2 x i32> 690 %t3 = shl <2 x i32> %t2, <i32 17, i32 17> 691 ret <2 x i32> %t3 692} 693 694define i32 @test38(i32 %x) nounwind readnone { 695; CHECK-LABEL: @test38( 696; CHECK-NEXT: [[REM1:%.*]] = and i32 %x, 31 697; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[REM1]] 698; CHECK-NEXT: ret i32 [[SHL]] 699; 700 %rem = srem i32 %x, 32 701 %shl = shl i32 1, %rem 702 ret i32 %shl 703} 704 705; <rdar://problem/8756731> 706define i8 @test39(i32 %a0) { 707; CHECK-LABEL: @test39( 708; CHECK-NEXT: entry: 709; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 %a0 to i8 710; CHECK-NEXT: [[TMP5:%.*]] = shl i8 [[TMP4]], 5 711; CHECK-NEXT: [[TMP49:%.*]] = shl i8 [[TMP4]], 6 712; CHECK-NEXT: [[TMP50:%.*]] = and i8 [[TMP49]], 64 713; CHECK-NEXT: [[TMP51:%.*]] = xor i8 [[TMP50]], [[TMP5]] 714; CHECK-NEXT: [[TMP0:%.*]] = shl i8 [[TMP4]], 2 715; CHECK-NEXT: [[TMP54:%.*]] = and i8 [[TMP0]], 16 716; CHECK-NEXT: [[TMP551:%.*]] = or i8 [[TMP54]], [[TMP51]] 717; CHECK-NEXT: ret i8 [[TMP551]] 718; 719entry: 720 %tmp4 = trunc i32 %a0 to i8 721 %tmp5 = shl i8 %tmp4, 5 722 %tmp48 = and i8 %tmp5, 32 723 %tmp49 = lshr i8 %tmp48, 5 724 %tmp50 = mul i8 %tmp49, 64 725 %tmp51 = xor i8 %tmp50, %tmp5 726 %tmp52 = and i8 %tmp51, -128 727 %tmp53 = lshr i8 %tmp52, 7 728 %tmp54 = mul i8 %tmp53, 16 729 %tmp55 = xor i8 %tmp54, %tmp51 730 ret i8 %tmp55 731} 732 733; PR9809 734define i32 @test40(i32 %a, i32 %b) nounwind { 735; CHECK-LABEL: @test40( 736; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, 2 737; CHECK-NEXT: [[DIV:%.*]] = lshr i32 %a, [[TMP1]] 738; CHECK-NEXT: ret i32 [[DIV]] 739; 740 %shl1 = shl i32 1, %b 741 %shl2 = shl i32 %shl1, 2 742 %div = udiv i32 %a, %shl2 743 ret i32 %div 744} 745 746define i32 @test41(i32 %a, i32 %b) nounwind { 747; CHECK-LABEL: @test41( 748; CHECK-NEXT: [[TMP1:%.*]] = shl i32 8, %b 749; CHECK-NEXT: ret i32 [[TMP1]] 750; 751 %1 = shl i32 1, %b 752 %2 = shl i32 %1, 3 753 ret i32 %2 754} 755 756define i32 @test42(i32 %a, i32 %b) nounwind { 757; CHECK-LABEL: @test42( 758; CHECK-NEXT: [[DIV:%.*]] = lshr exact i32 4096, %b 759; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 %a, [[DIV]] 760; CHECK-NEXT: ret i32 [[DIV2]] 761; 762 %div = lshr i32 4096, %b ; must be exact otherwise we'd divide by zero 763 %div2 = udiv i32 %a, %div 764 ret i32 %div2 765} 766 767define <2 x i32> @test42vec(<2 x i32> %a, <2 x i32> %b) { 768; CHECK-LABEL: @test42vec( 769; CHECK-NEXT: [[DIV:%.*]] = lshr exact <2 x i32> <i32 4096, i32 4096>, %b 770; CHECK-NEXT: [[DIV2:%.*]] = udiv <2 x i32> %a, [[DIV]] 771; CHECK-NEXT: ret <2 x i32> [[DIV2]] 772; 773 %div = lshr <2 x i32> <i32 4096, i32 4096>, %b ; must be exact otherwise we'd divide by zero 774 %div2 = udiv <2 x i32> %a, %div 775 ret <2 x i32> %div2 776} 777 778define i32 @test43(i32 %a, i32 %b) nounwind { 779; CHECK-LABEL: @test43( 780; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, 12 781; CHECK-NEXT: [[DIV2:%.*]] = lshr i32 %a, [[TMP1]] 782; CHECK-NEXT: ret i32 [[DIV2]] 783; 784 %div = shl i32 4096, %b ; must be exact otherwise we'd divide by zero 785 %div2 = udiv i32 %a, %div 786 ret i32 %div2 787} 788 789define i32 @test44(i32 %a) nounwind { 790; CHECK-LABEL: @test44( 791; CHECK-NEXT: [[Y:%.*]] = shl i32 %a, 5 792; CHECK-NEXT: ret i32 [[Y]] 793; 794 %y = shl nuw i32 %a, 1 795 %z = shl i32 %y, 4 796 ret i32 %z 797} 798 799define i32 @test45(i32 %a) nounwind { 800; CHECK-LABEL: @test45( 801; CHECK-NEXT: [[Y:%.*]] = lshr i32 %a, 5 802; CHECK-NEXT: ret i32 [[Y]] 803; 804 %y = lshr exact i32 %a, 1 805 %z = lshr i32 %y, 4 806 ret i32 %z 807} 808 809; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 810 811define i32 @test46(i32 %a) { 812; CHECK-LABEL: @test46( 813; CHECK-NEXT: [[Z:%.*]] = ashr exact i32 %a, 2 814; CHECK-NEXT: ret i32 [[Z]] 815; 816 %y = ashr exact i32 %a, 3 817 %z = shl i32 %y, 1 818 ret i32 %z 819} 820 821; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 822 823define <2 x i32> @test46_splat_vec(<2 x i32> %a) { 824; CHECK-LABEL: @test46_splat_vec( 825; CHECK-NEXT: [[Z:%.*]] = ashr exact <2 x i32> %a, <i32 2, i32 2> 826; CHECK-NEXT: ret <2 x i32> [[Z]] 827; 828 %y = ashr exact <2 x i32> %a, <i32 3, i32 3> 829 %z = shl <2 x i32> %y, <i32 1, i32 1> 830 ret <2 x i32> %z 831} 832 833; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 834 835define i8 @test47(i8 %a) { 836; CHECK-LABEL: @test47( 837; CHECK-NEXT: [[Z:%.*]] = lshr exact i8 %a, 2 838; CHECK-NEXT: ret i8 [[Z]] 839; 840 %y = lshr exact i8 %a, 3 841 %z = shl i8 %y, 1 842 ret i8 %z 843} 844 845; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 846 847define <2 x i8> @test47_splat_vec(<2 x i8> %a) { 848; CHECK-LABEL: @test47_splat_vec( 849; CHECK-NEXT: [[Z:%.*]] = lshr exact <2 x i8> %a, <i8 2, i8 2> 850; CHECK-NEXT: ret <2 x i8> [[Z]] 851; 852 %y = lshr exact <2 x i8> %a, <i8 3, i8 3> 853 %z = shl <2 x i8> %y, <i8 1, i8 1> 854 ret <2 x i8> %z 855} 856 857; (X >>u,exact C1) << C2 --> X << (C2-C1) when C2 > C1 858 859define i32 @test48(i32 %x) { 860; CHECK-LABEL: @test48( 861; CHECK-NEXT: [[B:%.*]] = shl i32 %x, 2 862; CHECK-NEXT: ret i32 [[B]] 863; 864 %A = lshr exact i32 %x, 1 865 %B = shl i32 %A, 3 866 ret i32 %B 867} 868 869; Verify that wrap flags are preserved from the original 'shl'. 870 871define i32 @test48_nuw_nsw(i32 %x) { 872; CHECK-LABEL: @test48_nuw_nsw( 873; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 %x, 2 874; CHECK-NEXT: ret i32 [[B]] 875; 876 %A = lshr exact i32 %x, 1 877 %B = shl nuw nsw i32 %A, 3 878 ret i32 %B 879} 880 881; (X >>u,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1 882 883define <2 x i32> @test48_splat_vec(<2 x i32> %x) { 884; CHECK-LABEL: @test48_splat_vec( 885; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> %x, <i32 2, i32 2> 886; CHECK-NEXT: ret <2 x i32> [[B]] 887; 888 %A = lshr exact <2 x i32> %x, <i32 1, i32 1> 889 %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3> 890 ret <2 x i32> %B 891} 892 893; (X >>s,exact C1) << C2 --> X << (C2-C1) when C2 > C1 894 895define i32 @test49(i32 %x) { 896; CHECK-LABEL: @test49( 897; CHECK-NEXT: [[B:%.*]] = shl i32 %x, 2 898; CHECK-NEXT: ret i32 [[B]] 899; 900 %A = ashr exact i32 %x, 1 901 %B = shl i32 %A, 3 902 ret i32 %B 903} 904 905; Verify that wrap flags are preserved from the original 'shl'. 906 907define i32 @test49_nuw_nsw(i32 %x) { 908; CHECK-LABEL: @test49_nuw_nsw( 909; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 %x, 2 910; CHECK-NEXT: ret i32 [[B]] 911; 912 %A = ashr exact i32 %x, 1 913 %B = shl nuw nsw i32 %A, 3 914 ret i32 %B 915} 916 917; (X >>s,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1 918 919define <2 x i32> @test49_splat_vec(<2 x i32> %x) { 920; CHECK-LABEL: @test49_splat_vec( 921; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> %x, <i32 2, i32 2> 922; CHECK-NEXT: ret <2 x i32> [[B]] 923; 924 %A = ashr exact <2 x i32> %x, <i32 1, i32 1> 925 %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3> 926 ret <2 x i32> %B 927} 928 929; (X <<nsw C1) >>s C2 --> X >>s (C2-C1) 930 931define i32 @test50(i32 %x) { 932; CHECK-LABEL: @test50( 933; CHECK-NEXT: [[B:%.*]] = ashr i32 %x, 2 934; CHECK-NEXT: ret i32 [[B]] 935; 936 %A = shl nsw i32 %x, 1 937 %B = ashr i32 %A, 3 938 ret i32 %B 939} 940 941; (X <<nsw C1) >>s C2 --> X >>s (C2-C1) 942; Also, check that exact is propagated. 943 944define <2 x i32> @test50_splat_vec(<2 x i32> %x) { 945; CHECK-LABEL: @test50_splat_vec( 946; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i32> %x, <i32 2, i32 2> 947; CHECK-NEXT: ret <2 x i32> [[B]] 948; 949 %A = shl nsw <2 x i32> %x, <i32 1, i32 1> 950 %B = ashr exact <2 x i32> %A, <i32 3, i32 3> 951 ret <2 x i32> %B 952} 953 954; (X <<nuw C1) >>u C2 --> X >>u (C2-C1) 955 956define i32 @test51(i32 %x) { 957; CHECK-LABEL: @test51( 958; CHECK-NEXT: [[B:%.*]] = lshr i32 %x, 2 959; CHECK-NEXT: ret i32 [[B]] 960; 961 %A = shl nuw i32 %x, 1 962 %B = lshr i32 %A, 3 963 ret i32 %B 964} 965 966; (X <<nuw C1) >>u C2 --> X >>u (C2-C1) with splats 967; Also, check that exact is propagated. 968 969define <2 x i32> @test51_splat_vec(<2 x i32> %x) { 970; CHECK-LABEL: @test51_splat_vec( 971; CHECK-NEXT: [[B:%.*]] = lshr exact <2 x i32> %x, <i32 2, i32 2> 972; CHECK-NEXT: ret <2 x i32> [[B]] 973; 974 %A = shl nuw <2 x i32> %x, <i32 1, i32 1> 975 %B = lshr exact <2 x i32> %A, <i32 3, i32 3> 976 ret <2 x i32> %B 977} 978 979; (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2) 980; Also, check that exact is propagated. 981 982define i32 @test51_no_nuw(i32 %x) { 983; CHECK-LABEL: @test51_no_nuw( 984; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 %x, 2 985; CHECK-NEXT: [[B:%.*]] = and i32 [[TMP1]], 536870911 986; CHECK-NEXT: ret i32 [[B]] 987; 988 %A = shl i32 %x, 1 989 %B = lshr exact i32 %A, 3 990 ret i32 %B 991} 992 993; (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2) 994 995define <2 x i32> @test51_no_nuw_splat_vec(<2 x i32> %x) { 996; CHECK-LABEL: @test51_no_nuw_splat_vec( 997; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> %x, <i32 2, i32 2> 998; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[TMP1]], <i32 536870911, i32 536870911> 999; CHECK-NEXT: ret <2 x i32> [[B]] 1000; 1001 %A = shl <2 x i32> %x, <i32 1, i32 1> 1002 %B = lshr <2 x i32> %A, <i32 3, i32 3> 1003 ret <2 x i32> %B 1004} 1005 1006; (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2) 1007 1008define i32 @test52(i32 %x) { 1009; CHECK-LABEL: @test52( 1010; CHECK-NEXT: [[B:%.*]] = shl nsw i32 %x, 2 1011; CHECK-NEXT: ret i32 [[B]] 1012; 1013 %A = shl nsw i32 %x, 3 1014 %B = ashr i32 %A, 1 1015 ret i32 %B 1016} 1017 1018; (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2) 1019 1020define <2 x i32> @test52_splat_vec(<2 x i32> %x) { 1021; CHECK-LABEL: @test52_splat_vec( 1022; CHECK-NEXT: [[B:%.*]] = shl nsw <2 x i32> %x, <i32 2, i32 2> 1023; CHECK-NEXT: ret <2 x i32> [[B]] 1024; 1025 %A = shl nsw <2 x i32> %x, <i32 3, i32 3> 1026 %B = ashr <2 x i32> %A, <i32 1, i32 1> 1027 ret <2 x i32> %B 1028} 1029 1030; (X <<nuw C1) >>u C2 --> X <<nuw (C1 - C2) 1031 1032define i32 @test53(i32 %x) { 1033; CHECK-LABEL: @test53( 1034; CHECK-NEXT: [[B:%.*]] = shl nuw i32 %x, 2 1035; CHECK-NEXT: ret i32 [[B]] 1036; 1037 %A = shl nuw i32 %x, 3 1038 %B = lshr i32 %A, 1 1039 ret i32 %B 1040} 1041 1042; (X <<nuw C1) >>u C2 --> X <<nuw (C1 - C2) 1043 1044define <2 x i32> @test53_splat_vec(<2 x i32> %x) { 1045; CHECK-LABEL: @test53_splat_vec( 1046; CHECK-NEXT: [[B:%.*]] = shl nuw <2 x i32> %x, <i32 2, i32 2> 1047; CHECK-NEXT: ret <2 x i32> [[B]] 1048; 1049 %A = shl nuw <2 x i32> %x, <i32 3, i32 3> 1050 %B = lshr <2 x i32> %A, <i32 1, i32 1> 1051 ret <2 x i32> %B 1052} 1053 1054; (X << C1) >>u C2 --> X << (C1 - C2) & (-1 >> C2) 1055 1056define i8 @test53_no_nuw(i8 %x) { 1057; CHECK-LABEL: @test53_no_nuw( 1058; CHECK-NEXT: [[TMP1:%.*]] = shl i8 %x, 2 1059; CHECK-NEXT: [[B:%.*]] = and i8 [[TMP1]], 124 1060; CHECK-NEXT: ret i8 [[B]] 1061; 1062 %A = shl i8 %x, 3 1063 %B = lshr i8 %A, 1 1064 ret i8 %B 1065} 1066 1067; (X << C1) >>u C2 --> X << (C1 - C2) & (-1 >> C2) 1068 1069define <2 x i8> @test53_no_nuw_splat_vec(<2 x i8> %x) { 1070; CHECK-LABEL: @test53_no_nuw_splat_vec( 1071; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i8> %x, <i8 2, i8 2> 1072; CHECK-NEXT: [[B:%.*]] = and <2 x i8> [[TMP1]], <i8 124, i8 124> 1073; CHECK-NEXT: ret <2 x i8> [[B]] 1074; 1075 %A = shl <2 x i8> %x, <i8 3, i8 3> 1076 %B = lshr <2 x i8> %A, <i8 1, i8 1> 1077 ret <2 x i8> %B 1078} 1079 1080define i32 @test54(i32 %x) { 1081; CHECK-LABEL: @test54( 1082; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3 1083; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP1]], 16 1084; CHECK-NEXT: ret i32 [[AND]] 1085; 1086 %shr2 = lshr i32 %x, 1 1087 %shl = shl i32 %shr2, 4 1088 %and = and i32 %shl, 16 1089 ret i32 %and 1090} 1091 1092define <2 x i32> @test54_splat_vec(<2 x i32> %x) { 1093; CHECK-LABEL: @test54_splat_vec( 1094; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> %x, <i32 3, i32 3> 1095; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[TMP1]], <i32 16, i32 16> 1096; CHECK-NEXT: ret <2 x i32> [[AND]] 1097; 1098 %shr2 = lshr <2 x i32> %x, <i32 1, i32 1> 1099 %shl = shl <2 x i32> %shr2, <i32 4, i32 4> 1100 %and = and <2 x i32> %shl, <i32 16, i32 16> 1101 ret <2 x i32> %and 1102} 1103 1104define i32 @test55(i32 %x) { 1105; CHECK-LABEL: @test55( 1106; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3 1107; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 8 1108; CHECK-NEXT: ret i32 [[OR]] 1109; 1110 %shr2 = lshr i32 %x, 1 1111 %shl = shl i32 %shr2, 4 1112 %or = or i32 %shl, 8 1113 ret i32 %or 1114} 1115 1116define i32 @test56(i32 %x) { 1117; CHECK-LABEL: @test56( 1118; CHECK-NEXT: [[SHR2:%.*]] = lshr i32 %x, 1 1119; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[SHR2]], 4 1120; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7 1121; CHECK-NEXT: ret i32 [[OR]] 1122; 1123 %shr2 = lshr i32 %x, 1 1124 %shl = shl i32 %shr2, 4 1125 %or = or i32 %shl, 7 1126 ret i32 %or 1127} 1128 1129define i32 @test57(i32 %x) { 1130; CHECK-LABEL: @test57( 1131; CHECK-NEXT: [[SHR1:%.*]] = lshr i32 %x, 1 1132; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[SHR1]], 4 1133; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7 1134; CHECK-NEXT: ret i32 [[OR]] 1135; 1136 %shr = ashr i32 %x, 1 1137 %shl = shl i32 %shr, 4 1138 %or = or i32 %shl, 7 1139 ret i32 %or 1140} 1141 1142define i32 @test58(i32 %x) { 1143; CHECK-LABEL: @test58( 1144; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 %x, 3 1145; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 1 1146; CHECK-NEXT: ret i32 [[OR]] 1147; 1148 %shr = ashr i32 %x, 4 1149 %shl = shl i32 %shr, 1 1150 %or = or i32 %shl, 1 1151 ret i32 %or 1152} 1153 1154define <2 x i32> @test58_splat_vec(<2 x i32> %x) { 1155; CHECK-LABEL: @test58_splat_vec( 1156; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> %x, <i32 3, i32 3> 1157; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[TMP1]], <i32 1, i32 1> 1158; CHECK-NEXT: ret <2 x i32> [[OR]] 1159; 1160 %shr = ashr <2 x i32> %x, <i32 4, i32 4> 1161 %shl = shl <2 x i32> %shr, <i32 1, i32 1> 1162 %or = or <2 x i32> %shl, <i32 1, i32 1> 1163 ret <2 x i32> %or 1164} 1165 1166define i32 @test59(i32 %x) { 1167; CHECK-LABEL: @test59( 1168; CHECK-NEXT: [[SHR:%.*]] = ashr i32 %x, 4 1169; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SHR]], 1 1170; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 2 1171; CHECK-NEXT: ret i32 [[OR]] 1172; 1173 %shr = ashr i32 %x, 4 1174 %shl = shl i32 %shr, 1 1175 %or = or i32 %shl, 2 1176 ret i32 %or 1177} 1178 1179; propagate "exact" trait 1180define i32 @test60(i32 %x) { 1181; CHECK-LABEL: @test60( 1182; CHECK-NEXT: [[SHL:%.*]] = ashr exact i32 %x, 3 1183; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 1 1184; CHECK-NEXT: ret i32 [[OR]] 1185; 1186 %shr = ashr exact i32 %x, 4 1187 %shl = shl i32 %shr, 1 1188 %or = or i32 %shl, 1 1189 ret i32 %or 1190} 1191 1192; PR17026 1193define void @test61(i128 %arg) { 1194; CHECK-LABEL: @test61( 1195; CHECK-NEXT: bb: 1196; CHECK-NEXT: br i1 undef, label %bb1, label %bb12 1197; CHECK: bb1: 1198; CHECK-NEXT: br label %bb2 1199; CHECK: bb2: 1200; CHECK-NEXT: br i1 undef, label %bb3, label %bb7 1201; CHECK: bb3: 1202; CHECK-NEXT: br label %bb8 1203; CHECK: bb7: 1204; CHECK-NEXT: br i1 undef, label %bb8, label %bb2 1205; CHECK: bb8: 1206; CHECK-NEXT: br i1 undef, label %bb11, label %bb12 1207; CHECK: bb11: 1208; CHECK-NEXT: br i1 undef, label %bb1, label %bb12 1209; CHECK: bb12: 1210; CHECK-NEXT: ret void 1211; 1212bb: 1213 br i1 undef, label %bb1, label %bb12 1214 1215bb1: ; preds = %bb11, %bb 1216 br label %bb2 1217 1218bb2: ; preds = %bb7, %bb1 1219 br i1 undef, label %bb3, label %bb7 1220 1221bb3: ; preds = %bb2 1222 %tmp = lshr i128 %arg, 36893488147419103232 1223 %tmp4 = shl i128 %tmp, 0 1224 %tmp5 = or i128 %tmp4, undef 1225 %tmp6 = trunc i128 %tmp5 to i16 1226 br label %bb8 1227 1228bb7: ; preds = %bb2 1229 br i1 undef, label %bb8, label %bb2 1230 1231bb8: ; preds = %bb7, %bb3 1232 %tmp9 = phi i16 [ %tmp6, %bb3 ], [ undef, %bb7 ] 1233 %tmp10 = icmp eq i16 %tmp9, 0 1234 br i1 %tmp10, label %bb11, label %bb12 1235 1236bb11: ; preds = %bb8 1237 br i1 undef, label %bb1, label %bb12 1238 1239bb12: ; preds = %bb11, %bb8, %bb 1240 ret void 1241} 1242 1243define i32 @test62(i32 %a) { 1244; CHECK-LABEL: @test62( 1245; CHECK-NEXT: ret i32 undef 1246; 1247 %b = ashr i32 %a, 32 ; shift all bits out 1248 ret i32 %b 1249} 1250 1251define <4 x i32> @test62_splat_vector(<4 x i32> %a) { 1252; CHECK-LABEL: @test62_splat_vector( 1253; CHECK-NEXT: ret <4 x i32> undef 1254; 1255 %b = ashr <4 x i32> %a, <i32 32, i32 32, i32 32, i32 32> ; shift all bits out 1256 ret <4 x i32> %b 1257} 1258 1259define <4 x i32> @test62_non_splat_vector(<4 x i32> %a) { 1260; CHECK-LABEL: @test62_non_splat_vector( 1261; CHECK-NEXT: [[B:%.*]] = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> 1262; CHECK-NEXT: ret <4 x i32> [[B]] 1263; 1264 %b = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> ; shift all bits out 1265 ret <4 x i32> %b 1266} 1267 1268define <2 x i65> @test_63(<2 x i64> %t) { 1269; CHECK-LABEL: @test_63( 1270; CHECK-NEXT: [[A:%.*]] = zext <2 x i64> %t to <2 x i65> 1271; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i65> [[A]], <i65 33, i65 33> 1272; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i65> [[SEXT]], <i65 33, i65 33> 1273; CHECK-NEXT: ret <2 x i65> [[B]] 1274; 1275 %a = zext <2 x i64> %t to <2 x i65> 1276 %sext = shl <2 x i65> %a, <i65 33, i65 33> 1277 %b = ashr <2 x i65> %sext, <i65 33, i65 33> 1278 ret <2 x i65> %b 1279} 1280 1281define i64 @test_64(i32 %t) { 1282; CHECK-LABEL: @test_64( 1283; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %t, 8 1284; CHECK-NEXT: [[SHL:%.*]] = zext i32 [[TMP1]] to i64 1285; CHECK-NEXT: ret i64 [[SHL]] 1286; 1287 %and = and i32 %t, 16777215 1288 %ext = zext i32 %and to i64 1289 %shl = shl i64 %ext, 8 1290 ret i64 %shl 1291} 1292 1293define <2 x i64> @test_64_splat_vec(<2 x i32> %t) { 1294; CHECK-LABEL: @test_64_splat_vec( 1295; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> %t, <i32 8, i32 8> 1296; CHECK-NEXT: [[SHL:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> 1297; CHECK-NEXT: ret <2 x i64> [[SHL]] 1298; 1299 %and = and <2 x i32> %t, <i32 16777215, i32 16777215> 1300 %ext = zext <2 x i32> %and to <2 x i64> 1301 %shl = shl <2 x i64> %ext, <i64 8, i64 8> 1302 ret <2 x i64> %shl 1303} 1304 1305define <2 x i8> @ashr_demanded_bits_splat(<2 x i8> %x) { 1306; CHECK-LABEL: @ashr_demanded_bits_splat( 1307; CHECK-NEXT: [[SHR:%.*]] = ashr <2 x i8> %x, <i8 7, i8 7> 1308; CHECK-NEXT: ret <2 x i8> [[SHR]] 1309; 1310 %and = and <2 x i8> %x, <i8 128, i8 128> 1311 %shr = ashr <2 x i8> %and, <i8 7, i8 7> 1312 ret <2 x i8> %shr 1313} 1314 1315define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) { 1316; CHECK-LABEL: @lshr_demanded_bits_splat( 1317; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> %x, <i8 7, i8 7> 1318; CHECK-NEXT: ret <2 x i8> [[SHR]] 1319; 1320 %and = and <2 x i8> %x, <i8 128, i8 128> 1321 %shr = lshr <2 x i8> %and, <i8 7, i8 7> 1322 ret <2 x i8> %shr 1323} 1324 1325; Make sure known bits works correctly with non power of 2 bit widths. 1326define i7 @test65(i7 %a, i7 %b) { 1327; CHECK-LABEL: @test65( 1328; CHECK-NEXT: ret i7 0 1329; 1330 %shiftamt = and i7 %b, 6 ; this ensures the shift amount is even and less than the bit width. 1331 %x = lshr i7 42, %shiftamt ; 42 has a zero in every even numbered bit and a one in every odd bit. 1332 %y = and i7 %x, 1 ; this extracts the lsb which should be 0 because we shifted an even number of bits and all even bits of the shift input are 0. 1333 ret i7 %y 1334} 1335 1336define i32 @shl_select_add_true(i32 %x, i1 %cond) { 1337; CHECK-LABEL: @shl_select_add_true( 1338; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1339; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14 1340; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1341; CHECK-NEXT: ret i32 [[TMP3]] 1342; 1343 %1 = add i32 %x, 7 1344 %2 = select i1 %cond, i32 %1, i32 %x 1345 %3 = shl i32 %2, 1 1346 ret i32 %3 1347} 1348 1349define i32 @shl_select_add_false(i32 %x, i1 %cond) { 1350; CHECK-LABEL: @shl_select_add_false( 1351; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1352; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14 1353; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1354; CHECK-NEXT: ret i32 [[TMP3]] 1355; 1356 %1 = add i32 %x, 7 1357 %2 = select i1 %cond, i32 %x, i32 %1 1358 %3 = shl i32 %2, 1 1359 ret i32 %3 1360} 1361 1362define i32 @shl_select_and_true(i32 %x, i1 %cond) { 1363; CHECK-LABEL: @shl_select_and_true( 1364; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1365; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14 1366; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1367; CHECK-NEXT: ret i32 [[TMP3]] 1368; 1369 %1 = and i32 %x, 7 1370 %2 = select i1 %cond, i32 %1, i32 %x 1371 %3 = shl i32 %2, 1 1372 ret i32 %3 1373} 1374 1375define i32 @shl_select_and_false(i32 %x, i1 %cond) { 1376; CHECK-LABEL: @shl_select_and_false( 1377; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1378; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14 1379; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1380; CHECK-NEXT: ret i32 [[TMP3]] 1381; 1382 %1 = and i32 %x, 7 1383 %2 = select i1 %cond, i32 %x, i32 %1 1384 %3 = shl i32 %2, 1 1385 ret i32 %3 1386} 1387 1388define i32 @lshr_select_and_true(i32 %x, i1 %cond) { 1389; CHECK-LABEL: @lshr_select_and_true( 1390; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1391; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3 1392; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1393; CHECK-NEXT: ret i32 [[TMP3]] 1394; 1395 %1 = and i32 %x, 7 1396 %2 = select i1 %cond, i32 %1, i32 %x 1397 %3 = lshr i32 %2, 1 1398 ret i32 %3 1399} 1400 1401define i32 @lshr_select_and_false(i32 %x, i1 %cond) { 1402; CHECK-LABEL: @lshr_select_and_false( 1403; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1404; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3 1405; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1406; CHECK-NEXT: ret i32 [[TMP3]] 1407; 1408 %1 = and i32 %x, 7 1409 %2 = select i1 %cond, i32 %x, i32 %1 1410 %3 = lshr i32 %2, 1 1411 ret i32 %3 1412} 1413 1414define i32 @ashr_select_and_true(i32 %x, i1 %cond) { 1415; CHECK-LABEL: @ashr_select_and_true( 1416; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1417; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821 1418; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1419; CHECK-NEXT: ret i32 [[TMP3]] 1420; 1421 %1 = and i32 %x, 2147483655 1422 %2 = select i1 %cond, i32 %1, i32 %x 1423 %3 = ashr i32 %2, 1 1424 ret i32 %3 1425} 1426 1427define i32 @ashr_select_and_false(i32 %x, i1 %cond) { 1428; CHECK-LABEL: @ashr_select_and_false( 1429; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1430; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821 1431; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1432; CHECK-NEXT: ret i32 [[TMP3]] 1433; 1434 %1 = and i32 %x, 2147483655 1435 %2 = select i1 %cond, i32 %x, i32 %1 1436 %3 = ashr i32 %2, 1 1437 ret i32 %3 1438} 1439 1440define i32 @shl_select_or_true(i32 %x, i1 %cond) { 1441; CHECK-LABEL: @shl_select_or_true( 1442; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1443; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14 1444; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1445; CHECK-NEXT: ret i32 [[TMP3]] 1446; 1447 %1 = or i32 %x, 7 1448 %2 = select i1 %cond, i32 %1, i32 %x 1449 %3 = shl i32 %2, 1 1450 ret i32 %3 1451} 1452 1453define i32 @shl_select_or_false(i32 %x, i1 %cond) { 1454; CHECK-LABEL: @shl_select_or_false( 1455; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1456; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14 1457; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1458; CHECK-NEXT: ret i32 [[TMP3]] 1459; 1460 %1 = or i32 %x, 7 1461 %2 = select i1 %cond, i32 %x, i32 %1 1462 %3 = shl i32 %2, 1 1463 ret i32 %3 1464} 1465 1466define i32 @lshr_select_or_true(i32 %x, i1 %cond) { 1467; CHECK-LABEL: @lshr_select_or_true( 1468; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1469; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1470; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1471; CHECK-NEXT: ret i32 [[TMP3]] 1472; 1473 %1 = or i32 %x, 7 1474 %2 = select i1 %cond, i32 %1, i32 %x 1475 %3 = lshr i32 %2, 1 1476 ret i32 %3 1477} 1478 1479define i32 @lshr_select_or_false(i32 %x, i1 %cond) { 1480; CHECK-LABEL: @lshr_select_or_false( 1481; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1482; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1483; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1484; CHECK-NEXT: ret i32 [[TMP3]] 1485; 1486 %1 = or i32 %x, 7 1487 %2 = select i1 %cond, i32 %x, i32 %1 1488 %3 = lshr i32 %2, 1 1489 ret i32 %3 1490} 1491 1492define i32 @ashr_select_or_true(i32 %x, i1 %cond) { 1493; CHECK-LABEL: @ashr_select_or_true( 1494; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1495; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1496; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1497; CHECK-NEXT: ret i32 [[TMP3]] 1498; 1499 %1 = or i32 %x, 7 1500 %2 = select i1 %cond, i32 %1, i32 %x 1501 %3 = ashr i32 %2, 1 1502 ret i32 %3 1503} 1504 1505define i32 @ashr_select_or_false(i32 %x, i1 %cond) { 1506; CHECK-LABEL: @ashr_select_or_false( 1507; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1508; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1509; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1510; CHECK-NEXT: ret i32 [[TMP3]] 1511; 1512 %1 = or i32 %x, 7 1513 %2 = select i1 %cond, i32 %x, i32 %1 1514 %3 = ashr i32 %2, 1 1515 ret i32 %3 1516} 1517 1518define i32 @shl_select_xor_true(i32 %x, i1 %cond) { 1519; CHECK-LABEL: @shl_select_xor_true( 1520; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1521; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14 1522; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1523; CHECK-NEXT: ret i32 [[TMP3]] 1524; 1525 %1 = xor i32 %x, 7 1526 %2 = select i1 %cond, i32 %1, i32 %x 1527 %3 = shl i32 %2, 1 1528 ret i32 %3 1529} 1530 1531define i32 @shl_select_xor_false(i32 %x, i1 %cond) { 1532; CHECK-LABEL: @shl_select_xor_false( 1533; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1534; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14 1535; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1536; CHECK-NEXT: ret i32 [[TMP3]] 1537; 1538 %1 = xor i32 %x, 7 1539 %2 = select i1 %cond, i32 %x, i32 %1 1540 %3 = shl i32 %2, 1 1541 ret i32 %3 1542} 1543 1544define i32 @lshr_select_xor_true(i32 %x, i1 %cond) { 1545; CHECK-LABEL: @lshr_select_xor_true( 1546; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1547; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1548; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1549; CHECK-NEXT: ret i32 [[TMP3]] 1550; 1551 %1 = xor i32 %x, 7 1552 %2 = select i1 %cond, i32 %1, i32 %x 1553 %3 = lshr i32 %2, 1 1554 ret i32 %3 1555} 1556 1557define i32 @lshr_select_xor_false(i32 %x, i1 %cond) { 1558; CHECK-LABEL: @lshr_select_xor_false( 1559; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1560; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1561; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1562; CHECK-NEXT: ret i32 [[TMP3]] 1563; 1564 %1 = xor i32 %x, 7 1565 %2 = select i1 %cond, i32 %x, i32 %1 1566 %3 = lshr i32 %2, 1 1567 ret i32 %3 1568} 1569 1570define i32 @ashr_select_xor_true(i32 %x, i1 %cond) { 1571; CHECK-LABEL: @ashr_select_xor_true( 1572; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1573; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1574; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1575; CHECK-NEXT: ret i32 [[TMP3]] 1576; 1577 %1 = xor i32 %x, 7 1578 %2 = select i1 %cond, i32 %1, i32 %x 1579 %3 = ashr i32 %2, 1 1580 ret i32 %3 1581} 1582 1583define i32 @ashr_select_xor_false(i32 %x, i1 %cond) { 1584; CHECK-LABEL: @ashr_select_xor_false( 1585; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1586; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1587; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1588; CHECK-NEXT: ret i32 [[TMP3]] 1589; 1590 %1 = xor i32 %x, 7 1591 %2 = select i1 %cond, i32 %x, i32 %1 1592 %3 = ashr i32 %2, 1 1593 ret i32 %3 1594} 1595