1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; This test makes sure that these instructions are properly eliminated. 3; 4; RUN: opt < %s -instcombine -S | FileCheck %s 5 6define i32 @test1(i32 %A) { 7; CHECK-LABEL: @test1( 8; CHECK-NEXT: ret i32 %A 9; 10 %B = shl i32 %A, 0 11 ret i32 %B 12} 13 14define i32 @test2(i8 %A) { 15; CHECK-LABEL: @test2( 16; CHECK-NEXT: ret i32 0 17; 18 %shift.upgrd.1 = zext i8 %A to i32 19 %B = shl i32 0, %shift.upgrd.1 20 ret i32 %B 21} 22 23define i32 @test3(i32 %A) { 24; CHECK-LABEL: @test3( 25; CHECK-NEXT: ret i32 %A 26; 27 %B = ashr i32 %A, 0 28 ret i32 %B 29} 30 31define i32 @test4(i8 %A) { 32; CHECK-LABEL: @test4( 33; CHECK-NEXT: ret i32 0 34; 35 %shift.upgrd.2 = zext i8 %A to i32 36 %B = ashr i32 0, %shift.upgrd.2 37 ret i32 %B 38} 39 40define i32 @test5(i32 %A) { 41; CHECK-LABEL: @test5( 42; CHECK-NEXT: ret i32 undef 43; 44 %B = lshr i32 %A, 32 ;; shift all bits out 45 ret i32 %B 46} 47 48define <4 x i32> @test5_splat_vector(<4 x i32> %A) { 49; CHECK-LABEL: @test5_splat_vector( 50; CHECK-NEXT: ret <4 x i32> undef 51; 52 %B = lshr <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out 53 ret <4 x i32> %B 54} 55 56define <4 x i32> @test5_zero_vector(<4 x i32> %A) { 57; CHECK-LABEL: @test5_zero_vector( 58; CHECK-NEXT: ret <4 x i32> %A 59; 60 %B = lshr <4 x i32> %A, zeroinitializer 61 ret <4 x i32> %B 62} 63 64define <4 x i32> @test5_non_splat_vector(<4 x i32> %A) { 65; CHECK-LABEL: @test5_non_splat_vector( 66; CHECK-NEXT: [[B:%.*]] = lshr <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 67; CHECK-NEXT: ret <4 x i32> [[B]] 68; 69 %B = lshr <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 70 ret <4 x i32> %B 71} 72 73define i32 @test5a(i32 %A) { 74; CHECK-LABEL: @test5a( 75; CHECK-NEXT: ret i32 undef 76; 77 %B = shl i32 %A, 32 ;; shift all bits out 78 ret i32 %B 79} 80 81define <4 x i32> @test5a_splat_vector(<4 x i32> %A) { 82; CHECK-LABEL: @test5a_splat_vector( 83; CHECK-NEXT: ret <4 x i32> undef 84; 85 %B = shl <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out 86 ret <4 x i32> %B 87} 88 89define <4 x i32> @test5a_non_splat_vector(<4 x i32> %A) { 90; CHECK-LABEL: @test5a_non_splat_vector( 91; CHECK-NEXT: [[B:%.*]] = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 92; CHECK-NEXT: ret <4 x i32> [[B]] 93; 94 %B = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 95 ret <4 x i32> %B 96} 97 98define i32 @test5b() { 99; CHECK-LABEL: @test5b( 100; CHECK-NEXT: ret i32 0 101; 102 %B = ashr i32 undef, 2 ;; top two bits must be equal, so not undef 103 ret i32 %B 104} 105 106define i32 @test5b2(i32 %A) { 107; CHECK-LABEL: @test5b2( 108; CHECK-NEXT: ret i32 0 109; 110 %B = ashr i32 undef, %A ;; top %A bits must be equal, so not undef 111 ret i32 %B 112} 113 114define i32 @test6(i32 %A) { 115; CHECK-LABEL: @test6( 116; CHECK-NEXT: [[C:%.*]] = mul i32 %A, 6 117; CHECK-NEXT: ret i32 [[C]] 118; 119 %B = shl i32 %A, 1 ;; convert to an mul instruction 120 %C = mul i32 %B, 3 121 ret i32 %C 122} 123 124define i32 @test6a(i32 %A) { 125; CHECK-LABEL: @test6a( 126; CHECK-NEXT: [[C:%.*]] = mul i32 %A, 6 127; CHECK-NEXT: ret i32 [[C]] 128; 129 %B = mul i32 %A, 3 130 %C = shl i32 %B, 1 ;; convert to an mul instruction 131 ret i32 %C 132} 133 134define i32 @test7(i8 %A) { 135; CHECK-LABEL: @test7( 136; CHECK-NEXT: ret i32 -1 137; 138 %shift.upgrd.3 = zext i8 %A to i32 139 %B = ashr i32 -1, %shift.upgrd.3 ;; Always equal to -1 140 ret i32 %B 141} 142 143;; (A << 5) << 3 === A << 8 == 0 144define i8 @test8(i8 %A) { 145; CHECK-LABEL: @test8( 146; CHECK-NEXT: ret i8 0 147; 148 %B = shl i8 %A, 5 149 %C = shl i8 %B, 3 150 ret i8 %C 151} 152 153;; (A << 7) >> 7 === A & 1 154define i8 @test9(i8 %A) { 155; CHECK-LABEL: @test9( 156; CHECK-NEXT: [[B:%.*]] = and i8 %A, 1 157; CHECK-NEXT: ret i8 [[B]] 158; 159 %B = shl i8 %A, 7 160 %C = lshr i8 %B, 7 161 ret i8 %C 162} 163 164;; This transformation is deferred to DAGCombine: 165;; (A >> 7) << 7 === A & 128 166;; The shl may be valuable to scalar evolution. 167define i8 @test10(i8 %A) { 168; CHECK-LABEL: @test10( 169; CHECK-NEXT: [[B:%.*]] = and i8 %A, -128 170; CHECK-NEXT: ret i8 [[B]] 171; 172 %B = lshr i8 %A, 7 173 %C = shl i8 %B, 7 174 ret i8 %C 175} 176 177;; Allow the simplification when the lshr shift is exact. 178define i8 @test10a(i8 %A) { 179; CHECK-LABEL: @test10a( 180; CHECK-NEXT: ret i8 %A 181; 182 %B = lshr exact i8 %A, 7 183 %C = shl i8 %B, 7 184 ret i8 %C 185} 186 187;; This transformation is deferred to DAGCombine: 188;; (A >> 3) << 4 === (A & 0x1F) << 1 189;; The shl may be valuable to scalar evolution. 190define i8 @test11(i8 %A) { 191; CHECK-LABEL: @test11( 192; CHECK-NEXT: [[A:%.*]] = mul i8 %A, 3 193; CHECK-NEXT: [[B:%.*]] = lshr i8 [[A]], 3 194; CHECK-NEXT: [[C:%.*]] = shl i8 [[B]], 4 195; CHECK-NEXT: ret i8 [[C]] 196; 197 %a = mul i8 %A, 3 198 %B = lshr i8 %a, 3 199 %C = shl i8 %B, 4 200 ret i8 %C 201} 202 203;; Allow the simplification in InstCombine when the lshr shift is exact. 204define i8 @test11a(i8 %A) { 205; CHECK-LABEL: @test11a( 206; CHECK-NEXT: [[C:%.*]] = mul i8 %A, 6 207; CHECK-NEXT: ret i8 [[C]] 208; 209 %a = mul i8 %A, 3 210 %B = lshr exact i8 %a, 3 211 %C = shl i8 %B, 4 212 ret i8 %C 213} 214 215;; This is deferred to DAGCombine unless %B is single-use. 216;; (A >> 8) << 8 === A & -256 217define i32 @test12(i32 %A) { 218; CHECK-LABEL: @test12( 219; CHECK-NEXT: [[B1:%.*]] = and i32 %A, -256 220; CHECK-NEXT: ret i32 [[B1]] 221; 222 %B = ashr i32 %A, 8 223 %C = shl i32 %B, 8 224 ret i32 %C 225} 226 227;; This transformation is deferred to DAGCombine: 228;; (A >> 3) << 4 === (A & -8) * 2 229;; The shl may be valuable to scalar evolution. 230define i8 @test13(i8 %A) { 231; CHECK-LABEL: @test13( 232; CHECK-NEXT: [[A:%.*]] = mul i8 %A, 3 233; CHECK-NEXT: [[B1:%.*]] = lshr i8 [[A]], 3 234; CHECK-NEXT: [[C:%.*]] = shl i8 [[B1]], 4 235; CHECK-NEXT: ret i8 [[C]] 236; 237 %a = mul i8 %A, 3 238 %B = ashr i8 %a, 3 239 %C = shl i8 %B, 4 240 ret i8 %C 241} 242 243define i8 @test13a(i8 %A) { 244; CHECK-LABEL: @test13a( 245; CHECK-NEXT: [[C:%.*]] = mul i8 %A, 6 246; CHECK-NEXT: ret i8 [[C]] 247; 248 %a = mul i8 %A, 3 249 %B = ashr exact i8 %a, 3 250 %C = shl i8 %B, 4 251 ret i8 %C 252} 253 254;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4) 255define i32 @test14(i32 %A) { 256; CHECK-LABEL: @test14( 257; CHECK-NEXT: [[B:%.*]] = and i32 %A, -19760 258; CHECK-NEXT: [[C:%.*]] = or i32 [[B]], 19744 259; CHECK-NEXT: ret i32 [[C]] 260; 261 %B = lshr i32 %A, 4 262 %C = or i32 %B, 1234 263 %D = shl i32 %C, 4 264 ret i32 %D 265} 266 267;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4) 268define i32 @test14a(i32 %A) { 269; CHECK-LABEL: @test14a( 270; CHECK-NEXT: [[C:%.*]] = and i32 %A, 77 271; CHECK-NEXT: ret i32 [[C]] 272; 273 %B = shl i32 %A, 4 274 %C = and i32 %B, 1234 275 %D = lshr i32 %C, 4 276 ret i32 %D 277} 278 279define i32 @test15(i1 %C) { 280; CHECK-LABEL: @test15( 281; CHECK-NEXT: [[A:%.*]] = select i1 %C, i32 12, i32 4 282; CHECK-NEXT: ret i32 [[A]] 283; 284 %A = select i1 %C, i32 3, i32 1 285 %V = shl i32 %A, 2 286 ret i32 %V 287} 288 289define i32 @test15a(i1 %C) { 290; CHECK-LABEL: @test15a( 291; CHECK-NEXT: [[V:%.*]] = select i1 %C, i32 512, i32 128 292; CHECK-NEXT: ret i32 [[V]] 293; 294 %A = select i1 %C, i8 3, i8 1 295 %shift.upgrd.4 = zext i8 %A to i32 296 %V = shl i32 64, %shift.upgrd.4 297 ret i32 %V 298} 299 300define i1 @test16(i32 %X) { 301; CHECK-LABEL: @test16( 302; CHECK-NEXT: [[TMP_6:%.*]] = and i32 %X, 16 303; CHECK-NEXT: [[TMP_7:%.*]] = icmp ne i32 [[TMP_6]], 0 304; CHECK-NEXT: ret i1 [[TMP_7]] 305; 306 %tmp.3 = ashr i32 %X, 4 307 %tmp.6 = and i32 %tmp.3, 1 308 %tmp.7 = icmp ne i32 %tmp.6, 0 309 ret i1 %tmp.7 310} 311 312define i1 @test17(i32 %A) { 313; CHECK-LABEL: @test17( 314; CHECK-NEXT: [[B_MASK:%.*]] = and i32 %A, -8 315; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[B_MASK]], 9872 316; CHECK-NEXT: ret i1 [[C]] 317; 318 %B = lshr i32 %A, 3 319 %C = icmp eq i32 %B, 1234 320 ret i1 %C 321} 322 323define <2 x i1> @test17vec(<2 x i32> %A) { 324; CHECK-LABEL: @test17vec( 325; CHECK-NEXT: [[B_MASK:%.*]] = and <2 x i32> %A, <i32 -8, i32 -8> 326; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i32> [[B_MASK]], <i32 9872, i32 9872> 327; CHECK-NEXT: ret <2 x i1> [[C]] 328; 329 %B = lshr <2 x i32> %A, <i32 3, i32 3> 330 %C = icmp eq <2 x i32> %B, <i32 1234, i32 1234> 331 ret <2 x i1> %C 332} 333 334define i1 @test18(i8 %A) { 335; CHECK-LABEL: @test18( 336; CHECK-NEXT: ret i1 false 337; 338 %B = lshr i8 %A, 7 339 ;; false 340 %C = icmp eq i8 %B, 123 341 ret i1 %C 342} 343 344define i1 @test19(i32 %A) { 345; CHECK-LABEL: @test19( 346; CHECK-NEXT: [[C:%.*]] = icmp ult i32 %A, 4 347; CHECK-NEXT: ret i1 [[C]] 348; 349 %B = ashr i32 %A, 2 350 ;; (X & -4) == 0 351 %C = icmp eq i32 %B, 0 352 ret i1 %C 353} 354 355define <2 x i1> @test19vec(<2 x i32> %A) { 356; CHECK-LABEL: @test19vec( 357; CHECK-NEXT: [[C:%.*]] = icmp ult <2 x i32> %A, <i32 4, i32 4> 358; CHECK-NEXT: ret <2 x i1> [[C]] 359; 360 %B = ashr <2 x i32> %A, <i32 2, i32 2> 361 %C = icmp eq <2 x i32> %B, zeroinitializer 362 ret <2 x i1> %C 363} 364 365;; X >u ~4 366define i1 @test19a(i32 %A) { 367; CHECK-LABEL: @test19a( 368; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 %A, -5 369; CHECK-NEXT: ret i1 [[C]] 370; 371 %B = ashr i32 %A, 2 372 %C = icmp eq i32 %B, -1 373 ret i1 %C 374} 375 376define <2 x i1> @test19a_vec(<2 x i32> %A) { 377; CHECK-LABEL: @test19a_vec( 378; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> %A, <i32 -5, i32 -5> 379; CHECK-NEXT: ret <2 x i1> [[C]] 380; 381 %B = ashr <2 x i32> %A, <i32 2, i32 2> 382 %C = icmp eq <2 x i32> %B, <i32 -1, i32 -1> 383 ret <2 x i1> %C 384} 385 386define i1 @test20(i8 %A) { 387; CHECK-LABEL: @test20( 388; CHECK-NEXT: ret i1 false 389; 390 %B = ashr i8 %A, 7 391 ;; false 392 %C = icmp eq i8 %B, 123 393 ret i1 %C 394} 395 396define i1 @test21(i8 %A) { 397; CHECK-LABEL: @test21( 398; CHECK-NEXT: [[B_MASK:%.*]] = and i8 %A, 15 399; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 8 400; CHECK-NEXT: ret i1 [[C]] 401; 402 %B = shl i8 %A, 4 403 %C = icmp eq i8 %B, -128 404 ret i1 %C 405} 406 407define i1 @test22(i8 %A) { 408; CHECK-LABEL: @test22( 409; CHECK-NEXT: [[B_MASK:%.*]] = and i8 %A, 15 410; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 0 411; CHECK-NEXT: ret i1 [[C]] 412; 413 %B = shl i8 %A, 4 414 %C = icmp eq i8 %B, 0 415 ret i1 %C 416} 417 418define i8 @test23(i32 %A) { 419; CHECK-LABEL: @test23( 420; CHECK-NEXT: [[D:%.*]] = trunc i32 %A to i8 421; CHECK-NEXT: ret i8 [[D]] 422; 423 ;; casts not needed 424 %B = shl i32 %A, 24 425 %C = ashr i32 %B, 24 426 %D = trunc i32 %C to i8 427 ret i8 %D 428} 429 430define i8 @test24(i8 %X) { 431; CHECK-LABEL: @test24( 432; CHECK-NEXT: [[Z:%.*]] = and i8 %X, 3 433; CHECK-NEXT: ret i8 [[Z]] 434; 435 %Y = and i8 %X, -5 436 %Z = shl i8 %Y, 5 437 %Q = ashr i8 %Z, 5 438 ret i8 %Q 439} 440 441define i32 @test25(i32 %tmp.2, i32 %AA) { 442; CHECK-LABEL: @test25( 443; CHECK-NEXT: [[TMP_3:%.*]] = and i32 %tmp.2, -131072 444; CHECK-NEXT: [[X2:%.*]] = add i32 [[TMP_3]], %AA 445; CHECK-NEXT: [[TMP_6:%.*]] = and i32 [[X2]], -131072 446; CHECK-NEXT: ret i32 [[TMP_6]] 447; 448 %x = lshr i32 %AA, 17 449 %tmp.3 = lshr i32 %tmp.2, 17 450 %tmp.5 = add i32 %tmp.3, %x 451 %tmp.6 = shl i32 %tmp.5, 17 452 ret i32 %tmp.6 453} 454 455define <2 x i32> @test25_vector(<2 x i32> %tmp.2, <2 x i32> %AA) { 456; CHECK-LABEL: @test25_vector( 457; CHECK-NEXT: [[TMP_3:%.*]] = lshr <2 x i32> %tmp.2, <i32 17, i32 17> 458; CHECK-NEXT: [[TMP_51:%.*]] = shl <2 x i32> [[TMP_3]], <i32 17, i32 17> 459; CHECK-NEXT: [[X2:%.*]] = add <2 x i32> [[TMP_51]], %AA 460; CHECK-NEXT: [[TMP_6:%.*]] = and <2 x i32> [[X2]], <i32 -131072, i32 -131072> 461; CHECK-NEXT: ret <2 x i32> [[TMP_6]] 462; 463 %x = lshr <2 x i32> %AA, <i32 17, i32 17> 464 %tmp.3 = lshr <2 x i32> %tmp.2, <i32 17, i32 17> 465 %tmp.5 = add <2 x i32> %tmp.3, %x 466 %tmp.6 = shl <2 x i32> %tmp.5, <i32 17, i32 17> 467 ret <2 x i32> %tmp.6 468} 469 470;; handle casts between shifts. 471define i32 @test26(i32 %A) { 472; CHECK-LABEL: @test26( 473; CHECK-NEXT: [[B:%.*]] = and i32 %A, -2 474; CHECK-NEXT: ret i32 [[B]] 475; 476 %B = lshr i32 %A, 1 477 %C = bitcast i32 %B to i32 478 %D = shl i32 %C, 1 479 ret i32 %D 480} 481 482 483define i1 @test27(i32 %x) nounwind { 484; CHECK-LABEL: @test27( 485; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 8 486; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[TMP1]], 0 487; CHECK-NEXT: ret i1 [[Z]] 488; 489 %y = lshr i32 %x, 3 490 %z = trunc i32 %y to i1 491 ret i1 %z 492} 493 494define i1 @test28(i8 %x) { 495; CHECK-LABEL: @test28( 496; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 %x, 0 497; CHECK-NEXT: ret i1 [[CMP]] 498; 499 %shr = lshr i8 %x, 7 500 %cmp = icmp ne i8 %shr, 0 501 ret i1 %cmp 502} 503 504define <2 x i1> @test28vec(<2 x i8> %x) { 505; CHECK-LABEL: @test28vec( 506; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> %x, zeroinitializer 507; CHECK-NEXT: ret <2 x i1> [[CMP]] 508; 509 %shr = lshr <2 x i8> %x, <i8 7, i8 7> 510 %cmp = icmp ne <2 x i8> %shr, zeroinitializer 511 ret <2 x i1> %cmp 512} 513 514define i8 @test28a(i8 %x, i8 %y) { 515; CHECK-LABEL: @test28a( 516; CHECK-NEXT: entry: 517; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 %x, 7 518; CHECK-NEXT: [[COND1:%.*]] = icmp eq i8 [[TMP1]], 0 519; CHECK-NEXT: br i1 [[COND1]], label %bb2, label %bb1 520; CHECK: bb1: 521; CHECK-NEXT: ret i8 [[TMP1]] 522; CHECK: bb2: 523; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], %y 524; CHECK-NEXT: ret i8 [[TMP2]] 525; 526entry: 527; This shouldn't be transformed. 528 %tmp1 = lshr i8 %x, 7 529 %cond1 = icmp ne i8 %tmp1, 0 530 br i1 %cond1, label %bb1, label %bb2 531bb1: 532 ret i8 %tmp1 533bb2: 534 %tmp2 = add i8 %tmp1, %y 535 ret i8 %tmp2 536} 537 538 539define i32 @test29(i64 %d18) { 540; CHECK-LABEL: @test29( 541; CHECK-NEXT: entry: 542; CHECK-NEXT: [[TMP916:%.*]] = lshr i64 %d18, 63 543; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP916]] to i32 544; CHECK-NEXT: ret i32 [[TMP10]] 545; 546entry: 547 %tmp916 = lshr i64 %d18, 32 548 %tmp917 = trunc i64 %tmp916 to i32 549 %tmp10 = lshr i32 %tmp917, 31 550 ret i32 %tmp10 551} 552 553 554define i32 @test30(i32 %A, i32 %B, i32 %C) { 555; CHECK-LABEL: @test30( 556; CHECK-NEXT: [[X1:%.*]] = and i32 %A, %B 557; CHECK-NEXT: [[Z:%.*]] = shl i32 [[X1]], %C 558; CHECK-NEXT: ret i32 [[Z]] 559; 560 %X = shl i32 %A, %C 561 %Y = shl i32 %B, %C 562 %Z = and i32 %X, %Y 563 ret i32 %Z 564} 565 566define i32 @test31(i32 %A, i32 %B, i32 %C) { 567; CHECK-LABEL: @test31( 568; CHECK-NEXT: [[X1:%.*]] = or i32 %A, %B 569; CHECK-NEXT: [[Z:%.*]] = lshr i32 [[X1]], %C 570; CHECK-NEXT: ret i32 [[Z]] 571; 572 %X = lshr i32 %A, %C 573 %Y = lshr i32 %B, %C 574 %Z = or i32 %X, %Y 575 ret i32 %Z 576} 577 578define i32 @test32(i32 %A, i32 %B, i32 %C) { 579; CHECK-LABEL: @test32( 580; CHECK-NEXT: [[X1:%.*]] = xor i32 %A, %B 581; CHECK-NEXT: [[Z:%.*]] = ashr i32 [[X1]], %C 582; CHECK-NEXT: ret i32 [[Z]] 583; 584 %X = ashr i32 %A, %C 585 %Y = ashr i32 %B, %C 586 %Z = xor i32 %X, %Y 587 ret i32 %Z 588} 589 590define i1 @test33(i32 %X) { 591; CHECK-LABEL: @test33( 592; CHECK-NEXT: [[TMP1_MASK:%.*]] = and i32 %X, 16777216 593; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1_MASK]], 0 594; CHECK-NEXT: ret i1 [[TMP2]] 595; 596 %tmp1 = shl i32 %X, 7 597 %tmp2 = icmp slt i32 %tmp1, 0 598 ret i1 %tmp2 599} 600 601define <2 x i1> @test33vec(<2 x i32> %X) { 602; CHECK-LABEL: @test33vec( 603; CHECK-NEXT: [[TMP1_MASK:%.*]] = and <2 x i32> %X, <i32 16777216, i32 16777216> 604; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1_MASK]], zeroinitializer 605; CHECK-NEXT: ret <2 x i1> [[TMP2]] 606; 607 %tmp1 = shl <2 x i32> %X, <i32 7, i32 7> 608 %tmp2 = icmp slt <2 x i32> %tmp1, zeroinitializer 609 ret <2 x i1> %tmp2 610} 611 612define i1 @test34(i32 %X) { 613; CHECK-LABEL: @test34( 614; CHECK-NEXT: ret i1 false 615; 616 %tmp1 = lshr i32 %X, 7 617 %tmp2 = icmp slt i32 %tmp1, 0 618 ret i1 %tmp2 619} 620 621define i1 @test35(i32 %X) { 622; CHECK-LABEL: @test35( 623; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 %X, 0 624; CHECK-NEXT: ret i1 [[TMP2]] 625; 626 %tmp1 = ashr i32 %X, 7 627 %tmp2 = icmp slt i32 %tmp1, 0 628 ret i1 %tmp2 629} 630 631define <2 x i1> @test35vec(<2 x i32> %X) { 632; CHECK-LABEL: @test35vec( 633; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> %X, zeroinitializer 634; CHECK-NEXT: ret <2 x i1> [[TMP2]] 635; 636 %tmp1 = ashr <2 x i32> %X, <i32 7, i32 7> 637 %tmp2 = icmp slt <2 x i32> %tmp1, zeroinitializer 638 ret <2 x i1> %tmp2 639} 640 641define i128 @test36(i128 %A, i128 %B) { 642; CHECK-LABEL: @test36( 643; CHECK-NEXT: entry: 644; CHECK-NEXT: [[TMP231:%.*]] = or i128 %B, %A 645; CHECK-NEXT: [[INS:%.*]] = and i128 [[TMP231]], 18446744073709551615 646; CHECK-NEXT: ret i128 [[INS]] 647; 648entry: 649 %tmp27 = shl i128 %A, 64 650 %tmp23 = shl i128 %B, 64 651 %ins = or i128 %tmp23, %tmp27 652 %tmp45 = lshr i128 %ins, 64 653 ret i128 %tmp45 654 655} 656 657define i64 @test37(i128 %A, i32 %B) { 658; CHECK-LABEL: @test37( 659; CHECK-NEXT: entry: 660; CHECK-NEXT: [[TMP22:%.*]] = zext i32 %B to i128 661; CHECK-NEXT: [[TMP23:%.*]] = shl nuw nsw i128 [[TMP22]], 32 662; CHECK-NEXT: [[INS:%.*]] = or i128 [[TMP23]], %A 663; CHECK-NEXT: [[TMP46:%.*]] = trunc i128 [[INS]] to i64 664; CHECK-NEXT: ret i64 [[TMP46]] 665; 666entry: 667 %tmp27 = shl i128 %A, 64 668 %tmp22 = zext i32 %B to i128 669 %tmp23 = shl i128 %tmp22, 96 670 %ins = or i128 %tmp23, %tmp27 671 %tmp45 = lshr i128 %ins, 64 672 %tmp46 = trunc i128 %tmp45 to i64 673 ret i64 %tmp46 674 675} 676 677define i32 @test38(i32 %x) nounwind readnone { 678; CHECK-LABEL: @test38( 679; CHECK-NEXT: [[REM1:%.*]] = and i32 %x, 31 680; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[REM1]] 681; CHECK-NEXT: ret i32 [[SHL]] 682; 683 %rem = srem i32 %x, 32 684 %shl = shl i32 1, %rem 685 ret i32 %shl 686} 687 688; <rdar://problem/8756731> 689define i8 @test39(i32 %a0) { 690; CHECK-LABEL: @test39( 691; CHECK-NEXT: entry: 692; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 %a0 to i8 693; CHECK-NEXT: [[TMP5:%.*]] = shl i8 [[TMP4]], 5 694; CHECK-NEXT: [[TMP49:%.*]] = shl i8 [[TMP4]], 6 695; CHECK-NEXT: [[TMP50:%.*]] = and i8 [[TMP49]], 64 696; CHECK-NEXT: [[TMP51:%.*]] = xor i8 [[TMP50]], [[TMP5]] 697; CHECK-NEXT: [[TMP0:%.*]] = shl i8 [[TMP4]], 2 698; CHECK-NEXT: [[TMP54:%.*]] = and i8 [[TMP0]], 16 699; CHECK-NEXT: [[TMP551:%.*]] = or i8 [[TMP54]], [[TMP51]] 700; CHECK-NEXT: ret i8 [[TMP551]] 701; 702entry: 703 %tmp4 = trunc i32 %a0 to i8 704 %tmp5 = shl i8 %tmp4, 5 705 %tmp48 = and i8 %tmp5, 32 706 %tmp49 = lshr i8 %tmp48, 5 707 %tmp50 = mul i8 %tmp49, 64 708 %tmp51 = xor i8 %tmp50, %tmp5 709 %tmp52 = and i8 %tmp51, -128 710 %tmp53 = lshr i8 %tmp52, 7 711 %tmp54 = mul i8 %tmp53, 16 712 %tmp55 = xor i8 %tmp54, %tmp51 713 ret i8 %tmp55 714} 715 716; PR9809 717define i32 @test40(i32 %a, i32 %b) nounwind { 718; CHECK-LABEL: @test40( 719; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, 2 720; CHECK-NEXT: [[DIV:%.*]] = lshr i32 %a, [[TMP1]] 721; CHECK-NEXT: ret i32 [[DIV]] 722; 723 %shl1 = shl i32 1, %b 724 %shl2 = shl i32 %shl1, 2 725 %div = udiv i32 %a, %shl2 726 ret i32 %div 727} 728 729define i32 @test41(i32 %a, i32 %b) nounwind { 730; CHECK-LABEL: @test41( 731; CHECK-NEXT: [[TMP1:%.*]] = shl i32 8, %b 732; CHECK-NEXT: ret i32 [[TMP1]] 733; 734 %1 = shl i32 1, %b 735 %2 = shl i32 %1, 3 736 ret i32 %2 737} 738 739define i32 @test42(i32 %a, i32 %b) nounwind { 740; CHECK-LABEL: @test42( 741; CHECK-NEXT: [[DIV:%.*]] = lshr exact i32 4096, %b 742; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 %a, [[DIV]] 743; CHECK-NEXT: ret i32 [[DIV2]] 744; 745 %div = lshr i32 4096, %b ; must be exact otherwise we'd divide by zero 746 %div2 = udiv i32 %a, %div 747 ret i32 %div2 748} 749 750define <2 x i32> @test42vec(<2 x i32> %a, <2 x i32> %b) { 751; CHECK-LABEL: @test42vec( 752; CHECK-NEXT: [[DIV:%.*]] = lshr exact <2 x i32> <i32 4096, i32 4096>, %b 753; CHECK-NEXT: [[DIV2:%.*]] = udiv <2 x i32> %a, [[DIV]] 754; CHECK-NEXT: ret <2 x i32> [[DIV2]] 755; 756 %div = lshr <2 x i32> <i32 4096, i32 4096>, %b ; must be exact otherwise we'd divide by zero 757 %div2 = udiv <2 x i32> %a, %div 758 ret <2 x i32> %div2 759} 760 761define i32 @test43(i32 %a, i32 %b) nounwind { 762; CHECK-LABEL: @test43( 763; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, 12 764; CHECK-NEXT: [[DIV2:%.*]] = lshr i32 %a, [[TMP1]] 765; CHECK-NEXT: ret i32 [[DIV2]] 766; 767 %div = shl i32 4096, %b ; must be exact otherwise we'd divide by zero 768 %div2 = udiv i32 %a, %div 769 ret i32 %div2 770} 771 772define i32 @test44(i32 %a) nounwind { 773; CHECK-LABEL: @test44( 774; CHECK-NEXT: [[Y:%.*]] = shl i32 %a, 5 775; CHECK-NEXT: ret i32 [[Y]] 776; 777 %y = shl nuw i32 %a, 1 778 %z = shl i32 %y, 4 779 ret i32 %z 780} 781 782define i32 @test45(i32 %a) nounwind { 783; CHECK-LABEL: @test45( 784; CHECK-NEXT: [[Y:%.*]] = lshr i32 %a, 5 785; CHECK-NEXT: ret i32 [[Y]] 786; 787 %y = lshr exact i32 %a, 1 788 %z = lshr i32 %y, 4 789 ret i32 %z 790} 791 792define i32 @test46(i32 %a) { 793; CHECK-LABEL: @test46( 794; CHECK-NEXT: [[Z:%.*]] = ashr exact i32 %a, 2 795; CHECK-NEXT: ret i32 [[Z]] 796; 797 %y = ashr exact i32 %a, 3 798 %z = shl i32 %y, 1 799 ret i32 %z 800} 801 802define i32 @test47(i32 %a) { 803; CHECK-LABEL: @test47( 804; CHECK-NEXT: [[Z:%.*]] = lshr exact i32 %a, 2 805; CHECK-NEXT: ret i32 [[Z]] 806; 807 %y = lshr exact i32 %a, 3 808 %z = shl i32 %y, 1 809 ret i32 %z 810} 811 812define i32 @test48(i32 %x) { 813; CHECK-LABEL: @test48( 814; CHECK-NEXT: [[B:%.*]] = shl i32 %x, 2 815; CHECK-NEXT: ret i32 [[B]] 816; 817 %A = lshr exact i32 %x, 1 818 %B = shl i32 %A, 3 819 ret i32 %B 820} 821 822define i32 @test49(i32 %x) { 823; CHECK-LABEL: @test49( 824; CHECK-NEXT: [[B:%.*]] = shl i32 %x, 2 825; CHECK-NEXT: ret i32 [[B]] 826; 827 %A = ashr exact i32 %x, 1 828 %B = shl i32 %A, 3 829 ret i32 %B 830} 831 832define i32 @test50(i32 %x) { 833; CHECK-LABEL: @test50( 834; CHECK-NEXT: [[B:%.*]] = ashr i32 %x, 2 835; CHECK-NEXT: ret i32 [[B]] 836; 837 %A = shl nsw i32 %x, 1 838 %B = ashr i32 %A, 3 839 ret i32 %B 840} 841 842define i32 @test51(i32 %x) { 843; CHECK-LABEL: @test51( 844; CHECK-NEXT: [[B:%.*]] = lshr i32 %x, 2 845; CHECK-NEXT: ret i32 [[B]] 846; 847 %A = shl nuw i32 %x, 1 848 %B = lshr i32 %A, 3 849 ret i32 %B 850} 851 852define i32 @test52(i32 %x) { 853; CHECK-LABEL: @test52( 854; CHECK-NEXT: [[B:%.*]] = shl nsw i32 %x, 2 855; CHECK-NEXT: ret i32 [[B]] 856; 857 %A = shl nsw i32 %x, 3 858 %B = ashr i32 %A, 1 859 ret i32 %B 860} 861 862define i32 @test53(i32 %x) { 863; CHECK-LABEL: @test53( 864; CHECK-NEXT: [[B:%.*]] = shl nuw i32 %x, 2 865; CHECK-NEXT: ret i32 [[B]] 866; 867 %A = shl nuw i32 %x, 3 868 %B = lshr i32 %A, 1 869 ret i32 %B 870} 871 872define i32 @test54(i32 %x) { 873; CHECK-LABEL: @test54( 874; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3 875; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP1]], 16 876; CHECK-NEXT: ret i32 [[AND]] 877; 878 %shr2 = lshr i32 %x, 1 879 %shl = shl i32 %shr2, 4 880 %and = and i32 %shl, 16 881 ret i32 %and 882} 883 884 885define i32 @test55(i32 %x) { 886; CHECK-LABEL: @test55( 887; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %x, 3 888; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 8 889; CHECK-NEXT: ret i32 [[OR]] 890; 891 %shr2 = lshr i32 %x, 1 892 %shl = shl i32 %shr2, 4 893 %or = or i32 %shl, 8 894 ret i32 %or 895} 896 897define i32 @test56(i32 %x) { 898; CHECK-LABEL: @test56( 899; CHECK-NEXT: [[SHR2:%.*]] = lshr i32 %x, 1 900; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[SHR2]], 4 901; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7 902; CHECK-NEXT: ret i32 [[OR]] 903; 904 %shr2 = lshr i32 %x, 1 905 %shl = shl i32 %shr2, 4 906 %or = or i32 %shl, 7 907 ret i32 %or 908} 909 910 911define i32 @test57(i32 %x) { 912; CHECK-LABEL: @test57( 913; CHECK-NEXT: [[SHR1:%.*]] = lshr i32 %x, 1 914; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[SHR1]], 4 915; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7 916; CHECK-NEXT: ret i32 [[OR]] 917; 918 %shr = ashr i32 %x, 1 919 %shl = shl i32 %shr, 4 920 %or = or i32 %shl, 7 921 ret i32 %or 922} 923 924 925define i32 @test58(i32 %x) { 926; CHECK-LABEL: @test58( 927; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 %x, 3 928; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 1 929; CHECK-NEXT: ret i32 [[OR]] 930; 931 %shr = ashr i32 %x, 4 932 %shl = shl i32 %shr, 1 933 %or = or i32 %shl, 1 934 ret i32 %or 935} 936 937 938define i32 @test59(i32 %x) { 939; CHECK-LABEL: @test59( 940; CHECK-NEXT: [[SHR:%.*]] = ashr i32 %x, 4 941; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SHR]], 1 942; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 2 943; CHECK-NEXT: ret i32 [[OR]] 944; 945 %shr = ashr i32 %x, 4 946 %shl = shl i32 %shr, 1 947 %or = or i32 %shl, 2 948 ret i32 %or 949} 950 951; propagate "exact" trait 952define i32 @test60(i32 %x) { 953; CHECK-LABEL: @test60( 954; CHECK-NEXT: [[SHL:%.*]] = ashr exact i32 %x, 3 955; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 1 956; CHECK-NEXT: ret i32 [[OR]] 957; 958 %shr = ashr exact i32 %x, 4 959 %shl = shl i32 %shr, 1 960 %or = or i32 %shl, 1 961 ret i32 %or 962} 963 964; PR17026 965define void @test61(i128 %arg) { 966; CHECK-LABEL: @test61( 967; CHECK-NEXT: bb: 968; CHECK-NEXT: br i1 undef, label %bb1, label %bb12 969; CHECK: bb1: 970; CHECK-NEXT: br label %bb2 971; CHECK: bb2: 972; CHECK-NEXT: br i1 undef, label %bb3, label %bb7 973; CHECK: bb3: 974; CHECK-NEXT: br label %bb8 975; CHECK: bb7: 976; CHECK-NEXT: br i1 undef, label %bb8, label %bb2 977; CHECK: bb8: 978; CHECK-NEXT: br i1 undef, label %bb11, label %bb12 979; CHECK: bb11: 980; CHECK-NEXT: br i1 undef, label %bb1, label %bb12 981; CHECK: bb12: 982; CHECK-NEXT: ret void 983; 984bb: 985 br i1 undef, label %bb1, label %bb12 986 987bb1: ; preds = %bb11, %bb 988 br label %bb2 989 990bb2: ; preds = %bb7, %bb1 991 br i1 undef, label %bb3, label %bb7 992 993bb3: ; preds = %bb2 994 %tmp = lshr i128 %arg, 36893488147419103232 995 %tmp4 = shl i128 %tmp, 0 996 %tmp5 = or i128 %tmp4, undef 997 %tmp6 = trunc i128 %tmp5 to i16 998 br label %bb8 999 1000bb7: ; preds = %bb2 1001 br i1 undef, label %bb8, label %bb2 1002 1003bb8: ; preds = %bb7, %bb3 1004 %tmp9 = phi i16 [ %tmp6, %bb3 ], [ undef, %bb7 ] 1005 %tmp10 = icmp eq i16 %tmp9, 0 1006 br i1 %tmp10, label %bb11, label %bb12 1007 1008bb11: ; preds = %bb8 1009 br i1 undef, label %bb1, label %bb12 1010 1011bb12: ; preds = %bb11, %bb8, %bb 1012 ret void 1013} 1014 1015define i32 @test62(i32 %a) { 1016; CHECK-LABEL: @test62( 1017; CHECK-NEXT: ret i32 undef 1018; 1019 %b = ashr i32 %a, 32 ; shift all bits out 1020 ret i32 %b 1021} 1022 1023define <4 x i32> @test62_splat_vector(<4 x i32> %a) { 1024; CHECK-LABEL: @test62_splat_vector( 1025; CHECK-NEXT: ret <4 x i32> undef 1026; 1027 %b = ashr <4 x i32> %a, <i32 32, i32 32, i32 32, i32 32> ; shift all bits out 1028 ret <4 x i32> %b 1029} 1030 1031define <4 x i32> @test62_non_splat_vector(<4 x i32> %a) { 1032; CHECK-LABEL: @test62_non_splat_vector( 1033; CHECK-NEXT: [[B:%.*]] = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> 1034; CHECK-NEXT: ret <4 x i32> [[B]] 1035; 1036 %b = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> ; shift all bits out 1037 ret <4 x i32> %b 1038} 1039 1040define <2 x i65> @test_63(<2 x i64> %t) { 1041; CHECK-LABEL: @test_63( 1042; CHECK-NEXT: [[A:%.*]] = zext <2 x i64> %t to <2 x i65> 1043; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i65> [[A]], <i65 33, i65 33> 1044; CHECK-NEXT: [[B:%.*]] = ashr <2 x i65> [[SEXT]], <i65 33, i65 33> 1045; CHECK-NEXT: ret <2 x i65> [[B]] 1046; 1047 %a = zext <2 x i64> %t to <2 x i65> 1048 %sext = shl <2 x i65> %a, <i65 33, i65 33> 1049 %b = ashr <2 x i65> %sext, <i65 33, i65 33> 1050 ret <2 x i65> %b 1051} 1052 1053define i64 @test_64(i32 %t) { 1054; CHECK-LABEL: @test_64( 1055; CHECK-NEXT: [[SHL:%.*]] = shl i32 %t, 8 1056; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[SHL]] to i64 1057; CHECK-NEXT: ret i64 [[EXT]] 1058 1059 %and = and i32 %t, 16777215 1060 %ext = zext i32 %and to i64 1061 %shl = shl i64 %ext, 8 1062 ret i64 %shl 1063} 1064