1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -indvars -replexitval=always -S | FileCheck %s 3; Make sure IndVars preserves LCSSA form, especially across loop nests. 4 5target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" 6 7define void @PR18642(i32 %x) { 8; CHECK-LABEL: @PR18642( 9; CHECK-NEXT: entry: 10; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 11; CHECK: outer.header: 12; CHECK-NEXT: br label [[INNER_HEADER:%.*]] 13; CHECK: inner.header: 14; CHECK-NEXT: br i1 false, label [[INNER_LATCH:%.*]], label [[OUTER_LATCH:%.*]] 15; CHECK: inner.latch: 16; CHECK-NEXT: br i1 true, label [[INNER_HEADER]], label [[EXIT_LOOPEXIT:%.*]] 17; CHECK: outer.latch: 18; CHECK-NEXT: br i1 false, label [[OUTER_HEADER]], label [[EXIT_LOOPEXIT1:%.*]] 19; CHECK: exit.loopexit: 20; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ -2147483648, [[INNER_LATCH]] ] 21; CHECK-NEXT: br label [[EXIT:%.*]] 22; CHECK: exit.loopexit1: 23; CHECK-NEXT: br label [[EXIT]] 24; CHECK: exit: 25; CHECK-NEXT: [[EXIT_PHI:%.*]] = phi i32 [ [[INC_LCSSA]], [[EXIT_LOOPEXIT]] ], [ undef, [[EXIT_LOOPEXIT1]] ] 26; CHECK-NEXT: ret void 27; 28entry: 29 br label %outer.header 30 31outer.header: 32 %outer.iv = phi i32 [ 0, %entry ], [ %x, %outer.latch ] 33 br label %inner.header 34 35inner.header: 36 %inner.iv = phi i32 [ undef, %outer.header ], [ %inc, %inner.latch ] 37 %cmp1 = icmp slt i32 %inner.iv, %outer.iv 38 br i1 %cmp1, label %inner.latch, label %outer.latch 39 40inner.latch: 41 %inc = add nsw i32 %inner.iv, 1 42 %cmp2 = icmp slt i32 %inner.iv, %outer.iv 43 br i1 %cmp2, label %inner.header, label %exit 44 45outer.latch: 46 br i1 undef, label %outer.header, label %exit 47 48exit: 49 %exit.phi = phi i32 [ %inc, %inner.latch ], [ undef, %outer.latch ] 50 ret void 51} 52 53define i64 @unconditional_exit_simplification(i64 %arg) { 54; CHECK-LABEL: @unconditional_exit_simplification( 55; CHECK-NEXT: entry: 56; CHECK-NEXT: br label [[LOOP1:%.*]] 57; CHECK: loop1: 58; CHECK-NEXT: br label [[LOOP2:%.*]] 59; CHECK: loop2: 60; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[LOOP1]] ], [ 1, [[LOOP2]] ] 61; CHECK-NEXT: br i1 true, label [[LOOP2]], label [[LOOP1_LATCH:%.*]] 62; CHECK: loop1.latch: 63; CHECK-NEXT: [[RES_LCSSA:%.*]] = phi i64 [ [[IV2]], [[LOOP2]] ] 64; CHECK-NEXT: br i1 false, label [[LOOP1]], label [[EXIT:%.*]] 65; CHECK: exit: 66; CHECK-NEXT: [[RES_LCSSA2:%.*]] = phi i64 [ [[RES_LCSSA]], [[LOOP1_LATCH]] ] 67; CHECK-NEXT: ret i64 [[RES_LCSSA2]] 68; 69entry: 70 br label %loop1 71 72loop1: 73 %iv1 = phi i64 [ 0, %entry ], [ 1, %loop1.latch ] 74 br label %loop2 75 76loop2: 77 %iv2 = phi i64 [ 0, %loop1 ], [ 1, %loop2 ] 78 %res = add nuw nsw i64 %iv1, %iv2 79 br i1 true, label %loop2, label %loop1.latch 80 81loop1.latch: 82 %res.lcssa = phi i64 [ %res, %loop2 ] 83 br i1 false, label %loop1, label %exit 84 85exit: 86 %res.lcssa2 = phi i64 [ %res.lcssa, %loop1.latch ] 87 ret i64 %res.lcssa2 88} 89