1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -S -early-cse -earlycse-debug-hash | FileCheck %s 3; RUN: opt < %s -S -basic-aa -early-cse-memssa | FileCheck %s 4; RUN: opt < %s -S -passes=early-cse | FileCheck %s 5 6declare void @llvm.assume(i1) nounwind 7 8define void @test1(i8 %V, ptr%P) { 9; CHECK-LABEL: @test1( 10; CHECK-NEXT: store i32 23, ptr [[P:%.*]], align 4 11; CHECK-NEXT: [[C:%.*]] = zext i8 [[V:%.*]] to i32 12; CHECK-NEXT: store volatile i32 [[C]], ptr [[P]], align 4 13; CHECK-NEXT: store volatile i32 [[C]], ptr [[P]], align 4 14; CHECK-NEXT: [[E:%.*]] = add i32 [[C]], [[C]] 15; CHECK-NEXT: store volatile i32 [[E]], ptr [[P]], align 4 16; CHECK-NEXT: store volatile i32 [[E]], ptr [[P]], align 4 17; CHECK-NEXT: store volatile i32 [[E]], ptr [[P]], align 4 18; CHECK-NEXT: ret void 19; 20 %A = bitcast i64 42 to double ;; dead 21 %B = add i32 4, 19 ;; constant folds 22 store i32 %B, ptr %P 23 24 %C = zext i8 %V to i32 25 %D = zext i8 %V to i32 ;; CSE 26 store volatile i32 %C, ptr %P 27 store volatile i32 %D, ptr %P 28 29 %E = add i32 %C, %C 30 %F = add i32 %C, %C 31 store volatile i32 %E, ptr %P 32 store volatile i32 %F, ptr %P 33 34 %G = add nuw i32 %C, %C 35 store volatile i32 %G, ptr %P 36 ret void 37} 38 39 40;; Simple load value numbering. 41define i32 @test2(ptr%P) { 42; CHECK-LABEL: @test2( 43; CHECK-NEXT: [[V1:%.*]] = load i32, ptr [[P:%.*]], align 4 44; CHECK-NEXT: ret i32 0 45; 46 %V1 = load i32, ptr %P 47 %V2 = load i32, ptr %P 48 %Diff = sub i32 %V1, %V2 49 ret i32 %Diff 50} 51 52define i32 @test2a(ptr%P, i1 %b) { 53; CHECK-LABEL: @test2a( 54; CHECK-NEXT: [[V1:%.*]] = load i32, ptr [[P:%.*]], align 4 55; CHECK-NEXT: tail call void @llvm.assume(i1 [[B:%.*]]) 56; CHECK-NEXT: ret i32 0 57; 58 %V1 = load i32, ptr %P 59 tail call void @llvm.assume(i1 %b) 60 %V2 = load i32, ptr %P 61 %Diff = sub i32 %V1, %V2 62 ret i32 %Diff 63} 64 65;; Cross block load value numbering. 66define i32 @test3(ptr%P, i1 %Cond) { 67; CHECK-LABEL: @test3( 68; CHECK-NEXT: [[V1:%.*]] = load i32, ptr [[P:%.*]], align 4 69; CHECK-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]] 70; CHECK: T: 71; CHECK-NEXT: store i32 4, ptr [[P]], align 4 72; CHECK-NEXT: ret i32 42 73; CHECK: F: 74; CHECK-NEXT: ret i32 0 75; 76 %V1 = load i32, ptr %P 77 br i1 %Cond, label %T, label %F 78T: 79 store i32 4, ptr %P 80 ret i32 42 81F: 82 %V2 = load i32, ptr %P 83 %Diff = sub i32 %V1, %V2 84 ret i32 %Diff 85} 86 87define i32 @test3a(ptr%P, i1 %Cond, i1 %b) { 88; CHECK-LABEL: @test3a( 89; CHECK-NEXT: [[V1:%.*]] = load i32, ptr [[P:%.*]], align 4 90; CHECK-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]] 91; CHECK: T: 92; CHECK-NEXT: store i32 4, ptr [[P]], align 4 93; CHECK-NEXT: ret i32 42 94; CHECK: F: 95; CHECK-NEXT: tail call void @llvm.assume(i1 [[B:%.*]]) 96; CHECK-NEXT: ret i32 0 97; 98 %V1 = load i32, ptr %P 99 br i1 %Cond, label %T, label %F 100T: 101 store i32 4, ptr %P 102 ret i32 42 103F: 104 tail call void @llvm.assume(i1 %b) 105 %V2 = load i32, ptr %P 106 %Diff = sub i32 %V1, %V2 107 ret i32 %Diff 108} 109 110;; Cross block load value numbering stops when stores happen. 111define i32 @test4(ptr%P, i1 %Cond) { 112; CHECK-LABEL: @test4( 113; CHECK-NEXT: [[V1:%.*]] = load i32, ptr [[P:%.*]], align 4 114; CHECK-NEXT: br i1 [[COND:%.*]], label [[T:%.*]], label [[F:%.*]] 115; CHECK: T: 116; CHECK-NEXT: ret i32 42 117; CHECK: F: 118; CHECK-NEXT: store i32 42, ptr [[P]], align 4 119; CHECK-NEXT: [[DIFF:%.*]] = sub i32 [[V1]], 42 120; CHECK-NEXT: ret i32 [[DIFF]] 121; 122 %V1 = load i32, ptr %P 123 br i1 %Cond, label %T, label %F 124T: 125 ret i32 42 126F: 127 ; Clobbers V1 128 store i32 42, ptr %P 129 130 %V2 = load i32, ptr %P 131 %Diff = sub i32 %V1, %V2 132 ret i32 %Diff 133} 134 135declare i32 @func(ptr%P) readonly 136 137;; Simple call CSE'ing. 138define i32 @test5(ptr%P) { 139; CHECK-LABEL: @test5( 140; CHECK-NEXT: [[V1:%.*]] = call i32 @func(ptr [[P:%.*]]) 141; CHECK-NEXT: ret i32 0 142; 143 %V1 = call i32 @func(ptr %P) 144 %V2 = call i32 @func(ptr %P) 145 %Diff = sub i32 %V1, %V2 146 ret i32 %Diff 147} 148 149;; Trivial Store->load forwarding 150define i32 @test6(ptr%P) { 151; CHECK-LABEL: @test6( 152; CHECK-NEXT: store i32 42, ptr [[P:%.*]], align 4 153; CHECK-NEXT: ret i32 42 154; 155 store i32 42, ptr %P 156 %V1 = load i32, ptr %P 157 ret i32 %V1 158} 159 160define i32 @test6a(ptr%P, i1 %b) { 161; CHECK-LABEL: @test6a( 162; CHECK-NEXT: store i32 42, ptr [[P:%.*]], align 4 163; CHECK-NEXT: tail call void @llvm.assume(i1 [[B:%.*]]) 164; CHECK-NEXT: ret i32 42 165; 166 store i32 42, ptr %P 167 tail call void @llvm.assume(i1 %b) 168 %V1 = load i32, ptr %P 169 ret i32 %V1 170} 171 172;; Trivial dead store elimination. 173define void @test7(ptr%P) { 174; CHECK-LABEL: @test7( 175; CHECK-NEXT: store i32 45, ptr [[P:%.*]], align 4 176; CHECK-NEXT: ret void 177; 178 store i32 42, ptr %P 179 store i32 45, ptr %P 180 ret void 181} 182 183;; Readnone functions aren't invalidated by stores. 184define i32 @test8(ptr%P) { 185; CHECK-LABEL: @test8( 186; CHECK-NEXT: [[V1:%.*]] = call i32 @func(ptr [[P:%.*]]) #[[ATTR2:[0-9]+]] 187; CHECK-NEXT: store i32 4, ptr [[P]], align 4 188; CHECK-NEXT: ret i32 0 189; 190 %V1 = call i32 @func(ptr %P) readnone 191 store i32 4, ptr %P 192 %V2 = call i32 @func(ptr %P) readnone 193 %Diff = sub i32 %V1, %V2 194 ret i32 %Diff 195} 196 197;; Trivial DSE can't be performed across a readonly call. The call 198;; can observe the earlier write. 199define i32 @test9(ptr%P) { 200; CHECK-LABEL: @test9( 201; CHECK-NEXT: store i32 4, ptr [[P:%.*]], align 4 202; CHECK-NEXT: [[V1:%.*]] = call i32 @func(ptr [[P]]) #[[ATTR1:[0-9]+]] 203; CHECK-NEXT: store i32 5, ptr [[P]], align 4 204; CHECK-NEXT: ret i32 [[V1]] 205; 206 store i32 4, ptr %P 207 %V1 = call i32 @func(ptr %P) readonly 208 store i32 5, ptr %P 209 ret i32 %V1 210} 211 212;; Trivial DSE can be performed across a readnone call. 213define i32 @test10(ptr%P) { 214; CHECK-LABEL: @test10( 215; CHECK-NEXT: [[V1:%.*]] = call i32 @func(ptr [[P:%.*]]) #[[ATTR2]] 216; CHECK-NEXT: store i32 5, ptr [[P]], align 4 217; CHECK-NEXT: ret i32 [[V1]] 218; 219 store i32 4, ptr %P 220 %V1 = call i32 @func(ptr %P) readnone 221 store i32 5, ptr %P 222 ret i32 %V1 223} 224 225;; Trivial dead store elimination - should work for an entire series of dead stores too. 226define void @test11(ptr%P) { 227; CHECK-LABEL: @test11( 228; CHECK-NEXT: store i32 45, ptr [[P:%.*]], align 4 229; CHECK-NEXT: ret void 230; 231 store i32 42, ptr %P 232 store i32 43, ptr %P 233 store i32 44, ptr %P 234 store i32 45, ptr %P 235 ret void 236} 237 238define i32 @test12(i1 %B, ptr %P1, ptr %P2) { 239; CHECK-LABEL: @test12( 240; CHECK-NEXT: [[LOAD0:%.*]] = load i32, ptr [[P1:%.*]], align 4 241; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, ptr [[P2:%.*]] seq_cst, align 4 242; CHECK-NEXT: [[LOAD1:%.*]] = load i32, ptr [[P1]], align 4 243; CHECK-NEXT: [[SEL:%.*]] = select i1 [[B:%.*]], i32 [[LOAD0]], i32 [[LOAD1]] 244; CHECK-NEXT: ret i32 [[SEL]] 245; 246 %load0 = load i32, ptr %P1 247 %1 = load atomic i32, ptr %P2 seq_cst, align 4 248 %load1 = load i32, ptr %P1 249 %sel = select i1 %B, i32 %load0, i32 %load1 250 ret i32 %sel 251} 252 253define void @dse1(ptr%P) { 254; CHECK-LABEL: @dse1( 255; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[P:%.*]], align 4 256; CHECK-NEXT: ret void 257; 258 %v = load i32, ptr %P 259 store i32 %v, ptr %P 260 ret void 261} 262 263define void @dse2(ptr%P) { 264; CHECK-LABEL: @dse2( 265; CHECK-NEXT: [[V:%.*]] = load atomic i32, ptr [[P:%.*]] seq_cst, align 4 266; CHECK-NEXT: ret void 267; 268 %v = load atomic i32, ptr %P seq_cst, align 4 269 store i32 %v, ptr %P 270 ret void 271} 272 273define void @dse3(ptr%P) { 274; CHECK-LABEL: @dse3( 275; CHECK-NEXT: [[V:%.*]] = load atomic i32, ptr [[P:%.*]] seq_cst, align 4 276; CHECK-NEXT: ret void 277; 278 %v = load atomic i32, ptr %P seq_cst, align 4 279 store atomic i32 %v, ptr %P unordered, align 4 280 ret void 281} 282 283define i32 @dse4(ptr%P, ptr%Q) { 284; CHECK-LABEL: @dse4( 285; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[Q:%.*]], align 4 286; CHECK-NEXT: [[V:%.*]] = load atomic i32, ptr [[P:%.*]] unordered, align 4 287; CHECK-NEXT: ret i32 0 288; 289 %a = load i32, ptr %Q 290 %v = load atomic i32, ptr %P unordered, align 4 291 store atomic i32 %v, ptr %P unordered, align 4 292 %b = load i32, ptr %Q 293 %res = sub i32 %a, %b 294 ret i32 %res 295} 296 297; Note that in this example, %P and %Q could in fact be the same 298; pointer. %v could be different than the value observed for %a 299; and that's okay because we're using relaxed memory ordering. 300; The only guarantee we have to provide is that each of the loads 301; has to observe some value written to that location. We do 302; not have to respect the order in which those writes were done. 303define i32 @dse5(ptr%P, ptr%Q) { 304; CHECK-LABEL: @dse5( 305; CHECK-NEXT: [[V:%.*]] = load atomic i32, ptr [[P:%.*]] unordered, align 4 306; CHECK-NEXT: [[A:%.*]] = load atomic i32, ptr [[Q:%.*]] unordered, align 4 307; CHECK-NEXT: ret i32 0 308; 309 %v = load atomic i32, ptr %P unordered, align 4 310 %a = load atomic i32, ptr %Q unordered, align 4 311 store atomic i32 %v, ptr %P unordered, align 4 312 %b = load atomic i32, ptr %Q unordered, align 4 313 %res = sub i32 %a, %b 314 ret i32 %res 315} 316 317 318define void @dse_neg1(ptr%P) { 319; CHECK-LABEL: @dse_neg1( 320; CHECK-NEXT: store i32 5, ptr [[P:%.*]], align 4 321; CHECK-NEXT: ret void 322; 323 %v = load i32, ptr %P 324 store i32 5, ptr %P 325 ret void 326} 327 328; Could remove the store, but only if ordering was somehow 329; encoded. 330define void @dse_neg2(ptr%P) { 331; CHECK-LABEL: @dse_neg2( 332; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[P:%.*]], align 4 333; CHECK-NEXT: store atomic i32 [[V]], ptr [[P]] seq_cst, align 4 334; CHECK-NEXT: ret void 335; 336 %v = load i32, ptr %P 337 store atomic i32 %v, ptr %P seq_cst, align 4 338 ret void 339} 340 341@c = external global i32, align 4 342declare i32 @reads_c(i32 returned) 343define void @pr28763() { 344; CHECK-LABEL: @pr28763( 345; CHECK-NEXT: entry: 346; CHECK-NEXT: store i32 0, ptr @c, align 4 347; CHECK-NEXT: [[CALL:%.*]] = call i32 @reads_c(i32 0) 348; CHECK-NEXT: store i32 2, ptr @c, align 4 349; CHECK-NEXT: ret void 350; 351entry: 352 %load = load i32, ptr @c, align 4 353 store i32 0, ptr @c, align 4 354 %call = call i32 @reads_c(i32 0) 355 store i32 2, ptr @c, align 4 356 ret void 357} 358 359define i1 @cse_freeze(i1 %a) { 360; CHECK-LABEL: @cse_freeze( 361; CHECK-NEXT: entry: 362; CHECK-NEXT: [[B:%.*]] = freeze i1 [[A:%.*]] 363; CHECK-NEXT: ret i1 [[B]] 364; 365entry: 366 %b = freeze i1 %a 367 %c = freeze i1 %a 368 %and = and i1 %b, %c 369 ret i1 %and 370} 371