1// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
2
3s_delay_alu
4// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
5
6s_delay_alu instid9(VALU_DEP_1)
7// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid field name instid9
8
9s_delay_alu instid0(VALU_DEP_9)
10// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid value name VALU_DEP_9
11
12s_delay_alu instid0(1)
13// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: expected a value name
14
15s_delay_alu instid0(VALU_DEP_9|)
16// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: expected a right parenthesis
17
18s_delay_alu instid0(VALU_DEP_1) | (SALU_CYCLE_1)
19// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: expected a field name
20
21s_delay_alu instid0(VALU_DEP_1) | SALU_CYCLE_1)
22// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: expected a left parenthesis
23
24lds_direct_load v15 wait_vdst:16
25// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
26
27lds_direct_load v15 wait_vdst
28// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
29
30v_interp_p10_f32 v0, v1, v2, v3 wait_exp:8
31// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
32
33v_interp_p2_f32 v0, -v1, v2, v3 wait_exp
34// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
35
36global_atomic_cmpswap_x2 v[1:4], v3, v[5:8], off offset:2047 glc
37// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
38
39v_cubesc_f32_e64_dpp v5, v1, v2, 12345678 row_shr:4 row_mask:0xf bank_mask:0xf
40// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
41
42v_add3_u32_e64_dpp v5, v1, v2, 49812340 dpp8:[7,6,5,4,3,2,1,0]
43// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
44
45v_add3_u32_e64_dpp v5, v1, s1, v0 dpp8:[7,6,5,4,3,2,1,0]
46// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
47
48v_cvt_f32_i32_e64_dpp v5, s1 dpp8:[7,6,5,4,3,2,1,0]
49// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
50
51v_cvt_f32_i32_e64_dpp v5, s1 row_shl:15 row_mask:0xf bank_mask:0xf
52// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
53
54v_cvt_f16_u16_e64_dpp v5, s1 dpp8:[7,6,5,4,3,2,1,0]
55// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
56
57v_cvt_f16_u16_e64_dpp v5, s1 row_shl:1 row_mask:0xf bank_mask:0xf
58// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
59
60; disallow space between colons
61v_dual_mul_f32 v0, v0, v2 : : v_dual_mul_f32 v1, v1, v3
62// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
63
64// On GFX11, v_dot8_i32_i4 is a valid SP3 alias for v_dot8_i32_iu4.
65// However, we intentionally leave it unimplemented because on other
66// processors v_dot8_i32_i4 denotes an instruction of a different
67// behaviour, which is considered potentially dangerous.
68v_dot8_i32_i4 v0, v1, v2, v3
69// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
70
71// On GFX11, v_dot4_i32_i8 is a valid SP3 alias for v_dot4_i32_iu8.
72// However, we intentionally leave it unimplemented because on other
73// processors v_dot4_i32_i8 denotes an instruction of a different
74// behaviour, which is considered potentially dangerous.
75v_dot4_i32_i8 v0, v1, v2, v3
76// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
77
78v_dot4c_i32_i8 v0, v1, v2
79// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
80
81v_cmp_class_f16_e64_dpp s105, s2, v2 row_ror:15
82// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
83
84v_cmpx_class_f32_e64_dpp s1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
85// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
86