1; RUN: opt < %s -S -mcpu=z13 -msan-kernel=1 -float-abi=soft -passes=msan 2>&1 | FileCheck %s 2 3target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64" 4target triple = "s390x-unknown-linux-gnu" 5 6declare i64 @foo(i64 %guard, ...) #0 7 8attributes #0 = { "target-features"="+soft-float" "use-soft-float"="true" } 9 10declare i32 @random_i32() 11declare i64 @random_i64() 12declare float @random_float() 13declare double @random_double() 14 15define i64 @bar() #1 { 16 %arg2 = call i32 () @random_i32() 17 %arg3 = call float () @random_float() 18 %arg4 = call i32 () @random_i32() 19 %arg5 = call double () @random_double() 20 %arg6 = call i64 () @random_i64() 21 %arg9 = call i32 () @random_i32() 22 %arg11 = call float () @random_float() 23 %arg12 = call i32 () @random_i32() 24 %arg13 = call double () @random_double() 25 %arg14 = call i64 () @random_i64() 26 %1 = call i64 (i64, ...) @foo(i64 1, i32 zeroext %arg2, float %arg3, 27 i32 signext %arg4, double %arg5, i64 %arg6, 28 i64 7, double 8.0, i32 zeroext %arg9, 29 double 10.0, float %arg11, i32 signext %arg12, 30 double %arg13, i64 %arg14) 31 ret i64 %1 32} 33 34attributes #1 = { sanitize_memory } 35 36; In kernel the floating point values are passed in GPRs: 37; - r2@16 == i64 1 - skipped, because it's fixed 38; - r3@24 == i32 zext %arg2 - shadow is zero-extended 39; - r4@(32 + 4) == float %arg3 - right-justified, shadow is 32-bit 40; - r5@40 == i32 sext %arg4 - shadow is sign-extended 41; - r6@48 == double %arg5 - straightforward 42; - overflow@160 == i64 %arg6 - straightforward 43; - overflow@168 == 7 - filler 44; - overflow@176 == 8.0 - filler 45; - overflow@184 == i32 zext %arg9 - shadow is zero-extended 46; - overflow@192 == 10.0 - filler 47; - overflow@(200 + 4) == float %arg11 - right-justified, shadow is 32-bit 48; - overflow@208 == i32 sext %arg12 - shadow is sign-extended 49; - overflow@216 == double %arg13 - straightforward 50; - overflow@224 == i64 %arg14 - straightforward 51; Overflow arg area size is 72. 52 53; CHECK-LABEL: @bar 54 55; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 56; CHECK: [[S:%.*]] = add i64 [[B]], 24 57; CHECK: [[V:%.*]] = zext {{.*}} 58; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 59; CHECK: store {{.*}} [[V]], {{.*}} [[M]] 60 61; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 62; CHECK: [[S:%.*]] = add i64 [[B]], 36 63; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 64; CHECK: store {{.*}} [[M]] 65 66; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 67; CHECK: [[S:%.*]] = add i64 [[B]], 40 68; CHECK: [[V:%.*]] = sext {{.*}} 69; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 70; CHECK: store {{.*}} [[V]], {{.*}} [[M]] 71 72; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 73; CHECK: [[S:%.*]] = add i64 [[B]], 48 74; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 75; CHECK: store {{.*}} [[M]] 76 77; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 78; CHECK: [[S:%.*]] = add i64 [[B]], 160 79; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 80; CHECK: store {{.*}} [[M]] 81 82; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 83; CHECK: [[S:%.*]] = add i64 [[B]], 168 84; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 85; CHECK: store {{.*}} [[M]] 86 87; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 88; CHECK: [[S:%.*]] = add i64 [[B]], 176 89; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 90; CHECK: store {{.*}} [[M]] 91 92; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 93; CHECK: [[S:%.*]] = add i64 [[B]], 184 94; CHECK: [[V:%.*]] = zext {{.*}} 95; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 96; CHECK: store {{.*}} [[V]], {{.*}} [[M]] 97 98; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 99; CHECK: [[S:%.*]] = add i64 [[B]], 192 100; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 101; CHECK: store {{.*}} [[M]] 102 103; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 104; CHECK: [[S:%.*]] = add i64 [[B]], 204 105; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 106; CHECK: store {{.*}} [[M]] 107 108; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 109; CHECK: [[S:%.*]] = add i64 [[B]], 208 110; CHECK: [[V:%.*]] = sext {{.*}} 111; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 112; CHECK: store {{.*}} [[V]], {{.*}} [[M]] 113 114; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 115; CHECK: [[S:%.*]] = add i64 [[B]], 216 116; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 117; CHECK: store {{.*}} [[M]] 118 119; CHECK: [[B:%.*]] = ptrtoint ptr %va_arg_shadow to i64 120; CHECK: [[S:%.*]] = add i64 [[B]], 224 121; CHECK: [[M:%_msarg_va_s.*]] = inttoptr i64 [[S]] to ptr 122; CHECK: store {{.*}} [[M]] 123 124; CHECK: store {{.*}} 72, {{.*}} %va_arg_overflow_size 125