1; RUN: opt < %s -dfsan -S | FileCheck %s
2target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
3target triple = "x86_64-unknown-linux-gnu"
4
5; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]]
6; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]]
7
8define <4 x i4> @pass_vector(<4 x i4> %v) {
9  ; CHECK-LABEL: @pass_vector.dfsan
10  ; CHECK-NEXT: %[[#REG:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]]
11  ; CHECK-NEXT: store i[[#SBITS]] %[[#REG]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]]
12  ; CHECK-NEXT: ret <4 x i4> %v
13  ret <4 x i4> %v
14}
15
16define void @load_update_store_vector(<4 x i4>* %p) {
17  ; CHECK-LABEL: @load_update_store_vector.dfsan
18  ; CHECK: {{.*}} = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2
19
20  %v = load <4 x i4>, <4 x i4>* %p
21  %e2 = extractelement <4 x i4> %v, i32 2
22  %v1 = insertelement <4 x i4> %v, i4 %e2, i32 0
23  store <4 x i4> %v1, <4 x i4>* %p
24  ret void
25}
26
27define <4 x i1> @icmp_vector(<4 x i8> %a, <4 x i8> %b) {
28  ; CHECK-LABEL: @icmp_vector.dfsan
29  ; CHECK-NEXT: %[[B:.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN:2]]
30  ; CHECK-NEXT: %[[A:.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]]
31  ; CHECK:       %[[L:.*]] = or i[[#SBITS]] %[[A]], %[[B]]
32
33  ; CHECK: %r = icmp eq <4 x i8> %a, %b
34  ; CHECK: store i[[#SBITS]] %[[L]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]]
35  ; CHECK: ret <4 x i1> %r
36
37  %r = icmp eq <4 x i8> %a, %b
38  ret <4 x i1> %r
39}
40
41define <2 x i32> @const_vector() {
42  ; CHECK-LABEL: @const_vector.dfsan
43  ; CHECK-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2
44  ; CHECK-NEXT: ret <2 x i32> <i32 42, i32 11>
45
46  ret <2 x i32> < i32 42, i32 11 >
47}
48
49define <4 x i4> @call_vector(<4 x i4> %v) {
50  ; CHECK-LABEL: @call_vector.dfsan
51  ; CHECK-NEXT: %[[V:.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]]
52  ; CHECK-NEXT: store i[[#SBITS]] %[[V]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]]
53  ; CHECK-NEXT: %r = call <4 x i4> @pass_vector.dfsan(<4 x i4> %v)
54  ; CHECK-NEXT: %_dfsret = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]]
55  ; CHECK-NEXT: store i[[#SBITS]] %_dfsret, i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]]
56  ; CHECK-NEXT: ret <4 x i4> %r
57
58  %r = call <4 x i4> @pass_vector(<4 x i4> %v)
59  ret <4 x i4> %r
60}
61