1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=+avx | FileCheck %s
3
4define <2 x float> @cvt_v2i8_v2f32(<2 x i8> %src) {
5; CHECK-LABEL: cvt_v2i8_v2f32:
6; CHECK:       ## %bb.0:
7; CHECK-NEXT:    vpmovsxbd %xmm0, %xmm0
8; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
9; CHECK-NEXT:    retl
10  %res = sitofp <2 x i8> %src to <2 x float>
11  ret <2 x float> %res
12}
13
14define <2 x float> @cvt_v2i16_v2f32(<2 x i16> %src) {
15; CHECK-LABEL: cvt_v2i16_v2f32:
16; CHECK:       ## %bb.0:
17; CHECK-NEXT:    vpmovsxwd %xmm0, %xmm0
18; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
19; CHECK-NEXT:    retl
20  %res = sitofp <2 x i16> %src to <2 x float>
21  ret <2 x float> %res
22}
23
24define <2 x float> @cvt_v2i32_v2f32(<2 x i32> %src) {
25; CHECK-LABEL: cvt_v2i32_v2f32:
26; CHECK:       ## %bb.0:
27; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
28; CHECK-NEXT:    retl
29  %res = sitofp <2 x i32> %src to <2 x float>
30  ret <2 x float> %res
31}
32
33define <2 x float> @cvt_v2u8_v2f32(<2 x i8> %src) {
34; CHECK-LABEL: cvt_v2u8_v2f32:
35; CHECK:       ## %bb.0:
36; CHECK-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
37; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
38; CHECK-NEXT:    retl
39  %res = uitofp <2 x i8> %src to <2 x float>
40  ret <2 x float> %res
41}
42
43define <2 x float> @cvt_v2u16_v2f32(<2 x i16> %src) {
44; CHECK-LABEL: cvt_v2u16_v2f32:
45; CHECK:       ## %bb.0:
46; CHECK-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
47; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
48; CHECK-NEXT:    retl
49  %res = uitofp <2 x i16> %src to <2 x float>
50  ret <2 x float> %res
51}
52
53define <2 x float> @cvt_v2u32_v2f32(<2 x i32> %src) {
54; CHECK-LABEL: cvt_v2u32_v2f32:
55; CHECK:       ## %bb.0:
56; CHECK-NEXT:    vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
57; CHECK-NEXT:    vmovdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
58; CHECK-NEXT:    vpor %xmm1, %xmm0, %xmm0
59; CHECK-NEXT:    vsubpd %xmm1, %xmm0, %xmm0
60; CHECK-NEXT:    vcvtpd2ps %xmm0, %xmm0
61; CHECK-NEXT:    retl
62  %res = uitofp <2 x i32> %src to <2 x float>
63  ret <2 x float> %res
64}
65
66define <2 x i8> @cvt_v2f32_v2i8(<2 x float> %src) {
67; CHECK-LABEL: cvt_v2f32_v2i8:
68; CHECK:       ## %bb.0:
69; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
70; CHECK-NEXT:    vpackssdw %xmm0, %xmm0, %xmm0
71; CHECK-NEXT:    vpacksswb %xmm0, %xmm0, %xmm0
72; CHECK-NEXT:    retl
73  %res = fptosi <2 x float> %src to <2 x i8>
74  ret <2 x i8> %res
75}
76
77define <2 x i16> @cvt_v2f32_v2i16(<2 x float> %src) {
78; CHECK-LABEL: cvt_v2f32_v2i16:
79; CHECK:       ## %bb.0:
80; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
81; CHECK-NEXT:    vpackssdw %xmm0, %xmm0, %xmm0
82; CHECK-NEXT:    retl
83  %res = fptosi <2 x float> %src to <2 x i16>
84  ret <2 x i16> %res
85}
86
87define <2 x i32> @cvt_v2f32_v2i32(<2 x float> %src) {
88; CHECK-LABEL: cvt_v2f32_v2i32:
89; CHECK:       ## %bb.0:
90; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
91; CHECK-NEXT:    retl
92  %res = fptosi <2 x float> %src to <2 x i32>
93  ret <2 x i32> %res
94}
95
96define <2 x i8> @cvt_v2f32_v2u8(<2 x float> %src) {
97; CHECK-LABEL: cvt_v2f32_v2u8:
98; CHECK:       ## %bb.0:
99; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
100; CHECK-NEXT:    vpackusdw %xmm0, %xmm0, %xmm0
101; CHECK-NEXT:    vpackuswb %xmm0, %xmm0, %xmm0
102; CHECK-NEXT:    retl
103  %res = fptoui <2 x float> %src to <2 x i8>
104  ret <2 x i8> %res
105}
106
107define <2 x i16> @cvt_v2f32_v2u16(<2 x float> %src) {
108; CHECK-LABEL: cvt_v2f32_v2u16:
109; CHECK:       ## %bb.0:
110; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
111; CHECK-NEXT:    vpackusdw %xmm0, %xmm0, %xmm0
112; CHECK-NEXT:    retl
113  %res = fptoui <2 x float> %src to <2 x i16>
114  ret <2 x i16> %res
115}
116
117define <2 x i32> @cvt_v2f32_v2u32(<2 x float> %src) {
118; CHECK-LABEL: cvt_v2f32_v2u32:
119; CHECK:       ## %bb.0:
120; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm1
121; CHECK-NEXT:    vpsrad $31, %xmm1, %xmm2
122; CHECK-NEXT:    vsubps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
123; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
124; CHECK-NEXT:    vpand %xmm2, %xmm0, %xmm0
125; CHECK-NEXT:    vpor %xmm0, %xmm1, %xmm0
126; CHECK-NEXT:    retl
127  %res = fptoui <2 x float> %src to <2 x i32>
128  ret <2 x i32> %res
129}
130
131define <32 x i8> @PR40146(<4 x i64> %x) {
132; CHECK-LABEL: PR40146:
133; CHECK:       ## %bb.0:
134; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
135; CHECK-NEXT:    vpunpckhbw {{.*#+}} xmm1 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
136; CHECK-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
137; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
138; CHECK-NEXT:    retl
139  %perm = shufflevector <4 x i64> %x, <4 x i64> undef, <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>
140  %t1 = bitcast <4 x i64> %perm to <32 x i8>
141  %t2 = shufflevector <32 x i8> %t1, <32 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <32 x i32> <i32 0, i32 32, i32 1, i32 32, i32 2, i32 32, i32 3, i32 32, i32 4, i32 32, i32 5, i32 32, i32 6, i32 32, i32 7, i32 32, i32 16, i32 48, i32 17, i32 48, i32 18, i32 48, i32 19, i32 48, i32 20, i32 48, i32 21, i32 48, i32 22, i32 48, i32 23, i32 48>
142  ret <32 x i8> %t2
143}
144
145