1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s 3 4define i8 @shl_and(i8 %x, i8 %y) nounwind { 5; CHECK-LABEL: shl_and: 6; CHECK: # %bb.0: 7; CHECK-NEXT: # kill: def $esi killed $esi def $rsi 8; CHECK-NEXT: leal (,%rsi,4), %eax 9; CHECK-NEXT: shlb $5, %dil 10; CHECK-NEXT: andb %dil, %al 11; CHECK-NEXT: # kill: def $al killed $al killed $eax 12; CHECK-NEXT: retq 13 %sh0 = shl i8 %x, 3 14 %r = and i8 %sh0, %y 15 %sh1 = shl i8 %r, 2 16 ret i8 %sh1 17} 18 19define i16 @shl_or(i16 %x, i16 %y) nounwind { 20; CHECK-LABEL: shl_or: 21; CHECK: # %bb.0: 22; CHECK-NEXT: movl %edi, %eax 23; CHECK-NEXT: shll $7, %esi 24; CHECK-NEXT: shll $12, %eax 25; CHECK-NEXT: orl %esi, %eax 26; CHECK-NEXT: # kill: def $ax killed $ax killed $eax 27; CHECK-NEXT: retq 28 %sh0 = shl i16 %x, 5 29 %r = or i16 %y, %sh0 30 %sh1 = shl i16 %r, 7 31 ret i16 %sh1 32} 33 34define i32 @shl_xor(i32 %x, i32 %y) nounwind { 35; CHECK-LABEL: shl_xor: 36; CHECK: # %bb.0: 37; CHECK-NEXT: movl %edi, %eax 38; CHECK-NEXT: shll $7, %esi 39; CHECK-NEXT: shll $12, %eax 40; CHECK-NEXT: xorl %esi, %eax 41; CHECK-NEXT: retq 42 %sh0 = shl i32 %x, 5 43 %r = xor i32 %sh0, %y 44 %sh1 = shl i32 %r, 7 45 ret i32 %sh1 46} 47 48define i64 @lshr_and(i64 %x, i64 %y) nounwind { 49; CHECK-LABEL: lshr_and: 50; CHECK: # %bb.0: 51; CHECK-NEXT: movq %rdi, %rax 52; CHECK-NEXT: shrq $7, %rsi 53; CHECK-NEXT: shrq $12, %rax 54; CHECK-NEXT: andq %rsi, %rax 55; CHECK-NEXT: retq 56 %sh0 = lshr i64 %x, 5 57 %r = and i64 %y, %sh0 58 %sh1 = lshr i64 %r, 7 59 ret i64 %sh1 60} 61 62define <4 x i32> @lshr_or(<4 x i32> %x, <4 x i32> %y) nounwind { 63; CHECK-LABEL: lshr_or: 64; CHECK: # %bb.0: 65; CHECK-NEXT: psrld $7, %xmm1 66; CHECK-NEXT: psrld $12, %xmm0 67; CHECK-NEXT: por %xmm1, %xmm0 68; CHECK-NEXT: retq 69 %sh0 = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5> 70 %r = or <4 x i32> %sh0, %y 71 %sh1 = lshr <4 x i32> %r, <i32 7, i32 7, i32 7, i32 7> 72 ret <4 x i32> %sh1 73} 74 75define <8 x i16> @lshr_xor(<8 x i16> %x, <8 x i16> %y) nounwind { 76; CHECK-LABEL: lshr_xor: 77; CHECK: # %bb.0: 78; CHECK-NEXT: psrlw $7, %xmm1 79; CHECK-NEXT: psrlw $12, %xmm0 80; CHECK-NEXT: pxor %xmm1, %xmm0 81; CHECK-NEXT: retq 82 %sh0 = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> 83 %r = xor <8 x i16> %y, %sh0 84 %sh1 = lshr <8 x i16> %r, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> 85 ret <8 x i16> %sh1 86} 87 88 89define <16 x i8> @ashr_and(<16 x i8> %x, <16 x i8> %y) nounwind { 90; CHECK-LABEL: ashr_and: 91; CHECK: # %bb.0: 92; CHECK-NEXT: psrlw $2, %xmm1 93; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 94; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32] 95; CHECK-NEXT: pxor %xmm2, %xmm1 96; CHECK-NEXT: psubb %xmm2, %xmm1 97; CHECK-NEXT: psrlw $5, %xmm0 98; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 99; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4] 100; CHECK-NEXT: pxor %xmm2, %xmm0 101; CHECK-NEXT: psubb %xmm2, %xmm0 102; CHECK-NEXT: pand %xmm1, %xmm0 103; CHECK-NEXT: retq 104 %sh0 = ashr <16 x i8> %x, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> 105 %r = and <16 x i8> %y, %sh0 106 %sh1 = ashr <16 x i8> %r, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 107 ret <16 x i8> %sh1 108} 109 110define <2 x i64> @ashr_or(<2 x i64> %x, <2 x i64> %y) nounwind { 111; CHECK-LABEL: ashr_or: 112; CHECK: # %bb.0: 113; CHECK-NEXT: movdqa %xmm1, %xmm2 114; CHECK-NEXT: psrad $7, %xmm2 115; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] 116; CHECK-NEXT: psrlq $7, %xmm1 117; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] 118; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] 119; CHECK-NEXT: movdqa %xmm0, %xmm2 120; CHECK-NEXT: psrad $12, %xmm2 121; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] 122; CHECK-NEXT: psrlq $12, %xmm0 123; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] 124; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] 125; CHECK-NEXT: por %xmm1, %xmm0 126; CHECK-NEXT: retq 127 %sh0 = ashr <2 x i64> %x, <i64 5, i64 5> 128 %r = or <2 x i64> %sh0, %y 129 %sh1 = ashr <2 x i64> %r, <i64 7, i64 7> 130 ret <2 x i64> %sh1 131} 132 133define i32 @ashr_xor(i32 %x, i32 %y) nounwind { 134; CHECK-LABEL: ashr_xor: 135; CHECK: # %bb.0: 136; CHECK-NEXT: movl %edi, %eax 137; CHECK-NEXT: sarl $7, %esi 138; CHECK-NEXT: sarl $12, %eax 139; CHECK-NEXT: xorl %esi, %eax 140; CHECK-NEXT: retq 141 %sh0 = ashr i32 %x, 5 142 %r = xor i32 %y, %sh0 143 %sh1 = ashr i32 %r, 7 144 ret i32 %sh1 145} 146 147define i32 @shr_mismatch_xor(i32 %x, i32 %y) nounwind { 148; CHECK-LABEL: shr_mismatch_xor: 149; CHECK: # %bb.0: 150; CHECK-NEXT: movl %edi, %eax 151; CHECK-NEXT: sarl $5, %eax 152; CHECK-NEXT: xorl %esi, %eax 153; CHECK-NEXT: shrl $7, %eax 154; CHECK-NEXT: retq 155 %sh0 = ashr i32 %x, 5 156 %r = xor i32 %y, %sh0 157 %sh1 = lshr i32 %r, 7 158 ret i32 %sh1 159} 160 161define i32 @ashr_overshift_xor(i32 %x, i32 %y) nounwind { 162; CHECK-LABEL: ashr_overshift_xor: 163; CHECK: # %bb.0: 164; CHECK-NEXT: movl %edi, %eax 165; CHECK-NEXT: sarl $15, %eax 166; CHECK-NEXT: xorl %esi, %eax 167; CHECK-NEXT: sarl $17, %eax 168; CHECK-NEXT: retq 169 %sh0 = ashr i32 %x, 15 170 %r = xor i32 %y, %sh0 171 %sh1 = ashr i32 %r, 17 172 ret i32 %sh1 173} 174 175define i32 @lshr_or_extra_use(i32 %x, i32 %y, ptr %p) nounwind { 176; CHECK-LABEL: lshr_or_extra_use: 177; CHECK: # %bb.0: 178; CHECK-NEXT: movl %edi, %eax 179; CHECK-NEXT: shrl $5, %eax 180; CHECK-NEXT: orl %esi, %eax 181; CHECK-NEXT: movl %eax, (%rdx) 182; CHECK-NEXT: shrl $7, %eax 183; CHECK-NEXT: retq 184 %sh0 = lshr i32 %x, 5 185 %r = or i32 %sh0, %y 186 store i32 %r, ptr %p 187 %sh1 = lshr i32 %r, 7 188 ret i32 %sh1 189} 190