1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i686-linux | FileCheck %s -check-prefix=CHECK-32 3; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK-64 4 5define i1 @isnan_f(float %x) { 6; CHECK-32-LABEL: isnan_f: 7; CHECK-32: # %bb.0: # %entry 8; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 9; CHECK-32-NEXT: fucomp %st(0) 10; CHECK-32-NEXT: fnstsw %ax 11; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 12; CHECK-32-NEXT: sahf 13; CHECK-32-NEXT: setp %al 14; CHECK-32-NEXT: retl 15; 16; CHECK-64-LABEL: isnan_f: 17; CHECK-64: # %bb.0: # %entry 18; CHECK-64-NEXT: ucomiss %xmm0, %xmm0 19; CHECK-64-NEXT: setp %al 20; CHECK-64-NEXT: retq 21entry: 22 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; "nan" 23 ret i1 %0 24} 25 26define i1 @isnot_nan_f(float %x) { 27; CHECK-32-LABEL: isnot_nan_f: 28; CHECK-32: # %bb.0: # %entry 29; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 30; CHECK-32-NEXT: fucomp %st(0) 31; CHECK-32-NEXT: fnstsw %ax 32; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 33; CHECK-32-NEXT: sahf 34; CHECK-32-NEXT: setnp %al 35; CHECK-32-NEXT: retl 36; 37; CHECK-64-LABEL: isnot_nan_f: 38; CHECK-64: # %bb.0: # %entry 39; CHECK-64-NEXT: ucomiss %xmm0, %xmm0 40; CHECK-64-NEXT: setnp %al 41; CHECK-64-NEXT: retq 42entry: 43 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1020) ; 0x3fc = "zero|subnormal|normal|inf" 44 ret i1 %0 45} 46 47define i1 @issignaling_f(float %x) { 48; CHECK-32-LABEL: issignaling_f: 49; CHECK-32: # %bb.0: # %entry 50; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 51; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 52; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000 53; CHECK-32-NEXT: setl %cl 54; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001 55; CHECK-32-NEXT: setge %al 56; CHECK-32-NEXT: andb %cl, %al 57; CHECK-32-NEXT: retl 58; 59; CHECK-64-LABEL: issignaling_f: 60; CHECK-64: # %bb.0: # %entry 61; CHECK-64-NEXT: movd %xmm0, %eax 62; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 63; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000 64; CHECK-64-NEXT: setl %cl 65; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001 66; CHECK-64-NEXT: setge %al 67; CHECK-64-NEXT: andb %cl, %al 68; CHECK-64-NEXT: retq 69entry: 70 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1) ; "snan" 71 ret i1 %0 72} 73 74define i1 @isquiet_f(float %x) { 75; CHECK-32-LABEL: isquiet_f: 76; CHECK-32: # %bb.0: # %entry 77; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 78; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 79; CHECK-32-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000 80; CHECK-32-NEXT: setge %al 81; CHECK-32-NEXT: retl 82; 83; CHECK-64-LABEL: isquiet_f: 84; CHECK-64: # %bb.0: # %entry 85; CHECK-64-NEXT: movd %xmm0, %eax 86; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 87; CHECK-64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000 88; CHECK-64-NEXT: setge %al 89; CHECK-64-NEXT: retq 90entry: 91 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 2) ; "qnan" 92 ret i1 %0 93} 94 95define i1 @isinf_f(float %x) { 96; CHECK-32-LABEL: isinf_f: 97; CHECK-32: # %bb.0: # %entry 98; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 99; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 100; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 101; CHECK-32-NEXT: sete %al 102; CHECK-32-NEXT: retl 103; 104; CHECK-64-LABEL: isinf_f: 105; CHECK-64: # %bb.0: # %entry 106; CHECK-64-NEXT: movd %xmm0, %eax 107; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 108; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 109; CHECK-64-NEXT: sete %al 110; CHECK-64-NEXT: retq 111entry: 112 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf" 113 ret i1 %0 114} 115 116define i1 @is_plus_inf_f(float %x) { 117; CHECK-32-LABEL: is_plus_inf_f: 118; CHECK-32: # %bb.0: # %entry 119; CHECK-32-NEXT: cmpl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000 120; CHECK-32-NEXT: sete %al 121; CHECK-32-NEXT: retl 122; 123; CHECK-64-LABEL: is_plus_inf_f: 124; CHECK-64: # %bb.0: # %entry 125; CHECK-64-NEXT: movd %xmm0, %eax 126; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 127; CHECK-64-NEXT: sete %al 128; CHECK-64-NEXT: retq 129entry: 130 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; 0x200 = "+inf" 131 ret i1 %0 132} 133 134define i1 @is_minus_inf_f(float %x) { 135; CHECK-32-LABEL: is_minus_inf_f: 136; CHECK-32: # %bb.0: # %entry 137; CHECK-32-NEXT: cmpl $-8388608, {{[0-9]+}}(%esp) # imm = 0xFF800000 138; CHECK-32-NEXT: sete %al 139; CHECK-32-NEXT: retl 140; 141; CHECK-64-LABEL: is_minus_inf_f: 142; CHECK-64: # %bb.0: # %entry 143; CHECK-64-NEXT: movd %xmm0, %eax 144; CHECK-64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000 145; CHECK-64-NEXT: sete %al 146; CHECK-64-NEXT: retq 147entry: 148 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 4) ; "-inf" 149 ret i1 %0 150} 151 152define i1 @isfinite_f(float %x) { 153; CHECK-32-LABEL: isfinite_f: 154; CHECK-32: # %bb.0: # %entry 155; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 156; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 157; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 158; CHECK-32-NEXT: setl %al 159; CHECK-32-NEXT: retl 160; 161; CHECK-64-LABEL: isfinite_f: 162; CHECK-64: # %bb.0: # %entry 163; CHECK-64-NEXT: movd %xmm0, %eax 164; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 165; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 166; CHECK-64-NEXT: setl %al 167; CHECK-64-NEXT: retq 168entry: 169 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite" 170 ret i1 %0 171} 172 173define i1 @is_plus_finite_f(float %x) { 174; CHECK-32-LABEL: is_plus_finite_f: 175; CHECK-32: # %bb.0: # %entry 176; CHECK-32-NEXT: cmpl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000 177; CHECK-32-NEXT: setb %al 178; CHECK-32-NEXT: retl 179; 180; CHECK-64-LABEL: is_plus_finite_f: 181; CHECK-64: # %bb.0: # %entry 182; CHECK-64-NEXT: movd %xmm0, %eax 183; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 184; CHECK-64-NEXT: setb %al 185; CHECK-64-NEXT: retq 186entry: 187 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 448) ; 0x1c0 = "+finite" 188 ret i1 %0 189} 190 191define i1 @is_minus_finite_f(float %x) { 192; CHECK-32-LABEL: is_minus_finite_f: 193; CHECK-32: # %bb.0: # %entry 194; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax 195; CHECK-32-NEXT: testl %eax, %eax 196; CHECK-32-NEXT: sets %cl 197; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 198; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 199; CHECK-32-NEXT: setl %al 200; CHECK-32-NEXT: andb %cl, %al 201; CHECK-32-NEXT: retl 202; 203; CHECK-64-LABEL: is_minus_finite_f: 204; CHECK-64: # %bb.0: # %entry 205; CHECK-64-NEXT: movd %xmm0, %eax 206; CHECK-64-NEXT: testl %eax, %eax 207; CHECK-64-NEXT: sets %cl 208; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 209; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 210; CHECK-64-NEXT: setl %al 211; CHECK-64-NEXT: andb %cl, %al 212; CHECK-64-NEXT: retq 213entry: 214 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 56) ; 0x38 = "-finite" 215 ret i1 %0 216} 217 218define i1 @isnormal_f(float %x) { 219; CHECK-32-LABEL: isnormal_f: 220; CHECK-32: # %bb.0: # %entry 221; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 222; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 223; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000 224; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000 225; CHECK-32-NEXT: setb %al 226; CHECK-32-NEXT: retl 227; 228; CHECK-64-LABEL: isnormal_f: 229; CHECK-64: # %bb.0: # %entry 230; CHECK-64-NEXT: movd %xmm0, %eax 231; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 232; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000 233; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000 234; CHECK-64-NEXT: setb %al 235; CHECK-64-NEXT: retq 236entry: 237 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 264) ; 0x108 = "normal" 238 ret i1 %0 239} 240 241define i1 @is_plus_normal_f(float %x) { 242; CHECK-32-LABEL: is_plus_normal_f: 243; CHECK-32: # %bb.0: # %entry 244; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax 245; CHECK-32-NEXT: testl %eax, %eax 246; CHECK-32-NEXT: setns %cl 247; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 248; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000 249; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000 250; CHECK-32-NEXT: setb %al 251; CHECK-32-NEXT: andb %cl, %al 252; CHECK-32-NEXT: retl 253; 254; CHECK-64-LABEL: is_plus_normal_f: 255; CHECK-64: # %bb.0: # %entry 256; CHECK-64-NEXT: movd %xmm0, %eax 257; CHECK-64-NEXT: testl %eax, %eax 258; CHECK-64-NEXT: setns %cl 259; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 260; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000 261; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000 262; CHECK-64-NEXT: setb %al 263; CHECK-64-NEXT: andb %cl, %al 264; CHECK-64-NEXT: retq 265entry: 266 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 256) ; 0x100 = "+normal" 267 ret i1 %0 268} 269 270define i1 @issubnormal_f(float %x) { 271; CHECK-32-LABEL: issubnormal_f: 272; CHECK-32: # %bb.0: # %entry 273; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 274; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 275; CHECK-32-NEXT: decl %eax 276; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF 277; CHECK-32-NEXT: setb %al 278; CHECK-32-NEXT: retl 279; 280; CHECK-64-LABEL: issubnormal_f: 281; CHECK-64: # %bb.0: # %entry 282; CHECK-64-NEXT: movd %xmm0, %eax 283; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 284; CHECK-64-NEXT: decl %eax 285; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF 286; CHECK-64-NEXT: setb %al 287; CHECK-64-NEXT: retq 288entry: 289 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal" 290 ret i1 %0 291} 292 293define i1 @is_plus_subnormal_f(float %x) { 294; CHECK-32-LABEL: is_plus_subnormal_f: 295; CHECK-32: # %bb.0: # %entry 296; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax 297; CHECK-32-NEXT: decl %eax 298; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF 299; CHECK-32-NEXT: setb %al 300; CHECK-32-NEXT: retl 301; 302; CHECK-64-LABEL: is_plus_subnormal_f: 303; CHECK-64: # %bb.0: # %entry 304; CHECK-64-NEXT: movd %xmm0, %eax 305; CHECK-64-NEXT: decl %eax 306; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF 307; CHECK-64-NEXT: setb %al 308; CHECK-64-NEXT: retq 309entry: 310 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 128) ; 0x80 = "+subnormal" 311 ret i1 %0 312} 313 314define i1 @is_minus_subnormal_f(float %x) { 315; CHECK-32-LABEL: is_minus_subnormal_f: 316; CHECK-32: # %bb.0: # %entry 317; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax 318; CHECK-32-NEXT: testl %eax, %eax 319; CHECK-32-NEXT: sets %cl 320; CHECK-32-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 321; CHECK-32-NEXT: decl %eax 322; CHECK-32-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF 323; CHECK-32-NEXT: setb %al 324; CHECK-32-NEXT: andb %cl, %al 325; CHECK-32-NEXT: retl 326; 327; CHECK-64-LABEL: is_minus_subnormal_f: 328; CHECK-64: # %bb.0: # %entry 329; CHECK-64-NEXT: movd %xmm0, %eax 330; CHECK-64-NEXT: testl %eax, %eax 331; CHECK-64-NEXT: sets %cl 332; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 333; CHECK-64-NEXT: decl %eax 334; CHECK-64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF 335; CHECK-64-NEXT: setb %al 336; CHECK-64-NEXT: andb %cl, %al 337; CHECK-64-NEXT: retq 338entry: 339 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 16) ; 0x10 = "-subnormal" 340 ret i1 %0 341} 342 343define i1 @iszero_f(float %x) { 344; CHECK-32-LABEL: iszero_f: 345; CHECK-32: # %bb.0: # %entry 346; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 347; CHECK-32-NEXT: fldz 348; CHECK-32-NEXT: fucompp 349; CHECK-32-NEXT: fnstsw %ax 350; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 351; CHECK-32-NEXT: sahf 352; CHECK-32-NEXT: setnp %cl 353; CHECK-32-NEXT: sete %al 354; CHECK-32-NEXT: andb %cl, %al 355; CHECK-32-NEXT: retl 356; 357; CHECK-64-LABEL: iszero_f: 358; CHECK-64: # %bb.0: # %entry 359; CHECK-64-NEXT: xorps %xmm1, %xmm1 360; CHECK-64-NEXT: cmpeqss %xmm0, %xmm1 361; CHECK-64-NEXT: movd %xmm1, %eax 362; CHECK-64-NEXT: andl $1, %eax 363; CHECK-64-NEXT: # kill: def $al killed $al killed $eax 364; CHECK-64-NEXT: retq 365entry: 366 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero" 367 ret i1 %0 368} 369 370define i1 @is_plus_zero_f(float %x) { 371; CHECK-32-LABEL: is_plus_zero_f: 372; CHECK-32: # %bb.0: # %entry 373; CHECK-32-NEXT: cmpl $0, {{[0-9]+}}(%esp) 374; CHECK-32-NEXT: sete %al 375; CHECK-32-NEXT: retl 376; 377; CHECK-64-LABEL: is_plus_zero_f: 378; CHECK-64: # %bb.0: # %entry 379; CHECK-64-NEXT: movd %xmm0, %eax 380; CHECK-64-NEXT: testl %eax, %eax 381; CHECK-64-NEXT: sete %al 382; CHECK-64-NEXT: retq 383entry: 384 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 64) ; 0x40 = "+zero" 385 ret i1 %0 386} 387 388define i1 @is_minus_zero_f(float %x) { 389; CHECK-32-LABEL: is_minus_zero_f: 390; CHECK-32: # %bb.0: # %entry 391; CHECK-32-NEXT: cmpl $-2147483648, {{[0-9]+}}(%esp) # imm = 0x80000000 392; CHECK-32-NEXT: sete %al 393; CHECK-32-NEXT: retl 394; 395; CHECK-64-LABEL: is_minus_zero_f: 396; CHECK-64: # %bb.0: # %entry 397; CHECK-64-NEXT: movd %xmm0, %eax 398; CHECK-64-NEXT: cmpl $-2147483648, %eax # imm = 0x80000000 399; CHECK-64-NEXT: sete %al 400; CHECK-64-NEXT: retq 401entry: 402 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 32) ; 0x20 = "-zero" 403 ret i1 %0 404} 405 406 407 408define i1 @isnan_f_strictfp(float %x) strictfp { 409; CHECK-32-LABEL: isnan_f_strictfp: 410; CHECK-32: # %bb.0: # %entry 411; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 412; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 413; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001 414; CHECK-32-NEXT: setge %al 415; CHECK-32-NEXT: retl 416; 417; CHECK-64-LABEL: isnan_f_strictfp: 418; CHECK-64: # %bb.0: # %entry 419; CHECK-64-NEXT: movd %xmm0, %eax 420; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 421; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001 422; CHECK-64-NEXT: setge %al 423; CHECK-64-NEXT: retq 424entry: 425 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; "nan" 426 ret i1 %0 427} 428 429define i1 @isfinite_f_strictfp(float %x) strictfp { 430; CHECK-32-LABEL: isfinite_f_strictfp: 431; CHECK-32: # %bb.0: # %entry 432; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 433; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 434; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 435; CHECK-32-NEXT: setl %al 436; CHECK-32-NEXT: retl 437; 438; CHECK-64-LABEL: isfinite_f_strictfp: 439; CHECK-64: # %bb.0: # %entry 440; CHECK-64-NEXT: movd %xmm0, %eax 441; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 442; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 443; CHECK-64-NEXT: setl %al 444; CHECK-64-NEXT: retq 445entry: 446 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite" 447 ret i1 %0 448} 449 450define i1 @iszero_f_strictfp(float %x) strictfp { 451; CHECK-32-LABEL: iszero_f_strictfp: 452; CHECK-32: # %bb.0: # %entry 453; CHECK-32-NEXT: testl $2147483647, {{[0-9]+}}(%esp) # imm = 0x7FFFFFFF 454; CHECK-32-NEXT: sete %al 455; CHECK-32-NEXT: retl 456; 457; CHECK-64-LABEL: iszero_f_strictfp: 458; CHECK-64: # %bb.0: # %entry 459; CHECK-64-NEXT: movd %xmm0, %eax 460; CHECK-64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF 461; CHECK-64-NEXT: sete %al 462; CHECK-64-NEXT: retq 463entry: 464 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero" 465 ret i1 %0 466} 467 468 469define i1 @isnan_d(double %x) { 470; CHECK-32-LABEL: isnan_d: 471; CHECK-32: # %bb.0: # %entry 472; CHECK-32-NEXT: fldl {{[0-9]+}}(%esp) 473; CHECK-32-NEXT: fucomp %st(0) 474; CHECK-32-NEXT: fnstsw %ax 475; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 476; CHECK-32-NEXT: sahf 477; CHECK-32-NEXT: setp %al 478; CHECK-32-NEXT: retl 479; 480; CHECK-64-LABEL: isnan_d: 481; CHECK-64: # %bb.0: # %entry 482; CHECK-64-NEXT: ucomisd %xmm0, %xmm0 483; CHECK-64-NEXT: setp %al 484; CHECK-64-NEXT: retq 485entry: 486 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; "nan" 487 ret i1 %0 488} 489 490define i1 @isinf_d(double %x) { 491; CHECK-32-LABEL: isinf_d: 492; CHECK-32: # %bb.0: # %entry 493; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 494; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 495; CHECK-32-NEXT: xorl $2146435072, %eax # imm = 0x7FF00000 496; CHECK-32-NEXT: orl {{[0-9]+}}(%esp), %eax 497; CHECK-32-NEXT: sete %al 498; CHECK-32-NEXT: retl 499; 500; CHECK-64-LABEL: isinf_d: 501; CHECK-64: # %bb.0: # %entry 502; CHECK-64-NEXT: movq %xmm0, %rax 503; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF 504; CHECK-64-NEXT: andq %rax, %rcx 505; CHECK-64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000 506; CHECK-64-NEXT: cmpq %rax, %rcx 507; CHECK-64-NEXT: sete %al 508; CHECK-64-NEXT: retq 509entry: 510 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 516) ; 0x204 = "inf" 511 ret i1 %0 512} 513 514define i1 @isfinite_d(double %x) { 515; CHECK-32-LABEL: isfinite_d: 516; CHECK-32: # %bb.0: # %entry 517; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 518; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 519; CHECK-32-NEXT: cmpl $2146435072, %eax # imm = 0x7FF00000 520; CHECK-32-NEXT: setl %al 521; CHECK-32-NEXT: retl 522; 523; CHECK-64-LABEL: isfinite_d: 524; CHECK-64: # %bb.0: # %entry 525; CHECK-64-NEXT: movq %xmm0, %rax 526; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF 527; CHECK-64-NEXT: andq %rax, %rcx 528; CHECK-64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000 529; CHECK-64-NEXT: cmpq %rax, %rcx 530; CHECK-64-NEXT: setl %al 531; CHECK-64-NEXT: retq 532entry: 533 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 504) ; 0x1f8 = "finite" 534 ret i1 %0 535} 536 537define i1 @isnormal_d(double %x) { 538; CHECK-32-LABEL: isnormal_d: 539; CHECK-32: # %bb.0: # %entry 540; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 541; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 542; CHECK-32-NEXT: addl $-1048576, %eax # imm = 0xFFF00000 543; CHECK-32-NEXT: shrl $21, %eax 544; CHECK-32-NEXT: cmpl $1023, %eax # imm = 0x3FF 545; CHECK-32-NEXT: setb %al 546; CHECK-32-NEXT: retl 547; 548; CHECK-64-LABEL: isnormal_d: 549; CHECK-64: # %bb.0: # %entry 550; CHECK-64-NEXT: movq %xmm0, %rax 551; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF 552; CHECK-64-NEXT: andq %rax, %rcx 553; CHECK-64-NEXT: movabsq $-4503599627370496, %rax # imm = 0xFFF0000000000000 554; CHECK-64-NEXT: addq %rcx, %rax 555; CHECK-64-NEXT: shrq $53, %rax 556; CHECK-64-NEXT: cmpl $1023, %eax # imm = 0x3FF 557; CHECK-64-NEXT: setb %al 558; CHECK-64-NEXT: retq 559entry: 560 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 264) ; 0x108 = "normal" 561 ret i1 %0 562} 563 564define i1 @issubnormal_d(double %x) { 565; CHECK-32-LABEL: issubnormal_d: 566; CHECK-32: # %bb.0: # %entry 567; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax 568; CHECK-32-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF 569; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %ecx 570; CHECK-32-NEXT: addl $-1, %eax 571; CHECK-32-NEXT: adcl $-1, %ecx 572; CHECK-32-NEXT: cmpl $-1, %eax 573; CHECK-32-NEXT: sbbl $1048575, %ecx # imm = 0xFFFFF 574; CHECK-32-NEXT: setb %al 575; CHECK-32-NEXT: retl 576; 577; CHECK-64-LABEL: issubnormal_d: 578; CHECK-64: # %bb.0: # %entry 579; CHECK-64-NEXT: movq %xmm0, %rax 580; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF 581; CHECK-64-NEXT: andq %rax, %rcx 582; CHECK-64-NEXT: decq %rcx 583; CHECK-64-NEXT: movabsq $4503599627370495, %rax # imm = 0xFFFFFFFFFFFFF 584; CHECK-64-NEXT: cmpq %rax, %rcx 585; CHECK-64-NEXT: setb %al 586; CHECK-64-NEXT: retq 587entry: 588 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 144) ; 0x90 = "subnormal" 589 ret i1 %0 590} 591 592define i1 @iszero_d(double %x) { 593; CHECK-32-LABEL: iszero_d: 594; CHECK-32: # %bb.0: # %entry 595; CHECK-32-NEXT: fldl {{[0-9]+}}(%esp) 596; CHECK-32-NEXT: fldz 597; CHECK-32-NEXT: fucompp 598; CHECK-32-NEXT: fnstsw %ax 599; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 600; CHECK-32-NEXT: sahf 601; CHECK-32-NEXT: setnp %cl 602; CHECK-32-NEXT: sete %al 603; CHECK-32-NEXT: andb %cl, %al 604; CHECK-32-NEXT: retl 605; 606; CHECK-64-LABEL: iszero_d: 607; CHECK-64: # %bb.0: # %entry 608; CHECK-64-NEXT: xorpd %xmm1, %xmm1 609; CHECK-64-NEXT: cmpeqsd %xmm0, %xmm1 610; CHECK-64-NEXT: movq %xmm1, %rax 611; CHECK-64-NEXT: andl $1, %eax 612; CHECK-64-NEXT: # kill: def $al killed $al killed $rax 613; CHECK-64-NEXT: retq 614entry: 615 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 96) ; 0x60 = "zero" 616 ret i1 %0 617} 618 619define i1 @issignaling_d(double %x) { 620; CHECK-32-LABEL: issignaling_d: 621; CHECK-32: # %bb.0: # %entry 622; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 623; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 624; CHECK-32-NEXT: xorl %ecx, %ecx 625; CHECK-32-NEXT: cmpl {{[0-9]+}}(%esp), %ecx 626; CHECK-32-NEXT: movl $2146435072, %ecx # imm = 0x7FF00000 627; CHECK-32-NEXT: sbbl %eax, %ecx 628; CHECK-32-NEXT: setl %cl 629; CHECK-32-NEXT: cmpl $2146959360, %eax # imm = 0x7FF80000 630; CHECK-32-NEXT: setl %al 631; CHECK-32-NEXT: andb %cl, %al 632; CHECK-32-NEXT: retl 633; 634; CHECK-64-LABEL: issignaling_d: 635; CHECK-64: # %bb.0: # %entry 636; CHECK-64-NEXT: movq %xmm0, %rax 637; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF 638; CHECK-64-NEXT: andq %rax, %rcx 639; CHECK-64-NEXT: movabsq $9221120237041090560, %rax # imm = 0x7FF8000000000000 640; CHECK-64-NEXT: cmpq %rax, %rcx 641; CHECK-64-NEXT: setl %dl 642; CHECK-64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000 643; CHECK-64-NEXT: cmpq %rax, %rcx 644; CHECK-64-NEXT: setg %al 645; CHECK-64-NEXT: andb %dl, %al 646; CHECK-64-NEXT: retq 647entry: 648 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1) ; "snan" 649 ret i1 %0 650} 651 652define i1 @isquiet_d(double %x) { 653; CHECK-32-LABEL: isquiet_d: 654; CHECK-32: # %bb.0: # %entry 655; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 656; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 657; CHECK-32-NEXT: cmpl $2146959360, %eax # imm = 0x7FF80000 658; CHECK-32-NEXT: setge %al 659; CHECK-32-NEXT: retl 660; 661; CHECK-64-LABEL: isquiet_d: 662; CHECK-64: # %bb.0: # %entry 663; CHECK-64-NEXT: movq %xmm0, %rax 664; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF 665; CHECK-64-NEXT: andq %rax, %rcx 666; CHECK-64-NEXT: movabsq $9221120237041090559, %rax # imm = 0x7FF7FFFFFFFFFFFF 667; CHECK-64-NEXT: cmpq %rax, %rcx 668; CHECK-64-NEXT: setg %al 669; CHECK-64-NEXT: retq 670entry: 671 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 2) ; "qnan" 672 ret i1 %0 673} 674 675define i1 @isnan_d_strictfp(double %x) strictfp { 676; CHECK-32-LABEL: isnan_d_strictfp: 677; CHECK-32: # %bb.0: # %entry 678; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 679; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 680; CHECK-32-NEXT: xorl %ecx, %ecx 681; CHECK-32-NEXT: cmpl {{[0-9]+}}(%esp), %ecx 682; CHECK-32-NEXT: movl $2146435072, %ecx # imm = 0x7FF00000 683; CHECK-32-NEXT: sbbl %eax, %ecx 684; CHECK-32-NEXT: setl %al 685; CHECK-32-NEXT: retl 686; 687; CHECK-64-LABEL: isnan_d_strictfp: 688; CHECK-64: # %bb.0: # %entry 689; CHECK-64-NEXT: movq %xmm0, %rax 690; CHECK-64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF 691; CHECK-64-NEXT: andq %rax, %rcx 692; CHECK-64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000 693; CHECK-64-NEXT: cmpq %rax, %rcx 694; CHECK-64-NEXT: setg %al 695; CHECK-64-NEXT: retq 696entry: 697 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; "nan" 698 ret i1 %0 699} 700 701define i1 @iszero_d_strictfp(double %x) strictfp { 702; CHECK-32-LABEL: iszero_d_strictfp: 703; CHECK-32: # %bb.0: # %entry 704; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 705; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 706; CHECK-32-NEXT: orl {{[0-9]+}}(%esp), %eax 707; CHECK-32-NEXT: sete %al 708; CHECK-32-NEXT: retl 709; 710; CHECK-64-LABEL: iszero_d_strictfp: 711; CHECK-64: # %bb.0: # %entry 712; CHECK-64-NEXT: movq %xmm0, %rax 713; CHECK-64-NEXT: shlq $1, %rax 714; CHECK-64-NEXT: testq %rax, %rax 715; CHECK-64-NEXT: sete %al 716; CHECK-64-NEXT: retq 717entry: 718 %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 96) ; 0x60 = "zero" 719 ret i1 %0 720} 721 722 723 724define <1 x i1> @isnan_v1f(<1 x float> %x) { 725; CHECK-32-LABEL: isnan_v1f: 726; CHECK-32: # %bb.0: # %entry 727; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 728; CHECK-32-NEXT: fucomp %st(0) 729; CHECK-32-NEXT: fnstsw %ax 730; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 731; CHECK-32-NEXT: sahf 732; CHECK-32-NEXT: setp %al 733; CHECK-32-NEXT: retl 734; 735; CHECK-64-LABEL: isnan_v1f: 736; CHECK-64: # %bb.0: # %entry 737; CHECK-64-NEXT: ucomiss %xmm0, %xmm0 738; CHECK-64-NEXT: setp %al 739; CHECK-64-NEXT: retq 740entry: 741 %0 = tail call <1 x i1> @llvm.is.fpclass.v1f32(<1 x float> %x, i32 3) ; "nan" 742 ret <1 x i1> %0 743} 744 745define <1 x i1> @isnan_v1f_strictfp(<1 x float> %x) strictfp { 746; CHECK-32-LABEL: isnan_v1f_strictfp: 747; CHECK-32: # %bb.0: # %entry 748; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 749; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax 750; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001 751; CHECK-32-NEXT: setge %al 752; CHECK-32-NEXT: retl 753; 754; CHECK-64-LABEL: isnan_v1f_strictfp: 755; CHECK-64: # %bb.0: # %entry 756; CHECK-64-NEXT: movd %xmm0, %eax 757; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF 758; CHECK-64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001 759; CHECK-64-NEXT: setge %al 760; CHECK-64-NEXT: retq 761entry: 762 %0 = tail call <1 x i1> @llvm.is.fpclass.v1f32(<1 x float> %x, i32 3) ; "nan" 763 ret <1 x i1> %0 764} 765 766define <2 x i1> @isnan_v2f(<2 x float> %x) { 767; CHECK-32-LABEL: isnan_v2f: 768; CHECK-32: # %bb.0: # %entry 769; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 770; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 771; CHECK-32-NEXT: fucomp %st(0) 772; CHECK-32-NEXT: fnstsw %ax 773; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 774; CHECK-32-NEXT: sahf 775; CHECK-32-NEXT: setp %cl 776; CHECK-32-NEXT: fucomp %st(0) 777; CHECK-32-NEXT: fnstsw %ax 778; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 779; CHECK-32-NEXT: sahf 780; CHECK-32-NEXT: setp %dl 781; CHECK-32-NEXT: movl %ecx, %eax 782; CHECK-32-NEXT: retl 783; 784; CHECK-64-LABEL: isnan_v2f: 785; CHECK-64: # %bb.0: # %entry 786; CHECK-64-NEXT: cmpunordps %xmm0, %xmm0 787; CHECK-64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3] 788; CHECK-64-NEXT: retq 789entry: 790 %0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 3) ; "nan" 791 ret <2 x i1> %0 792} 793 794 795define <2 x i1> @isnot_nan_v2f(<2 x float> %x) { 796; CHECK-32-LABEL: isnot_nan_v2f: 797; CHECK-32: # %bb.0: # %entry 798; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 799; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 800; CHECK-32-NEXT: fucomp %st(0) 801; CHECK-32-NEXT: fnstsw %ax 802; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 803; CHECK-32-NEXT: sahf 804; CHECK-32-NEXT: setnp %cl 805; CHECK-32-NEXT: fucomp %st(0) 806; CHECK-32-NEXT: fnstsw %ax 807; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 808; CHECK-32-NEXT: sahf 809; CHECK-32-NEXT: setnp %dl 810; CHECK-32-NEXT: movl %ecx, %eax 811; CHECK-32-NEXT: retl 812; 813; CHECK-64-LABEL: isnot_nan_v2f: 814; CHECK-64: # %bb.0: # %entry 815; CHECK-64-NEXT: cmpordps %xmm0, %xmm0 816; CHECK-64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3] 817; CHECK-64-NEXT: retq 818entry: 819 %0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 1020) ; 0x3fc = "zero|subnormal|normal|inf" 820 ret <2 x i1> %0 821} 822 823define <2 x i1> @isnan_v2f_strictfp(<2 x float> %x) strictfp { 824; CHECK-32-LABEL: isnan_v2f_strictfp: 825; CHECK-32: # %bb.0: # %entry 826; CHECK-32-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF 827; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax 828; CHECK-32-NEXT: andl %ecx, %eax 829; CHECK-32-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001 830; CHECK-32-NEXT: setge %al 831; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %ecx 832; CHECK-32-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001 833; CHECK-32-NEXT: setge %dl 834; CHECK-32-NEXT: retl 835; 836; CHECK-64-LABEL: isnan_v2f_strictfp: 837; CHECK-64: # %bb.0: # %entry 838; CHECK-64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3] 839; CHECK-64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 840; CHECK-64-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 841; CHECK-64-NEXT: retq 842entry: 843 %0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 3) ; "nan" 844 ret <2 x i1> %0 845} 846 847define <4 x i1> @isnan_v4f(<4 x float> %x) { 848; CHECK-32-LABEL: isnan_v4f: 849; CHECK-32: # %bb.0: # %entry 850; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %ecx 851; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 852; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 853; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 854; CHECK-32-NEXT: flds {{[0-9]+}}(%esp) 855; CHECK-32-NEXT: fucomp %st(0) 856; CHECK-32-NEXT: fnstsw %ax 857; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 858; CHECK-32-NEXT: sahf 859; CHECK-32-NEXT: setp %dh 860; CHECK-32-NEXT: fucomp %st(0) 861; CHECK-32-NEXT: fnstsw %ax 862; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 863; CHECK-32-NEXT: sahf 864; CHECK-32-NEXT: setp %dl 865; CHECK-32-NEXT: addb %dl, %dl 866; CHECK-32-NEXT: orb %dh, %dl 867; CHECK-32-NEXT: fucomp %st(0) 868; CHECK-32-NEXT: fnstsw %ax 869; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 870; CHECK-32-NEXT: sahf 871; CHECK-32-NEXT: setp %dh 872; CHECK-32-NEXT: fucomp %st(0) 873; CHECK-32-NEXT: fnstsw %ax 874; CHECK-32-NEXT: # kill: def $ah killed $ah killed $ax 875; CHECK-32-NEXT: sahf 876; CHECK-32-NEXT: setp %al 877; CHECK-32-NEXT: addb %al, %al 878; CHECK-32-NEXT: orb %dh, %al 879; CHECK-32-NEXT: shlb $2, %al 880; CHECK-32-NEXT: orb %dl, %al 881; CHECK-32-NEXT: movb %al, (%ecx) 882; CHECK-32-NEXT: movl %ecx, %eax 883; CHECK-32-NEXT: retl $4 884; 885; CHECK-64-LABEL: isnan_v4f: 886; CHECK-64: # %bb.0: # %entry 887; CHECK-64-NEXT: cmpunordps %xmm0, %xmm0 888; CHECK-64-NEXT: retq 889entry: 890 %0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 3) ; "nan" 891 ret <4 x i1> %0 892} 893 894define <4 x i1> @isnan_v4f_strictfp(<4 x float> %x) strictfp { 895; CHECK-32-LABEL: isnan_v4f_strictfp: 896; CHECK-32: # %bb.0: # %entry 897; CHECK-32-NEXT: pushl %esi 898; CHECK-32-NEXT: .cfi_def_cfa_offset 8 899; CHECK-32-NEXT: .cfi_offset %esi, -8 900; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %eax 901; CHECK-32-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF 902; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %edx 903; CHECK-32-NEXT: andl %ecx, %edx 904; CHECK-32-NEXT: cmpl $2139095041, %edx # imm = 0x7F800001 905; CHECK-32-NEXT: setge %dh 906; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %esi 907; CHECK-32-NEXT: andl %ecx, %esi 908; CHECK-32-NEXT: cmpl $2139095041, %esi # imm = 0x7F800001 909; CHECK-32-NEXT: setge %dl 910; CHECK-32-NEXT: addb %dl, %dl 911; CHECK-32-NEXT: orb %dh, %dl 912; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %esi 913; CHECK-32-NEXT: andl %ecx, %esi 914; CHECK-32-NEXT: cmpl $2139095041, %esi # imm = 0x7F800001 915; CHECK-32-NEXT: setge %dh 916; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %ecx 917; CHECK-32-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001 918; CHECK-32-NEXT: setge %cl 919; CHECK-32-NEXT: addb %cl, %cl 920; CHECK-32-NEXT: orb %dh, %cl 921; CHECK-32-NEXT: shlb $2, %cl 922; CHECK-32-NEXT: orb %dl, %cl 923; CHECK-32-NEXT: movb %cl, (%eax) 924; CHECK-32-NEXT: popl %esi 925; CHECK-32-NEXT: .cfi_def_cfa_offset 4 926; CHECK-32-NEXT: retl $4 927; 928; CHECK-64-LABEL: isnan_v4f_strictfp: 929; CHECK-64: # %bb.0: # %entry 930; CHECK-64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 931; CHECK-64-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 932; CHECK-64-NEXT: retq 933entry: 934 %0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 3) ; "nan" 935 ret <4 x i1> %0 936} 937 938define i1 @isnone_f(float %x) { 939; CHECK-32-LABEL: isnone_f: 940; CHECK-32: # %bb.0: # %entry 941; CHECK-32-NEXT: xorl %eax, %eax 942; CHECK-32-NEXT: retl 943; 944; CHECK-64-LABEL: isnone_f: 945; CHECK-64: # %bb.0: # %entry 946; CHECK-64-NEXT: xorl %eax, %eax 947; CHECK-64-NEXT: retq 948entry: 949 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 0) 950 ret i1 %0 951} 952 953define i1 @isany_f(float %x) { 954; CHECK-32-LABEL: isany_f: 955; CHECK-32: # %bb.0: # %entry 956; CHECK-32-NEXT: movb $1, %al 957; CHECK-32-NEXT: retl 958; 959; CHECK-64-LABEL: isany_f: 960; CHECK-64: # %bb.0: # %entry 961; CHECK-64-NEXT: movb $1, %al 962; CHECK-64-NEXT: retq 963entry: 964 %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1023) 965 ret i1 %0 966} 967 968 969 970declare i1 @llvm.is.fpclass.f32(float, i32) 971declare i1 @llvm.is.fpclass.f64(double, i32) 972declare <1 x i1> @llvm.is.fpclass.v1f32(<1 x float>, i32) 973declare <2 x i1> @llvm.is.fpclass.v2f32(<2 x float>, i32) 974declare <4 x i1> @llvm.is.fpclass.v4f32(<4 x float>, i32) 975