1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE
3; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx  | FileCheck %s --check-prefix=AVX
4
5;
6; SSE
7;
8
9define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
10; SSE-LABEL: test_x86_sse_comieq_ss:
11; SSE:       # %bb.0:
12; SSE-NEXT:    movl %edi, %eax
13; SSE-NEXT:    comiss %xmm1, %xmm0
14; SSE-NEXT:    setnp %cl
15; SSE-NEXT:    sete %dl
16; SSE-NEXT:    testb %cl, %dl
17; SSE-NEXT:    cmovnel %esi, %eax
18; SSE-NEXT:    retq
19;
20; AVX-LABEL: test_x86_sse_comieq_ss:
21; AVX:       # %bb.0:
22; AVX-NEXT:    movl %edi, %eax
23; AVX-NEXT:    vcomiss %xmm1, %xmm0
24; AVX-NEXT:    setnp %cl
25; AVX-NEXT:    sete %dl
26; AVX-NEXT:    testb %cl, %dl
27; AVX-NEXT:    cmovnel %esi, %eax
28; AVX-NEXT:    retq
29  %call = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1)
30  %cmp = icmp eq i32 %call, 0
31  %res = select i1 %cmp, i32 %a2, i32 %a3
32  ret i32 %res
33}
34declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone
35
36define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
37; SSE-LABEL: test_x86_sse_comige_ss:
38; SSE:       # %bb.0:
39; SSE-NEXT:    movl %edi, %eax
40; SSE-NEXT:    comiss %xmm1, %xmm0
41; SSE-NEXT:    cmovbl %esi, %eax
42; SSE-NEXT:    retq
43;
44; AVX-LABEL: test_x86_sse_comige_ss:
45; AVX:       # %bb.0:
46; AVX-NEXT:    movl %edi, %eax
47; AVX-NEXT:    vcomiss %xmm1, %xmm0
48; AVX-NEXT:    cmovbl %esi, %eax
49; AVX-NEXT:    retq
50  %call = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1)
51  %cmp = icmp ne i32 %call, 0
52  %res = select i1 %cmp, i32 %a2, i32 %a3
53  ret i32 %res
54}
55declare i32 @llvm.x86.sse.comige.ss(<4 x float>, <4 x float>) nounwind readnone
56
57define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
58; SSE-LABEL: test_x86_sse_comigt_ss:
59; SSE:       # %bb.0:
60; SSE-NEXT:    movl %edi, %eax
61; SSE-NEXT:    comiss %xmm1, %xmm0
62; SSE-NEXT:    cmoval %esi, %eax
63; SSE-NEXT:    retq
64;
65; AVX-LABEL: test_x86_sse_comigt_ss:
66; AVX:       # %bb.0:
67; AVX-NEXT:    movl %edi, %eax
68; AVX-NEXT:    vcomiss %xmm1, %xmm0
69; AVX-NEXT:    cmoval %esi, %eax
70; AVX-NEXT:    retq
71  %call = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1)
72  %cmp = icmp eq i32 %call, 0
73  %res = select i1 %cmp, i32 %a2, i32 %a3
74  ret i32 %res
75}
76declare i32 @llvm.x86.sse.comigt.ss(<4 x float>, <4 x float>) nounwind readnone
77
78define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
79; SSE-LABEL: test_x86_sse_comile_ss:
80; SSE:       # %bb.0:
81; SSE-NEXT:    movl %edi, %eax
82; SSE-NEXT:    comiss %xmm0, %xmm1
83; SSE-NEXT:    cmovbl %esi, %eax
84; SSE-NEXT:    retq
85;
86; AVX-LABEL: test_x86_sse_comile_ss:
87; AVX:       # %bb.0:
88; AVX-NEXT:    movl %edi, %eax
89; AVX-NEXT:    vcomiss %xmm0, %xmm1
90; AVX-NEXT:    cmovbl %esi, %eax
91; AVX-NEXT:    retq
92  %call = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1)
93  %cmp = icmp ne i32 %call, 0
94  %res = select i1 %cmp, i32 %a2, i32 %a3
95  ret i32 %res
96}
97declare i32 @llvm.x86.sse.comile.ss(<4 x float>, <4 x float>) nounwind readnone
98
99define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
100; SSE-LABEL: test_x86_sse_comilt_ss:
101; SSE:       # %bb.0:
102; SSE-NEXT:    movl %edi, %eax
103; SSE-NEXT:    comiss %xmm0, %xmm1
104; SSE-NEXT:    cmoval %esi, %eax
105; SSE-NEXT:    retq
106;
107; AVX-LABEL: test_x86_sse_comilt_ss:
108; AVX:       # %bb.0:
109; AVX-NEXT:    movl %edi, %eax
110; AVX-NEXT:    vcomiss %xmm0, %xmm1
111; AVX-NEXT:    cmoval %esi, %eax
112; AVX-NEXT:    retq
113  %call = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1)
114  %cmp = icmp eq i32 %call, 0
115  %res = select i1 %cmp, i32 %a2, i32 %a3
116  ret i32 %res
117}
118declare i32 @llvm.x86.sse.comilt.ss(<4 x float>, <4 x float>) nounwind readnone
119
120define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
121; SSE-LABEL: test_x86_sse_comineq_ss:
122; SSE:       # %bb.0:
123; SSE-NEXT:    movl %esi, %eax
124; SSE-NEXT:    comiss %xmm1, %xmm0
125; SSE-NEXT:    cmovnel %edi, %eax
126; SSE-NEXT:    cmovpl %edi, %eax
127; SSE-NEXT:    retq
128;
129; AVX-LABEL: test_x86_sse_comineq_ss:
130; AVX:       # %bb.0:
131; AVX-NEXT:    movl %esi, %eax
132; AVX-NEXT:    vcomiss %xmm1, %xmm0
133; AVX-NEXT:    cmovnel %edi, %eax
134; AVX-NEXT:    cmovpl %edi, %eax
135; AVX-NEXT:    retq
136  %call = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1)
137  %cmp = icmp ne i32 %call, 0
138  %res = select i1 %cmp, i32 %a2, i32 %a3
139  ret i32 %res
140}
141declare i32 @llvm.x86.sse.comineq.ss(<4 x float>, <4 x float>) nounwind readnone
142
143define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
144; SSE-LABEL: test_x86_sse_ucomieq_ss:
145; SSE:       # %bb.0:
146; SSE-NEXT:    movl %edi, %eax
147; SSE-NEXT:    ucomiss %xmm1, %xmm0
148; SSE-NEXT:    setnp %cl
149; SSE-NEXT:    sete %dl
150; SSE-NEXT:    testb %cl, %dl
151; SSE-NEXT:    cmovnel %esi, %eax
152; SSE-NEXT:    retq
153;
154; AVX-LABEL: test_x86_sse_ucomieq_ss:
155; AVX:       # %bb.0:
156; AVX-NEXT:    movl %edi, %eax
157; AVX-NEXT:    vucomiss %xmm1, %xmm0
158; AVX-NEXT:    setnp %cl
159; AVX-NEXT:    sete %dl
160; AVX-NEXT:    testb %cl, %dl
161; AVX-NEXT:    cmovnel %esi, %eax
162; AVX-NEXT:    retq
163  %call = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1)
164  %cmp = icmp eq i32 %call, 0
165  %res = select i1 %cmp, i32 %a2, i32 %a3
166  ret i32 %res
167}
168declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone
169
170define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
171; SSE-LABEL: test_x86_sse_ucomige_ss:
172; SSE:       # %bb.0:
173; SSE-NEXT:    movl %edi, %eax
174; SSE-NEXT:    ucomiss %xmm1, %xmm0
175; SSE-NEXT:    cmovbl %esi, %eax
176; SSE-NEXT:    retq
177;
178; AVX-LABEL: test_x86_sse_ucomige_ss:
179; AVX:       # %bb.0:
180; AVX-NEXT:    movl %edi, %eax
181; AVX-NEXT:    vucomiss %xmm1, %xmm0
182; AVX-NEXT:    cmovbl %esi, %eax
183; AVX-NEXT:    retq
184  %call = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1)
185  %cmp = icmp ne i32 %call, 0
186  %res = select i1 %cmp, i32 %a2, i32 %a3
187  ret i32 %res
188}
189declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone
190
191define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
192; SSE-LABEL: test_x86_sse_ucomigt_ss:
193; SSE:       # %bb.0:
194; SSE-NEXT:    movl %edi, %eax
195; SSE-NEXT:    ucomiss %xmm1, %xmm0
196; SSE-NEXT:    cmoval %esi, %eax
197; SSE-NEXT:    retq
198;
199; AVX-LABEL: test_x86_sse_ucomigt_ss:
200; AVX:       # %bb.0:
201; AVX-NEXT:    movl %edi, %eax
202; AVX-NEXT:    vucomiss %xmm1, %xmm0
203; AVX-NEXT:    cmoval %esi, %eax
204; AVX-NEXT:    retq
205  %call = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1)
206  %cmp = icmp eq i32 %call, 0
207  %res = select i1 %cmp, i32 %a2, i32 %a3
208  ret i32 %res
209}
210declare i32 @llvm.x86.sse.ucomigt.ss(<4 x float>, <4 x float>) nounwind readnone
211
212define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
213; SSE-LABEL: test_x86_sse_ucomile_ss:
214; SSE:       # %bb.0:
215; SSE-NEXT:    movl %edi, %eax
216; SSE-NEXT:    ucomiss %xmm0, %xmm1
217; SSE-NEXT:    cmovbl %esi, %eax
218; SSE-NEXT:    retq
219;
220; AVX-LABEL: test_x86_sse_ucomile_ss:
221; AVX:       # %bb.0:
222; AVX-NEXT:    movl %edi, %eax
223; AVX-NEXT:    vucomiss %xmm0, %xmm1
224; AVX-NEXT:    cmovbl %esi, %eax
225; AVX-NEXT:    retq
226  %call = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1)
227  %cmp = icmp ne i32 %call, 0
228  %res = select i1 %cmp, i32 %a2, i32 %a3
229  ret i32 %res
230}
231declare i32 @llvm.x86.sse.ucomile.ss(<4 x float>, <4 x float>) nounwind readnone
232
233define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
234; SSE-LABEL: test_x86_sse_ucomilt_ss:
235; SSE:       # %bb.0:
236; SSE-NEXT:    movl %edi, %eax
237; SSE-NEXT:    ucomiss %xmm0, %xmm1
238; SSE-NEXT:    cmoval %esi, %eax
239; SSE-NEXT:    retq
240;
241; AVX-LABEL: test_x86_sse_ucomilt_ss:
242; AVX:       # %bb.0:
243; AVX-NEXT:    movl %edi, %eax
244; AVX-NEXT:    vucomiss %xmm0, %xmm1
245; AVX-NEXT:    cmoval %esi, %eax
246; AVX-NEXT:    retq
247  %call = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1)
248  %cmp = icmp eq i32 %call, 0
249  %res = select i1 %cmp, i32 %a2, i32 %a3
250  ret i32 %res
251}
252declare i32 @llvm.x86.sse.ucomilt.ss(<4 x float>, <4 x float>) nounwind readnone
253
254define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1, i32 %a2, i32 %a3) {
255; SSE-LABEL: test_x86_sse_ucomineq_ss:
256; SSE:       # %bb.0:
257; SSE-NEXT:    movl %esi, %eax
258; SSE-NEXT:    ucomiss %xmm1, %xmm0
259; SSE-NEXT:    cmovnel %edi, %eax
260; SSE-NEXT:    cmovpl %edi, %eax
261; SSE-NEXT:    retq
262;
263; AVX-LABEL: test_x86_sse_ucomineq_ss:
264; AVX:       # %bb.0:
265; AVX-NEXT:    movl %esi, %eax
266; AVX-NEXT:    vucomiss %xmm1, %xmm0
267; AVX-NEXT:    cmovnel %edi, %eax
268; AVX-NEXT:    cmovpl %edi, %eax
269; AVX-NEXT:    retq
270  %call = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1)
271  %cmp = icmp ne i32 %call, 0
272  %res = select i1 %cmp, i32 %a2, i32 %a3
273  ret i32 %res
274}
275declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>) nounwind readnone
276
277;
278; SSE2
279;
280
281define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
282; SSE-LABEL: test_x86_sse2_comieq_sd:
283; SSE:       # %bb.0:
284; SSE-NEXT:    movl %edi, %eax
285; SSE-NEXT:    comisd %xmm1, %xmm0
286; SSE-NEXT:    setnp %cl
287; SSE-NEXT:    sete %dl
288; SSE-NEXT:    testb %cl, %dl
289; SSE-NEXT:    cmovnel %esi, %eax
290; SSE-NEXT:    retq
291;
292; AVX-LABEL: test_x86_sse2_comieq_sd:
293; AVX:       # %bb.0:
294; AVX-NEXT:    movl %edi, %eax
295; AVX-NEXT:    vcomisd %xmm1, %xmm0
296; AVX-NEXT:    setnp %cl
297; AVX-NEXT:    sete %dl
298; AVX-NEXT:    testb %cl, %dl
299; AVX-NEXT:    cmovnel %esi, %eax
300; AVX-NEXT:    retq
301  %call = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
302  %cmp = icmp eq i32 %call, 0
303  %res = select i1 %cmp, i32 %a2, i32 %a3
304  ret i32 %res
305}
306declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone
307
308define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
309; SSE-LABEL: test_x86_sse2_comige_sd:
310; SSE:       # %bb.0:
311; SSE-NEXT:    movl %edi, %eax
312; SSE-NEXT:    comisd %xmm1, %xmm0
313; SSE-NEXT:    cmovbl %esi, %eax
314; SSE-NEXT:    retq
315;
316; AVX-LABEL: test_x86_sse2_comige_sd:
317; AVX:       # %bb.0:
318; AVX-NEXT:    movl %edi, %eax
319; AVX-NEXT:    vcomisd %xmm1, %xmm0
320; AVX-NEXT:    cmovbl %esi, %eax
321; AVX-NEXT:    retq
322  %call = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
323  %cmp = icmp ne i32 %call, 0
324  %res = select i1 %cmp, i32 %a2, i32 %a3
325  ret i32 %res
326}
327declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>) nounwind readnone
328
329define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
330; SSE-LABEL: test_x86_sse2_comigt_sd:
331; SSE:       # %bb.0:
332; SSE-NEXT:    movl %edi, %eax
333; SSE-NEXT:    comisd %xmm1, %xmm0
334; SSE-NEXT:    cmoval %esi, %eax
335; SSE-NEXT:    retq
336;
337; AVX-LABEL: test_x86_sse2_comigt_sd:
338; AVX:       # %bb.0:
339; AVX-NEXT:    movl %edi, %eax
340; AVX-NEXT:    vcomisd %xmm1, %xmm0
341; AVX-NEXT:    cmoval %esi, %eax
342; AVX-NEXT:    retq
343  %call = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
344  %cmp = icmp eq i32 %call, 0
345  %res = select i1 %cmp, i32 %a2, i32 %a3
346  ret i32 %res
347}
348declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>) nounwind readnone
349
350define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
351; SSE-LABEL: test_x86_sse2_comile_sd:
352; SSE:       # %bb.0:
353; SSE-NEXT:    movl %edi, %eax
354; SSE-NEXT:    comisd %xmm0, %xmm1
355; SSE-NEXT:    cmovbl %esi, %eax
356; SSE-NEXT:    retq
357;
358; AVX-LABEL: test_x86_sse2_comile_sd:
359; AVX:       # %bb.0:
360; AVX-NEXT:    movl %edi, %eax
361; AVX-NEXT:    vcomisd %xmm0, %xmm1
362; AVX-NEXT:    cmovbl %esi, %eax
363; AVX-NEXT:    retq
364  %call = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
365  %cmp = icmp ne i32 %call, 0
366  %res = select i1 %cmp, i32 %a2, i32 %a3
367  ret i32 %res
368}
369declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>) nounwind readnone
370
371define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
372; SSE-LABEL: test_x86_sse2_comilt_sd:
373; SSE:       # %bb.0:
374; SSE-NEXT:    movl %edi, %eax
375; SSE-NEXT:    comisd %xmm0, %xmm1
376; SSE-NEXT:    cmoval %esi, %eax
377; SSE-NEXT:    retq
378;
379; AVX-LABEL: test_x86_sse2_comilt_sd:
380; AVX:       # %bb.0:
381; AVX-NEXT:    movl %edi, %eax
382; AVX-NEXT:    vcomisd %xmm0, %xmm1
383; AVX-NEXT:    cmoval %esi, %eax
384; AVX-NEXT:    retq
385  %call = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
386  %cmp = icmp eq i32 %call, 0
387  %res = select i1 %cmp, i32 %a2, i32 %a3
388  ret i32 %res
389}
390declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>) nounwind readnone
391
392define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
393; SSE-LABEL: test_x86_sse2_comineq_sd:
394; SSE:       # %bb.0:
395; SSE-NEXT:    movl %esi, %eax
396; SSE-NEXT:    comisd %xmm1, %xmm0
397; SSE-NEXT:    cmovnel %edi, %eax
398; SSE-NEXT:    cmovpl %edi, %eax
399; SSE-NEXT:    retq
400;
401; AVX-LABEL: test_x86_sse2_comineq_sd:
402; AVX:       # %bb.0:
403; AVX-NEXT:    movl %esi, %eax
404; AVX-NEXT:    vcomisd %xmm1, %xmm0
405; AVX-NEXT:    cmovnel %edi, %eax
406; AVX-NEXT:    cmovpl %edi, %eax
407; AVX-NEXT:    retq
408  %call = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
409  %cmp = icmp ne i32 %call, 0
410  %res = select i1 %cmp, i32 %a2, i32 %a3
411  ret i32 %res
412}
413declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>) nounwind readnone
414
415define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
416; SSE-LABEL: test_x86_sse2_ucomieq_sd:
417; SSE:       # %bb.0:
418; SSE-NEXT:    movl %edi, %eax
419; SSE-NEXT:    ucomisd %xmm1, %xmm0
420; SSE-NEXT:    setnp %cl
421; SSE-NEXT:    sete %dl
422; SSE-NEXT:    testb %cl, %dl
423; SSE-NEXT:    cmovnel %esi, %eax
424; SSE-NEXT:    retq
425;
426; AVX-LABEL: test_x86_sse2_ucomieq_sd:
427; AVX:       # %bb.0:
428; AVX-NEXT:    movl %edi, %eax
429; AVX-NEXT:    vucomisd %xmm1, %xmm0
430; AVX-NEXT:    setnp %cl
431; AVX-NEXT:    sete %dl
432; AVX-NEXT:    testb %cl, %dl
433; AVX-NEXT:    cmovnel %esi, %eax
434; AVX-NEXT:    retq
435  %call = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
436  %cmp = icmp eq i32 %call, 0
437  %res = select i1 %cmp, i32 %a2, i32 %a3
438  ret i32 %res
439}
440declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readnone
441
442define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
443; SSE-LABEL: test_x86_sse2_ucomige_sd:
444; SSE:       # %bb.0:
445; SSE-NEXT:    movl %edi, %eax
446; SSE-NEXT:    ucomisd %xmm1, %xmm0
447; SSE-NEXT:    cmovbl %esi, %eax
448; SSE-NEXT:    retq
449;
450; AVX-LABEL: test_x86_sse2_ucomige_sd:
451; AVX:       # %bb.0:
452; AVX-NEXT:    movl %edi, %eax
453; AVX-NEXT:    vucomisd %xmm1, %xmm0
454; AVX-NEXT:    cmovbl %esi, %eax
455; AVX-NEXT:    retq
456  %call = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
457  %cmp = icmp ne i32 %call, 0
458  %res = select i1 %cmp, i32 %a2, i32 %a3
459  ret i32 %res
460}
461declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>) nounwind readnone
462
463define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
464; SSE-LABEL: test_x86_sse2_ucomigt_sd:
465; SSE:       # %bb.0:
466; SSE-NEXT:    movl %edi, %eax
467; SSE-NEXT:    ucomisd %xmm1, %xmm0
468; SSE-NEXT:    cmoval %esi, %eax
469; SSE-NEXT:    retq
470;
471; AVX-LABEL: test_x86_sse2_ucomigt_sd:
472; AVX:       # %bb.0:
473; AVX-NEXT:    movl %edi, %eax
474; AVX-NEXT:    vucomisd %xmm1, %xmm0
475; AVX-NEXT:    cmoval %esi, %eax
476; AVX-NEXT:    retq
477  %call = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
478  %cmp = icmp eq i32 %call, 0
479  %res = select i1 %cmp, i32 %a2, i32 %a3
480  ret i32 %res
481}
482declare i32 @llvm.x86.sse2.ucomigt.sd(<2 x double>, <2 x double>) nounwind readnone
483
484define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
485; SSE-LABEL: test_x86_sse2_ucomile_sd:
486; SSE:       # %bb.0:
487; SSE-NEXT:    movl %edi, %eax
488; SSE-NEXT:    ucomisd %xmm0, %xmm1
489; SSE-NEXT:    cmovbl %esi, %eax
490; SSE-NEXT:    retq
491;
492; AVX-LABEL: test_x86_sse2_ucomile_sd:
493; AVX:       # %bb.0:
494; AVX-NEXT:    movl %edi, %eax
495; AVX-NEXT:    vucomisd %xmm0, %xmm1
496; AVX-NEXT:    cmovbl %esi, %eax
497; AVX-NEXT:    retq
498  %call = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
499  %cmp = icmp ne i32 %call, 0
500  %res = select i1 %cmp, i32 %a2, i32 %a3
501  ret i32 %res
502}
503declare i32 @llvm.x86.sse2.ucomile.sd(<2 x double>, <2 x double>) nounwind readnone
504
505define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
506; SSE-LABEL: test_x86_sse2_ucomilt_sd:
507; SSE:       # %bb.0:
508; SSE-NEXT:    movl %edi, %eax
509; SSE-NEXT:    ucomisd %xmm0, %xmm1
510; SSE-NEXT:    cmoval %esi, %eax
511; SSE-NEXT:    retq
512;
513; AVX-LABEL: test_x86_sse2_ucomilt_sd:
514; AVX:       # %bb.0:
515; AVX-NEXT:    movl %edi, %eax
516; AVX-NEXT:    vucomisd %xmm0, %xmm1
517; AVX-NEXT:    cmoval %esi, %eax
518; AVX-NEXT:    retq
519  %call = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
520  %cmp = icmp eq i32 %call, 0
521  %res = select i1 %cmp, i32 %a2, i32 %a3
522  ret i32 %res
523}
524declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>) nounwind readnone
525
526define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1, i32 %a2, i32 %a3) {
527; SSE-LABEL: test_x86_sse2_ucomineq_sd:
528; SSE:       # %bb.0:
529; SSE-NEXT:    movl %esi, %eax
530; SSE-NEXT:    ucomisd %xmm1, %xmm0
531; SSE-NEXT:    cmovnel %edi, %eax
532; SSE-NEXT:    cmovpl %edi, %eax
533; SSE-NEXT:    retq
534;
535; AVX-LABEL: test_x86_sse2_ucomineq_sd:
536; AVX:       # %bb.0:
537; AVX-NEXT:    movl %esi, %eax
538; AVX-NEXT:    vucomisd %xmm1, %xmm0
539; AVX-NEXT:    cmovnel %edi, %eax
540; AVX-NEXT:    cmovpl %edi, %eax
541; AVX-NEXT:    retq
542  %call = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
543  %cmp = icmp ne i32 %call, 0
544  %res = select i1 %cmp, i32 %a2, i32 %a3
545  ret i32 %res
546}
547declare i32 @llvm.x86.sse2.ucomineq.sd(<2 x double>, <2 x double>) nounwind readnone
548
549define void @PR38960_eq(<4 x float> %A, <4 x float> %B) {
550; SSE-LABEL: PR38960_eq:
551; SSE:       # %bb.0: # %entry
552; SSE-NEXT:    comiss %xmm1, %xmm0
553; SSE-NEXT:    setnp %al
554; SSE-NEXT:    sete %cl
555; SSE-NEXT:    testb %al, %cl
556; SSE-NEXT:    je .LBB24_1
557; SSE-NEXT:  # %bb.2: # %if.then
558; SSE-NEXT:    jmp foo@PLT # TAILCALL
559; SSE-NEXT:  .LBB24_1: # %if.end
560; SSE-NEXT:    retq
561;
562; AVX-LABEL: PR38960_eq:
563; AVX:       # %bb.0: # %entry
564; AVX-NEXT:    vcomiss %xmm1, %xmm0
565; AVX-NEXT:    setnp %al
566; AVX-NEXT:    sete %cl
567; AVX-NEXT:    testb %al, %cl
568; AVX-NEXT:    je .LBB24_1
569; AVX-NEXT:  # %bb.2: # %if.then
570; AVX-NEXT:    jmp foo@PLT # TAILCALL
571; AVX-NEXT:  .LBB24_1: # %if.end
572; AVX-NEXT:    retq
573entry:
574  %call = tail call i32 @llvm.x86.sse.comieq.ss(<4 x float> %A, <4 x float> %B) #3
575  %cmp = icmp eq i32 %call, 0
576  br i1 %cmp, label %if.end, label %if.then
577
578if.then:
579  tail call void @foo()
580  br label %if.end
581
582if.end:
583  ret void
584}
585
586define void @PR38960_neq(<4 x float> %A, <4 x float> %B) {
587; SSE-LABEL: PR38960_neq:
588; SSE:       # %bb.0: # %entry
589; SSE-NEXT:    comiss %xmm1, %xmm0
590; SSE-NEXT:    setp %al
591; SSE-NEXT:    setne %cl
592; SSE-NEXT:    orb %al, %cl
593; SSE-NEXT:    je .LBB25_1
594; SSE-NEXT:  # %bb.2: # %if.then
595; SSE-NEXT:    jmp foo@PLT # TAILCALL
596; SSE-NEXT:  .LBB25_1: # %if.end
597; SSE-NEXT:    retq
598;
599; AVX-LABEL: PR38960_neq:
600; AVX:       # %bb.0: # %entry
601; AVX-NEXT:    vcomiss %xmm1, %xmm0
602; AVX-NEXT:    setp %al
603; AVX-NEXT:    setne %cl
604; AVX-NEXT:    orb %al, %cl
605; AVX-NEXT:    je .LBB25_1
606; AVX-NEXT:  # %bb.2: # %if.then
607; AVX-NEXT:    jmp foo@PLT # TAILCALL
608; AVX-NEXT:  .LBB25_1: # %if.end
609; AVX-NEXT:    retq
610entry:
611  %call = tail call i32 @llvm.x86.sse.comineq.ss(<4 x float> %A, <4 x float> %B) #3
612  %cmp = icmp eq i32 %call, 0
613  br i1 %cmp, label %if.end, label %if.then
614
615if.then:
616  tail call void @foo()
617  br label %if.end
618
619if.end:
620  ret void
621}
622declare void @foo()
623