1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2   | FileCheck %s --check-prefixes=ANY,SSE,SSE2
3; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=ANY,SSE,SSE41
4; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx    | FileCheck %s --check-prefixes=ANY,AVX
5
6define <2 x i64> @extract0_i32_zext_insert0_i64_undef(<4 x i32> %x) {
7; SSE-LABEL: extract0_i32_zext_insert0_i64_undef:
8; SSE:       # %bb.0:
9; SSE-NEXT:    movd %xmm0, %eax
10; SSE-NEXT:    movq %rax, %xmm0
11; SSE-NEXT:    retq
12;
13; AVX-LABEL: extract0_i32_zext_insert0_i64_undef:
14; AVX:       # %bb.0:
15; AVX-NEXT:    vmovd %xmm0, %eax
16; AVX-NEXT:    vmovq %rax, %xmm0
17; AVX-NEXT:    retq
18  %e = extractelement <4 x i32> %x, i32 0
19  %z = zext i32 %e to i64
20  %r = insertelement <2 x i64> undef, i64 %z, i32 0
21  ret <2 x i64> %r
22}
23
24define <2 x i64> @extract0_i32_zext_insert0_i64_zero(<4 x i32> %x) {
25; SSE-LABEL: extract0_i32_zext_insert0_i64_zero:
26; SSE:       # %bb.0:
27; SSE-NEXT:    movd %xmm0, %eax
28; SSE-NEXT:    movq %rax, %xmm0
29; SSE-NEXT:    retq
30;
31; AVX-LABEL: extract0_i32_zext_insert0_i64_zero:
32; AVX:       # %bb.0:
33; AVX-NEXT:    vmovd %xmm0, %eax
34; AVX-NEXT:    vmovq %rax, %xmm0
35; AVX-NEXT:    retq
36  %e = extractelement <4 x i32> %x, i32 0
37  %z = zext i32 %e to i64
38  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
39  ret <2 x i64> %r
40}
41
42define <2 x i64> @extract1_i32_zext_insert0_i64_undef(<4 x i32> %x) {
43; SSE2-LABEL: extract1_i32_zext_insert0_i64_undef:
44; SSE2:       # %bb.0:
45; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
46; SSE2-NEXT:    movd %xmm0, %eax
47; SSE2-NEXT:    movq %rax, %xmm0
48; SSE2-NEXT:    retq
49;
50; SSE41-LABEL: extract1_i32_zext_insert0_i64_undef:
51; SSE41:       # %bb.0:
52; SSE41-NEXT:    extractps $1, %xmm0, %eax
53; SSE41-NEXT:    movq %rax, %xmm0
54; SSE41-NEXT:    retq
55;
56; AVX-LABEL: extract1_i32_zext_insert0_i64_undef:
57; AVX:       # %bb.0:
58; AVX-NEXT:    vextractps $1, %xmm0, %eax
59; AVX-NEXT:    vmovq %rax, %xmm0
60; AVX-NEXT:    retq
61  %e = extractelement <4 x i32> %x, i32 1
62  %z = zext i32 %e to i64
63  %r = insertelement <2 x i64> undef, i64 %z, i32 0
64  ret <2 x i64> %r
65}
66
67define <2 x i64> @extract1_i32_zext_insert0_i64_zero(<4 x i32> %x) {
68; SSE2-LABEL: extract1_i32_zext_insert0_i64_zero:
69; SSE2:       # %bb.0:
70; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
71; SSE2-NEXT:    movd %xmm0, %eax
72; SSE2-NEXT:    movq %rax, %xmm0
73; SSE2-NEXT:    retq
74;
75; SSE41-LABEL: extract1_i32_zext_insert0_i64_zero:
76; SSE41:       # %bb.0:
77; SSE41-NEXT:    extractps $1, %xmm0, %eax
78; SSE41-NEXT:    movq %rax, %xmm0
79; SSE41-NEXT:    retq
80;
81; AVX-LABEL: extract1_i32_zext_insert0_i64_zero:
82; AVX:       # %bb.0:
83; AVX-NEXT:    vextractps $1, %xmm0, %eax
84; AVX-NEXT:    vmovq %rax, %xmm0
85; AVX-NEXT:    retq
86  %e = extractelement <4 x i32> %x, i32 1
87  %z = zext i32 %e to i64
88  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
89  ret <2 x i64> %r
90}
91
92define <2 x i64> @extract2_i32_zext_insert0_i64_undef(<4 x i32> %x) {
93; SSE2-LABEL: extract2_i32_zext_insert0_i64_undef:
94; SSE2:       # %bb.0:
95; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
96; SSE2-NEXT:    movd %xmm0, %eax
97; SSE2-NEXT:    movq %rax, %xmm0
98; SSE2-NEXT:    retq
99;
100; SSE41-LABEL: extract2_i32_zext_insert0_i64_undef:
101; SSE41:       # %bb.0:
102; SSE41-NEXT:    extractps $2, %xmm0, %eax
103; SSE41-NEXT:    movq %rax, %xmm0
104; SSE41-NEXT:    retq
105;
106; AVX-LABEL: extract2_i32_zext_insert0_i64_undef:
107; AVX:       # %bb.0:
108; AVX-NEXT:    vextractps $2, %xmm0, %eax
109; AVX-NEXT:    vmovq %rax, %xmm0
110; AVX-NEXT:    retq
111  %e = extractelement <4 x i32> %x, i32 2
112  %z = zext i32 %e to i64
113  %r = insertelement <2 x i64> undef, i64 %z, i32 0
114  ret <2 x i64> %r
115}
116
117define <2 x i64> @extract2_i32_zext_insert0_i64_zero(<4 x i32> %x) {
118; SSE2-LABEL: extract2_i32_zext_insert0_i64_zero:
119; SSE2:       # %bb.0:
120; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
121; SSE2-NEXT:    movd %xmm0, %eax
122; SSE2-NEXT:    movq %rax, %xmm0
123; SSE2-NEXT:    retq
124;
125; SSE41-LABEL: extract2_i32_zext_insert0_i64_zero:
126; SSE41:       # %bb.0:
127; SSE41-NEXT:    extractps $2, %xmm0, %eax
128; SSE41-NEXT:    movq %rax, %xmm0
129; SSE41-NEXT:    retq
130;
131; AVX-LABEL: extract2_i32_zext_insert0_i64_zero:
132; AVX:       # %bb.0:
133; AVX-NEXT:    vextractps $2, %xmm0, %eax
134; AVX-NEXT:    vmovq %rax, %xmm0
135; AVX-NEXT:    retq
136  %e = extractelement <4 x i32> %x, i32 2
137  %z = zext i32 %e to i64
138  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
139  ret <2 x i64> %r
140}
141
142define <2 x i64> @extract3_i32_zext_insert0_i64_undef(<4 x i32> %x) {
143; SSE2-LABEL: extract3_i32_zext_insert0_i64_undef:
144; SSE2:       # %bb.0:
145; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
146; SSE2-NEXT:    movd %xmm0, %eax
147; SSE2-NEXT:    movq %rax, %xmm0
148; SSE2-NEXT:    retq
149;
150; SSE41-LABEL: extract3_i32_zext_insert0_i64_undef:
151; SSE41:       # %bb.0:
152; SSE41-NEXT:    extractps $3, %xmm0, %eax
153; SSE41-NEXT:    movq %rax, %xmm0
154; SSE41-NEXT:    retq
155;
156; AVX-LABEL: extract3_i32_zext_insert0_i64_undef:
157; AVX:       # %bb.0:
158; AVX-NEXT:    vextractps $3, %xmm0, %eax
159; AVX-NEXT:    vmovq %rax, %xmm0
160; AVX-NEXT:    retq
161  %e = extractelement <4 x i32> %x, i32 3
162  %z = zext i32 %e to i64
163  %r = insertelement <2 x i64> undef, i64 %z, i32 0
164  ret <2 x i64> %r
165}
166
167define <2 x i64> @extract3_i32_zext_insert0_i64_zero(<4 x i32> %x) {
168; SSE2-LABEL: extract3_i32_zext_insert0_i64_zero:
169; SSE2:       # %bb.0:
170; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
171; SSE2-NEXT:    movd %xmm0, %eax
172; SSE2-NEXT:    movq %rax, %xmm0
173; SSE2-NEXT:    retq
174;
175; SSE41-LABEL: extract3_i32_zext_insert0_i64_zero:
176; SSE41:       # %bb.0:
177; SSE41-NEXT:    extractps $3, %xmm0, %eax
178; SSE41-NEXT:    movq %rax, %xmm0
179; SSE41-NEXT:    retq
180;
181; AVX-LABEL: extract3_i32_zext_insert0_i64_zero:
182; AVX:       # %bb.0:
183; AVX-NEXT:    vextractps $3, %xmm0, %eax
184; AVX-NEXT:    vmovq %rax, %xmm0
185; AVX-NEXT:    retq
186  %e = extractelement <4 x i32> %x, i32 3
187  %z = zext i32 %e to i64
188  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
189  ret <2 x i64> %r
190}
191
192define <2 x i64> @extract0_i32_zext_insert1_i64_undef(<4 x i32> %x) {
193; SSE-LABEL: extract0_i32_zext_insert1_i64_undef:
194; SSE:       # %bb.0:
195; SSE-NEXT:    movd %xmm0, %eax
196; SSE-NEXT:    movq %rax, %xmm0
197; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
198; SSE-NEXT:    retq
199;
200; AVX-LABEL: extract0_i32_zext_insert1_i64_undef:
201; AVX:       # %bb.0:
202; AVX-NEXT:    vmovd %xmm0, %eax
203; AVX-NEXT:    vmovq %rax, %xmm0
204; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
205; AVX-NEXT:    retq
206  %e = extractelement <4 x i32> %x, i32 0
207  %z = zext i32 %e to i64
208  %r = insertelement <2 x i64> undef, i64 %z, i32 1
209  ret <2 x i64> %r
210}
211
212define <2 x i64> @extract0_i32_zext_insert1_i64_zero(<4 x i32> %x) {
213; SSE-LABEL: extract0_i32_zext_insert1_i64_zero:
214; SSE:       # %bb.0:
215; SSE-NEXT:    movd %xmm0, %eax
216; SSE-NEXT:    movq %rax, %xmm0
217; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
218; SSE-NEXT:    retq
219;
220; AVX-LABEL: extract0_i32_zext_insert1_i64_zero:
221; AVX:       # %bb.0:
222; AVX-NEXT:    vmovd %xmm0, %eax
223; AVX-NEXT:    vmovq %rax, %xmm0
224; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
225; AVX-NEXT:    retq
226  %e = extractelement <4 x i32> %x, i32 0
227  %z = zext i32 %e to i64
228  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
229  ret <2 x i64> %r
230}
231
232define <2 x i64> @extract1_i32_zext_insert1_i64_undef(<4 x i32> %x) {
233; SSE2-LABEL: extract1_i32_zext_insert1_i64_undef:
234; SSE2:       # %bb.0:
235; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
236; SSE2-NEXT:    movd %xmm0, %eax
237; SSE2-NEXT:    movq %rax, %xmm0
238; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
239; SSE2-NEXT:    retq
240;
241; SSE41-LABEL: extract1_i32_zext_insert1_i64_undef:
242; SSE41:       # %bb.0:
243; SSE41-NEXT:    extractps $1, %xmm0, %eax
244; SSE41-NEXT:    movq %rax, %xmm0
245; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
246; SSE41-NEXT:    retq
247;
248; AVX-LABEL: extract1_i32_zext_insert1_i64_undef:
249; AVX:       # %bb.0:
250; AVX-NEXT:    vextractps $1, %xmm0, %eax
251; AVX-NEXT:    vmovq %rax, %xmm0
252; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
253; AVX-NEXT:    retq
254  %e = extractelement <4 x i32> %x, i32 1
255  %z = zext i32 %e to i64
256  %r = insertelement <2 x i64> undef, i64 %z, i32 1
257  ret <2 x i64> %r
258}
259
260define <2 x i64> @extract1_i32_zext_insert1_i64_zero(<4 x i32> %x) {
261; SSE2-LABEL: extract1_i32_zext_insert1_i64_zero:
262; SSE2:       # %bb.0:
263; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
264; SSE2-NEXT:    movd %xmm0, %eax
265; SSE2-NEXT:    movq %rax, %xmm0
266; SSE2-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
267; SSE2-NEXT:    retq
268;
269; SSE41-LABEL: extract1_i32_zext_insert1_i64_zero:
270; SSE41:       # %bb.0:
271; SSE41-NEXT:    extractps $1, %xmm0, %eax
272; SSE41-NEXT:    movq %rax, %xmm0
273; SSE41-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
274; SSE41-NEXT:    retq
275;
276; AVX-LABEL: extract1_i32_zext_insert1_i64_zero:
277; AVX:       # %bb.0:
278; AVX-NEXT:    vextractps $1, %xmm0, %eax
279; AVX-NEXT:    vmovq %rax, %xmm0
280; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
281; AVX-NEXT:    retq
282  %e = extractelement <4 x i32> %x, i32 1
283  %z = zext i32 %e to i64
284  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
285  ret <2 x i64> %r
286}
287
288define <2 x i64> @extract2_i32_zext_insert1_i64_undef(<4 x i32> %x) {
289; SSE2-LABEL: extract2_i32_zext_insert1_i64_undef:
290; SSE2:       # %bb.0:
291; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
292; SSE2-NEXT:    movd %xmm0, %eax
293; SSE2-NEXT:    movq %rax, %xmm0
294; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
295; SSE2-NEXT:    retq
296;
297; SSE41-LABEL: extract2_i32_zext_insert1_i64_undef:
298; SSE41:       # %bb.0:
299; SSE41-NEXT:    extractps $2, %xmm0, %eax
300; SSE41-NEXT:    movq %rax, %xmm0
301; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
302; SSE41-NEXT:    retq
303;
304; AVX-LABEL: extract2_i32_zext_insert1_i64_undef:
305; AVX:       # %bb.0:
306; AVX-NEXT:    vextractps $2, %xmm0, %eax
307; AVX-NEXT:    vmovq %rax, %xmm0
308; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
309; AVX-NEXT:    retq
310  %e = extractelement <4 x i32> %x, i32 2
311  %z = zext i32 %e to i64
312  %r = insertelement <2 x i64> undef, i64 %z, i32 1
313  ret <2 x i64> %r
314}
315
316define <2 x i64> @extract2_i32_zext_insert1_i64_zero(<4 x i32> %x) {
317; SSE2-LABEL: extract2_i32_zext_insert1_i64_zero:
318; SSE2:       # %bb.0:
319; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
320; SSE2-NEXT:    movd %xmm0, %eax
321; SSE2-NEXT:    movq %rax, %xmm0
322; SSE2-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
323; SSE2-NEXT:    retq
324;
325; SSE41-LABEL: extract2_i32_zext_insert1_i64_zero:
326; SSE41:       # %bb.0:
327; SSE41-NEXT:    extractps $2, %xmm0, %eax
328; SSE41-NEXT:    movq %rax, %xmm0
329; SSE41-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
330; SSE41-NEXT:    retq
331;
332; AVX-LABEL: extract2_i32_zext_insert1_i64_zero:
333; AVX:       # %bb.0:
334; AVX-NEXT:    vextractps $2, %xmm0, %eax
335; AVX-NEXT:    vmovq %rax, %xmm0
336; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
337; AVX-NEXT:    retq
338  %e = extractelement <4 x i32> %x, i32 2
339  %z = zext i32 %e to i64
340  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
341  ret <2 x i64> %r
342}
343
344define <2 x i64> @extract3_i32_zext_insert1_i64_undef(<4 x i32> %x) {
345; SSE2-LABEL: extract3_i32_zext_insert1_i64_undef:
346; SSE2:       # %bb.0:
347; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
348; SSE2-NEXT:    movd %xmm0, %eax
349; SSE2-NEXT:    movq %rax, %xmm0
350; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
351; SSE2-NEXT:    retq
352;
353; SSE41-LABEL: extract3_i32_zext_insert1_i64_undef:
354; SSE41:       # %bb.0:
355; SSE41-NEXT:    extractps $3, %xmm0, %eax
356; SSE41-NEXT:    movq %rax, %xmm0
357; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
358; SSE41-NEXT:    retq
359;
360; AVX-LABEL: extract3_i32_zext_insert1_i64_undef:
361; AVX:       # %bb.0:
362; AVX-NEXT:    vextractps $3, %xmm0, %eax
363; AVX-NEXT:    vmovq %rax, %xmm0
364; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
365; AVX-NEXT:    retq
366  %e = extractelement <4 x i32> %x, i32 3
367  %z = zext i32 %e to i64
368  %r = insertelement <2 x i64> undef, i64 %z, i32 1
369  ret <2 x i64> %r
370}
371
372define <2 x i64> @extract3_i32_zext_insert1_i64_zero(<4 x i32> %x) {
373; SSE2-LABEL: extract3_i32_zext_insert1_i64_zero:
374; SSE2:       # %bb.0:
375; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
376; SSE2-NEXT:    movd %xmm0, %eax
377; SSE2-NEXT:    movq %rax, %xmm0
378; SSE2-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
379; SSE2-NEXT:    retq
380;
381; SSE41-LABEL: extract3_i32_zext_insert1_i64_zero:
382; SSE41:       # %bb.0:
383; SSE41-NEXT:    extractps $3, %xmm0, %eax
384; SSE41-NEXT:    movq %rax, %xmm0
385; SSE41-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
386; SSE41-NEXT:    retq
387;
388; AVX-LABEL: extract3_i32_zext_insert1_i64_zero:
389; AVX:       # %bb.0:
390; AVX-NEXT:    vextractps $3, %xmm0, %eax
391; AVX-NEXT:    vmovq %rax, %xmm0
392; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
393; AVX-NEXT:    retq
394  %e = extractelement <4 x i32> %x, i32 3
395  %z = zext i32 %e to i64
396  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
397  ret <2 x i64> %r
398}
399
400define <2 x i64> @extract0_i16_zext_insert0_i64_undef(<8 x i16> %x) {
401; SSE-LABEL: extract0_i16_zext_insert0_i64_undef:
402; SSE:       # %bb.0:
403; SSE-NEXT:    pextrw $0, %xmm0, %eax
404; SSE-NEXT:    movq %rax, %xmm0
405; SSE-NEXT:    retq
406;
407; AVX-LABEL: extract0_i16_zext_insert0_i64_undef:
408; AVX:       # %bb.0:
409; AVX-NEXT:    vpextrw $0, %xmm0, %eax
410; AVX-NEXT:    vmovq %rax, %xmm0
411; AVX-NEXT:    retq
412  %e = extractelement <8 x i16> %x, i32 0
413  %z = zext i16 %e to i64
414  %r = insertelement <2 x i64> undef, i64 %z, i32 0
415  ret <2 x i64> %r
416}
417
418define <2 x i64> @extract0_i16_zext_insert0_i64_zero(<8 x i16> %x) {
419; SSE-LABEL: extract0_i16_zext_insert0_i64_zero:
420; SSE:       # %bb.0:
421; SSE-NEXT:    pextrw $0, %xmm0, %eax
422; SSE-NEXT:    movq %rax, %xmm0
423; SSE-NEXT:    retq
424;
425; AVX-LABEL: extract0_i16_zext_insert0_i64_zero:
426; AVX:       # %bb.0:
427; AVX-NEXT:    vpextrw $0, %xmm0, %eax
428; AVX-NEXT:    vmovq %rax, %xmm0
429; AVX-NEXT:    retq
430  %e = extractelement <8 x i16> %x, i32 0
431  %z = zext i16 %e to i64
432  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
433  ret <2 x i64> %r
434}
435
436define <2 x i64> @extract1_i16_zext_insert0_i64_undef(<8 x i16> %x) {
437; SSE-LABEL: extract1_i16_zext_insert0_i64_undef:
438; SSE:       # %bb.0:
439; SSE-NEXT:    pextrw $1, %xmm0, %eax
440; SSE-NEXT:    movq %rax, %xmm0
441; SSE-NEXT:    retq
442;
443; AVX-LABEL: extract1_i16_zext_insert0_i64_undef:
444; AVX:       # %bb.0:
445; AVX-NEXT:    vpextrw $1, %xmm0, %eax
446; AVX-NEXT:    vmovq %rax, %xmm0
447; AVX-NEXT:    retq
448  %e = extractelement <8 x i16> %x, i32 1
449  %z = zext i16 %e to i64
450  %r = insertelement <2 x i64> undef, i64 %z, i32 0
451  ret <2 x i64> %r
452}
453
454define <2 x i64> @extract1_i16_zext_insert0_i64_zero(<8 x i16> %x) {
455; SSE-LABEL: extract1_i16_zext_insert0_i64_zero:
456; SSE:       # %bb.0:
457; SSE-NEXT:    pextrw $1, %xmm0, %eax
458; SSE-NEXT:    movq %rax, %xmm0
459; SSE-NEXT:    retq
460;
461; AVX-LABEL: extract1_i16_zext_insert0_i64_zero:
462; AVX:       # %bb.0:
463; AVX-NEXT:    vpextrw $1, %xmm0, %eax
464; AVX-NEXT:    vmovq %rax, %xmm0
465; AVX-NEXT:    retq
466  %e = extractelement <8 x i16> %x, i32 1
467  %z = zext i16 %e to i64
468  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
469  ret <2 x i64> %r
470}
471
472define <2 x i64> @extract2_i16_zext_insert0_i64_undef(<8 x i16> %x) {
473; SSE-LABEL: extract2_i16_zext_insert0_i64_undef:
474; SSE:       # %bb.0:
475; SSE-NEXT:    pextrw $2, %xmm0, %eax
476; SSE-NEXT:    movq %rax, %xmm0
477; SSE-NEXT:    retq
478;
479; AVX-LABEL: extract2_i16_zext_insert0_i64_undef:
480; AVX:       # %bb.0:
481; AVX-NEXT:    vpextrw $2, %xmm0, %eax
482; AVX-NEXT:    vmovq %rax, %xmm0
483; AVX-NEXT:    retq
484  %e = extractelement <8 x i16> %x, i32 2
485  %z = zext i16 %e to i64
486  %r = insertelement <2 x i64> undef, i64 %z, i32 0
487  ret <2 x i64> %r
488}
489
490define <2 x i64> @extract2_i16_zext_insert0_i64_zero(<8 x i16> %x) {
491; SSE-LABEL: extract2_i16_zext_insert0_i64_zero:
492; SSE:       # %bb.0:
493; SSE-NEXT:    pextrw $2, %xmm0, %eax
494; SSE-NEXT:    movq %rax, %xmm0
495; SSE-NEXT:    retq
496;
497; AVX-LABEL: extract2_i16_zext_insert0_i64_zero:
498; AVX:       # %bb.0:
499; AVX-NEXT:    vpextrw $2, %xmm0, %eax
500; AVX-NEXT:    vmovq %rax, %xmm0
501; AVX-NEXT:    retq
502  %e = extractelement <8 x i16> %x, i32 2
503  %z = zext i16 %e to i64
504  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
505  ret <2 x i64> %r
506}
507
508define <2 x i64> @extract3_i16_zext_insert0_i64_undef(<8 x i16> %x) {
509; SSE-LABEL: extract3_i16_zext_insert0_i64_undef:
510; SSE:       # %bb.0:
511; SSE-NEXT:    pextrw $3, %xmm0, %eax
512; SSE-NEXT:    movq %rax, %xmm0
513; SSE-NEXT:    retq
514;
515; AVX-LABEL: extract3_i16_zext_insert0_i64_undef:
516; AVX:       # %bb.0:
517; AVX-NEXT:    vpextrw $3, %xmm0, %eax
518; AVX-NEXT:    vmovq %rax, %xmm0
519; AVX-NEXT:    retq
520  %e = extractelement <8 x i16> %x, i32 3
521  %z = zext i16 %e to i64
522  %r = insertelement <2 x i64> undef, i64 %z, i32 0
523  ret <2 x i64> %r
524}
525
526define <2 x i64> @extract3_i16_zext_insert0_i64_zero(<8 x i16> %x) {
527; SSE-LABEL: extract3_i16_zext_insert0_i64_zero:
528; SSE:       # %bb.0:
529; SSE-NEXT:    pextrw $3, %xmm0, %eax
530; SSE-NEXT:    movq %rax, %xmm0
531; SSE-NEXT:    retq
532;
533; AVX-LABEL: extract3_i16_zext_insert0_i64_zero:
534; AVX:       # %bb.0:
535; AVX-NEXT:    vpextrw $3, %xmm0, %eax
536; AVX-NEXT:    vmovq %rax, %xmm0
537; AVX-NEXT:    retq
538  %e = extractelement <8 x i16> %x, i32 3
539  %z = zext i16 %e to i64
540  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
541  ret <2 x i64> %r
542}
543
544define <2 x i64> @extract0_i16_zext_insert1_i64_undef(<8 x i16> %x) {
545; SSE-LABEL: extract0_i16_zext_insert1_i64_undef:
546; SSE:       # %bb.0:
547; SSE-NEXT:    pextrw $0, %xmm0, %eax
548; SSE-NEXT:    movq %rax, %xmm0
549; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
550; SSE-NEXT:    retq
551;
552; AVX-LABEL: extract0_i16_zext_insert1_i64_undef:
553; AVX:       # %bb.0:
554; AVX-NEXT:    vpextrw $0, %xmm0, %eax
555; AVX-NEXT:    vmovq %rax, %xmm0
556; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
557; AVX-NEXT:    retq
558  %e = extractelement <8 x i16> %x, i32 0
559  %z = zext i16 %e to i64
560  %r = insertelement <2 x i64> undef, i64 %z, i32 1
561  ret <2 x i64> %r
562}
563
564define <2 x i64> @extract0_i16_zext_insert1_i64_zero(<8 x i16> %x) {
565; SSE-LABEL: extract0_i16_zext_insert1_i64_zero:
566; SSE:       # %bb.0:
567; SSE-NEXT:    pextrw $0, %xmm0, %eax
568; SSE-NEXT:    movq %rax, %xmm0
569; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
570; SSE-NEXT:    retq
571;
572; AVX-LABEL: extract0_i16_zext_insert1_i64_zero:
573; AVX:       # %bb.0:
574; AVX-NEXT:    vpextrw $0, %xmm0, %eax
575; AVX-NEXT:    vmovq %rax, %xmm0
576; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
577; AVX-NEXT:    retq
578  %e = extractelement <8 x i16> %x, i32 0
579  %z = zext i16 %e to i64
580  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
581  ret <2 x i64> %r
582}
583
584define <2 x i64> @extract1_i16_zext_insert1_i64_undef(<8 x i16> %x) {
585; SSE-LABEL: extract1_i16_zext_insert1_i64_undef:
586; SSE:       # %bb.0:
587; SSE-NEXT:    pextrw $1, %xmm0, %eax
588; SSE-NEXT:    movq %rax, %xmm0
589; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
590; SSE-NEXT:    retq
591;
592; AVX-LABEL: extract1_i16_zext_insert1_i64_undef:
593; AVX:       # %bb.0:
594; AVX-NEXT:    vpextrw $1, %xmm0, %eax
595; AVX-NEXT:    vmovq %rax, %xmm0
596; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
597; AVX-NEXT:    retq
598  %e = extractelement <8 x i16> %x, i32 1
599  %z = zext i16 %e to i64
600  %r = insertelement <2 x i64> undef, i64 %z, i32 1
601  ret <2 x i64> %r
602}
603
604define <2 x i64> @extract1_i16_zext_insert1_i64_zero(<8 x i16> %x) {
605; SSE-LABEL: extract1_i16_zext_insert1_i64_zero:
606; SSE:       # %bb.0:
607; SSE-NEXT:    pextrw $1, %xmm0, %eax
608; SSE-NEXT:    movq %rax, %xmm0
609; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
610; SSE-NEXT:    retq
611;
612; AVX-LABEL: extract1_i16_zext_insert1_i64_zero:
613; AVX:       # %bb.0:
614; AVX-NEXT:    vpextrw $1, %xmm0, %eax
615; AVX-NEXT:    vmovq %rax, %xmm0
616; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
617; AVX-NEXT:    retq
618  %e = extractelement <8 x i16> %x, i32 1
619  %z = zext i16 %e to i64
620  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
621  ret <2 x i64> %r
622}
623
624define <2 x i64> @extract2_i16_zext_insert1_i64_undef(<8 x i16> %x) {
625; SSE-LABEL: extract2_i16_zext_insert1_i64_undef:
626; SSE:       # %bb.0:
627; SSE-NEXT:    pextrw $2, %xmm0, %eax
628; SSE-NEXT:    movq %rax, %xmm0
629; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
630; SSE-NEXT:    retq
631;
632; AVX-LABEL: extract2_i16_zext_insert1_i64_undef:
633; AVX:       # %bb.0:
634; AVX-NEXT:    vpextrw $2, %xmm0, %eax
635; AVX-NEXT:    vmovq %rax, %xmm0
636; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
637; AVX-NEXT:    retq
638  %e = extractelement <8 x i16> %x, i32 2
639  %z = zext i16 %e to i64
640  %r = insertelement <2 x i64> undef, i64 %z, i32 1
641  ret <2 x i64> %r
642}
643
644define <2 x i64> @extract2_i16_zext_insert1_i64_zero(<8 x i16> %x) {
645; SSE-LABEL: extract2_i16_zext_insert1_i64_zero:
646; SSE:       # %bb.0:
647; SSE-NEXT:    pextrw $2, %xmm0, %eax
648; SSE-NEXT:    movq %rax, %xmm0
649; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
650; SSE-NEXT:    retq
651;
652; AVX-LABEL: extract2_i16_zext_insert1_i64_zero:
653; AVX:       # %bb.0:
654; AVX-NEXT:    vpextrw $2, %xmm0, %eax
655; AVX-NEXT:    vmovq %rax, %xmm0
656; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
657; AVX-NEXT:    retq
658  %e = extractelement <8 x i16> %x, i32 2
659  %z = zext i16 %e to i64
660  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
661  ret <2 x i64> %r
662}
663
664define <2 x i64> @extract3_i16_zext_insert1_i64_undef(<8 x i16> %x) {
665; SSE-LABEL: extract3_i16_zext_insert1_i64_undef:
666; SSE:       # %bb.0:
667; SSE-NEXT:    pextrw $3, %xmm0, %eax
668; SSE-NEXT:    movq %rax, %xmm0
669; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
670; SSE-NEXT:    retq
671;
672; AVX-LABEL: extract3_i16_zext_insert1_i64_undef:
673; AVX:       # %bb.0:
674; AVX-NEXT:    vpextrw $3, %xmm0, %eax
675; AVX-NEXT:    vmovq %rax, %xmm0
676; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
677; AVX-NEXT:    retq
678  %e = extractelement <8 x i16> %x, i32 3
679  %z = zext i16 %e to i64
680  %r = insertelement <2 x i64> undef, i64 %z, i32 1
681  ret <2 x i64> %r
682}
683
684define <2 x i64> @extract3_i16_zext_insert1_i64_zero(<8 x i16> %x) {
685; SSE-LABEL: extract3_i16_zext_insert1_i64_zero:
686; SSE:       # %bb.0:
687; SSE-NEXT:    pextrw $3, %xmm0, %eax
688; SSE-NEXT:    movq %rax, %xmm0
689; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
690; SSE-NEXT:    retq
691;
692; AVX-LABEL: extract3_i16_zext_insert1_i64_zero:
693; AVX:       # %bb.0:
694; AVX-NEXT:    vpextrw $3, %xmm0, %eax
695; AVX-NEXT:    vmovq %rax, %xmm0
696; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
697; AVX-NEXT:    retq
698  %e = extractelement <8 x i16> %x, i32 3
699  %z = zext i16 %e to i64
700  %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
701  ret <2 x i64> %r
702}
703
704