1; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
2; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
3; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
4
5; Test that basic SIMD128 vector manipulation operations assemble as expected.
6
7target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
8target triple = "wasm32-unknown-unknown"
9
10; ==============================================================================
11; 16 x i8
12; ==============================================================================
13; CHECK-LABEL: const_v16i8:
14; NO-SIMD128-NOT: i8x16
15; SIMD128: .result v128{{$}}
16; SIMD128: v128.const $push0=,
17; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
18; SIMD128-SAME: # encoding: [0xfd,0x00,
19; SIMD128-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
20; SIMD128-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]{{$}}
21define <16 x i8> @const_v16i8() {
22  ret <16 x i8> <i8 00, i8 01, i8 02, i8 03, i8 04, i8 05, i8 06, i8 07,
23                 i8 08, i8 09, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>
24}
25
26; CHECK-LABEL: splat_v16i8:
27; NO-SIMD128-NOT: i8x16
28; SIMD128: .param i32{{$}}
29; SIMD128: .result v128{{$}}
30; SIMD128: i8x16.splat $push0=, $0 # encoding: [0xfd,0x03]{{$}}
31; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
32define <16 x i8> @splat_v16i8(i8 %x) {
33  %v = insertelement <16 x i8> undef, i8 %x, i32 0
34  %res = shufflevector <16 x i8> %v, <16 x i8> undef,
35    <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
36                i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
37  ret <16 x i8> %res
38}
39
40; CHECK-LABEL: extract_v16i8_s:
41; NO-SIMD128-NOT: i8x16
42; SIMD128: .param v128{{$}}
43; SIMD128: .result i32{{$}}
44; SIMD128: i8x16.extract_lane_s $push0=, $0, 13 # encoding: [0xfd,0x09,0x0d]{{$}}
45; SIMD128: return $pop0 #
46define i32 @extract_v16i8_s(<16 x i8> %v) {
47  %elem = extractelement <16 x i8> %v, i8 13
48  %a = sext i8 %elem to i32
49  ret i32 %a
50}
51
52; CHECK-LABEL: extract_v16i8_u:
53; NO-SIMD128-NOT: i8x16
54; SIMD128: .param v128{{$}}
55; SIMD128: .result i32{{$}}
56; SIMD128: i8x16.extract_lane_u $push0=, $0, 13 # encoding: [0xfd,0x0a,0x0d]{{$}}
57; SIMD128: return $pop0 #
58define i32 @extract_v16i8_u(<16 x i8> %v) {
59  %elem = extractelement <16 x i8> %v, i8 13
60  %a = zext i8 %elem to i32
61  ret i32 %a
62}
63
64; CHECK-LABEL: extract_v16i8:
65; NO-SIMD128-NOT: i8x16
66; SIMD128: .param v128{{$}}
67; SIMD128: .result i32{{$}}
68; SIMD128: i8x16.extract_lane_u $push0=, $0, 13 # encoding: [0xfd,0x0a,0x0d]{{$}}
69; SIMD128: return $pop0 #
70define i8 @extract_v16i8(<16 x i8> %v) {
71  %elem = extractelement <16 x i8> %v, i8 13
72  ret i8 %elem
73}
74
75; CHECK-LABEL: replace_v16i8:
76; NO-SIMD128-NOT: i8x16
77; SIMD128: .param v128, i32{{$}}
78; SIMD128: .result v128{{$}}
79; SIMD128: i8x16.replace_lane $push0=, $0, 11, $1 # encoding: [0xfd,0x11,0x0b]{{$}}
80; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
81define <16 x i8> @replace_v16i8(<16 x i8> %v, i8 %x) {
82  %res = insertelement <16 x i8> %v, i8 %x, i32 11
83  ret <16 x i8> %res
84}
85
86; CHECK-LABEL: build_v16i8:
87; NO-SIMD128-NOT: i8x16
88; SIMD128: .param i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32{{$}}
89; SIMD128: .result v128{{$}}
90; SIMD128: i8x16.splat $push0=, $0 # encoding: [0xfd,0x03]
91; SIMD128: i8x16.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x11,0x01]
92; SIMD128: i8x16.replace_lane $push2=, $pop1, 2, $2 # encoding: [0xfd,0x11,0x02]
93; SIMD128: i8x16.replace_lane $push3=, $pop2, 3, $3 # encoding: [0xfd,0x11,0x03]
94; SIMD128: i8x16.replace_lane $push4=, $pop3, 4, $4 # encoding: [0xfd,0x11,0x04]
95; SIMD128: i8x16.replace_lane $push5=, $pop4, 5, $5 # encoding: [0xfd,0x11,0x05]
96; SIMD128: i8x16.replace_lane $push6=, $pop5, 6, $6 # encoding: [0xfd,0x11,0x06]
97; SIMD128: i8x16.replace_lane $push7=, $pop6, 7, $7 # encoding: [0xfd,0x11,0x07]
98; SIMD128: i8x16.replace_lane $push8=, $pop7, 8, $8 # encoding: [0xfd,0x11,0x08]
99; SIMD128: i8x16.replace_lane $push9=, $pop8, 9, $9 # encoding: [0xfd,0x11,0x09]
100; SIMD128: i8x16.replace_lane $push10=, $pop9, 10, $10 # encoding: [0xfd,0x11,0x0a]
101; SIMD128: i8x16.replace_lane $push11=, $pop10, 11, $11 # encoding: [0xfd,0x11,0x0b]
102; SIMD128: i8x16.replace_lane $push12=, $pop11, 12, $12 # encoding: [0xfd,0x11,0x0c]
103; SIMD128: i8x16.replace_lane $push13=, $pop12, 13, $13 # encoding: [0xfd,0x11,0x0d]
104; SIMD128: i8x16.replace_lane $push14=, $pop13, 14, $14 # encoding: [0xfd,0x11,0x0e]
105; SIMD128: i8x16.replace_lane $push15=, $pop14, 15, $15 # encoding: [0xfd,0x11,0x0f]
106; SIMD128: return $pop15 # encoding: [0x0f]
107define <16 x i8> @build_v16i8(i8 %x0, i8 %x1, i8 %x2, i8 %x3,
108                              i8 %x4, i8 %x5, i8 %x6, i8 %x7,
109                              i8 %x8, i8 %x9, i8 %x10, i8 %x11,
110                              i8 %x12, i8 %x13, i8 %x14, i8 %x15) {
111  %t0 = insertelement <16 x i8> undef, i8 %x0, i32 0
112  %t1 = insertelement <16 x i8> %t0, i8 %x1, i32 1
113  %t2 = insertelement <16 x i8> %t1, i8 %x2, i32 2
114  %t3 = insertelement <16 x i8> %t2, i8 %x3, i32 3
115  %t4 = insertelement <16 x i8> %t3, i8 %x4, i32 4
116  %t5 = insertelement <16 x i8> %t4, i8 %x5, i32 5
117  %t6 = insertelement <16 x i8> %t5, i8 %x6, i32 6
118  %t7 = insertelement <16 x i8> %t6, i8 %x7, i32 7
119  %t8 = insertelement <16 x i8> %t7, i8 %x8, i32 8
120  %t9 = insertelement <16 x i8> %t8, i8 %x9, i32 9
121  %t10 = insertelement <16 x i8> %t9, i8 %x10, i32 10
122  %t11 = insertelement <16 x i8> %t10, i8 %x11, i32 11
123  %t12 = insertelement <16 x i8> %t11, i8 %x12, i32 12
124  %t13 = insertelement <16 x i8> %t12, i8 %x13, i32 13
125  %t14 = insertelement <16 x i8> %t13, i8 %x14, i32 14
126  %res = insertelement <16 x i8> %t14, i8 %x15, i32 15
127  ret <16 x i8> %res
128}
129
130; ==============================================================================
131; 8 x i16
132; ==============================================================================
133; CHECK-LABEL: const_v8i16:
134; NO-SIMD128-NOT: i16x8
135; SIMD128: .result v128{{$}}
136; SIMD128: v128.const $push0=, 256, 770, 1284, 1798, 2312, 2826, 3340, 3854
137; SIMD128-SAME: # encoding: [0xfd,0x00,
138; SIMD128-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
139; SIMD128-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]{{$}}
140define <8 x i16> @const_v8i16() {
141  ret <8 x i16> <i16 256, i16 770, i16 1284, i16 1798,
142                 i16 2312, i16 2826, i16 3340, i16 3854>
143}
144
145; CHECK-LABEL: splat_v8i16:
146; NO-SIMD128-NOT: i16x8
147; SIMD128: .param i32{{$}}
148; SIMD128: .result v128{{$}}
149; SIMD128: i16x8.splat $push0=, $0 # encoding: [0xfd,0x04]{{$}}
150; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
151define <8 x i16> @splat_v8i16(i16 %x) {
152  %v = insertelement <8 x i16> undef, i16 %x, i32 0
153  %res = shufflevector <8 x i16> %v, <8 x i16> undef,
154    <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
155  ret <8 x i16> %res
156}
157
158; CHECK-LABEL: extract_v8i16_s:
159; NO-SIMD128-NOT: i16x8
160; SIMD128: .param v128{{$}}
161; SIMD128: .result i32{{$}}
162; SIMD128: i16x8.extract_lane_s $push0=, $0, 5 # encoding: [0xfd,0x0b,0x05]{{$}}
163; SIMD128: return $pop0 #
164define i32 @extract_v8i16_s(<8 x i16> %v) {
165  %elem = extractelement <8 x i16> %v, i16 5
166  %a = sext i16 %elem to i32
167  ret i32 %a
168}
169
170; CHECK-LABEL: extract_v8i16_u:
171; NO-SIMD128-NOT: i16x8
172; SIMD128: .param v128{{$}}
173; SIMD128: .result i32{{$}}
174; SIMD128: i16x8.extract_lane_u $push0=, $0, 5 # encoding: [0xfd,0x0c,0x05]{{$}}
175; SIMD128: return $pop0 #
176define i32 @extract_v8i16_u(<8 x i16> %v) {
177  %elem = extractelement <8 x i16> %v, i16 5
178  %a = zext i16 %elem to i32
179  ret i32 %a
180}
181
182; CHECK-LABEL: extract_v8i16:
183; NO-SIMD128-NOT: i16x8
184; SIMD128: .param v128{{$}}
185; SIMD128: .result i32{{$}}
186; SIMD128: i16x8.extract_lane_u $push0=, $0, 5 # encoding: [0xfd,0x0c,0x05]{{$}}
187; SIMD128: return $pop0 #
188define i16 @extract_v8i16(<8 x i16> %v) {
189  %elem = extractelement <8 x i16> %v, i16 5
190  ret i16 %elem
191}
192
193; CHECK-LABEL: replace_v8i16:
194; NO-SIMD128-NOT: i16x8
195; SIMD128: .param v128, i32{{$}}
196; SIMD128: .result v128{{$}}
197; SIMD128: i16x8.replace_lane $push0=, $0, 7, $1 # encoding: [0xfd,0x12,0x07]{{$}}
198; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
199define <8 x i16> @replace_v8i16(<8 x i16> %v, i16 %x) {
200  %res = insertelement <8 x i16> %v, i16 %x, i32 7
201  ret <8 x i16> %res
202}
203
204; CHECK-LABEL: build_v8i16:
205; NO-SIMD128-NOT: i16x8
206; SIMD128: .param i32, i32, i32, i32, i32, i32, i32, i32{{$}}
207; SIMD128: .result v128{{$}}
208; SIMD128: i16x8.splat $push0=, $0 # encoding: [0xfd,0x04]
209; SIMD128: i16x8.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x12,0x01]
210; SIMD128: i16x8.replace_lane $push2=, $pop1, 2, $2 # encoding: [0xfd,0x12,0x02]
211; SIMD128: i16x8.replace_lane $push3=, $pop2, 3, $3 # encoding: [0xfd,0x12,0x03]
212; SIMD128: i16x8.replace_lane $push4=, $pop3, 4, $4 # encoding: [0xfd,0x12,0x04]
213; SIMD128: i16x8.replace_lane $push5=, $pop4, 5, $5 # encoding: [0xfd,0x12,0x05]
214; SIMD128: i16x8.replace_lane $push6=, $pop5, 6, $6 # encoding: [0xfd,0x12,0x06]
215; SIMD128: i16x8.replace_lane $push7=, $pop6, 7, $7 # encoding: [0xfd,0x12,0x07]
216; SIMD128: return $pop7 # encoding: [0x0f]
217define <8 x i16> @build_v8i16(i16 %x0, i16 %x1, i16 %x2, i16 %x3,
218                              i16 %x4, i16 %x5, i16 %x6, i16 %x7) {
219  %t0 = insertelement <8 x i16> undef, i16 %x0, i32 0
220  %t1 = insertelement <8 x i16> %t0, i16 %x1, i32 1
221  %t2 = insertelement <8 x i16> %t1, i16 %x2, i32 2
222  %t3 = insertelement <8 x i16> %t2, i16 %x3, i32 3
223  %t4 = insertelement <8 x i16> %t3, i16 %x4, i32 4
224  %t5 = insertelement <8 x i16> %t4, i16 %x5, i32 5
225  %t6 = insertelement <8 x i16> %t5, i16 %x6, i32 6
226  %res = insertelement <8 x i16> %t6, i16 %x7, i32 7
227  ret <8 x i16> %res
228}
229
230; ==============================================================================
231; 4 x i32
232; ==============================================================================
233; CHECK-LABEL: const_v4i32:
234; NO-SIMD128-NOT: i32x4
235; SIMD128: .result v128{{$}}
236; SIMD128: v128.const $push0=, 50462976, 117835012, 185207048, 252579084
237; SIMD128-SAME: # encoding: [0xfd,0x00,
238; SIMD128-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
239; SIMD128-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]{{$}}
240define <4 x i32> @const_v4i32() {
241  ret <4 x i32> <i32 50462976, i32 117835012, i32 185207048, i32 252579084>
242}
243
244; CHECK-LABEL: splat_v4i32:
245; NO-SIMD128-NOT: i32x4
246; SIMD128: .param i32{{$}}
247; SIMD128: .result v128{{$}}
248; SIMD128: i32x4.splat $push0=, $0 # encoding: [0xfd,0x05]{{$}}
249; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
250define <4 x i32> @splat_v4i32(i32 %x) {
251  %v = insertelement <4 x i32> undef, i32 %x, i32 0
252  %res = shufflevector <4 x i32> %v, <4 x i32> undef,
253    <4 x i32> <i32 0, i32 0, i32 0, i32 0>
254  ret <4 x i32> %res
255}
256
257; CHECK-LABEL: extract_v4i32:
258; NO-SIMD128-NOT: i32x4
259; SIMD128: .param v128{{$}}
260; SIMD128: .result i32{{$}}
261; SIMD128: i32x4.extract_lane $push0=, $0, 3 # encoding: [0xfd,0x0d,0x03]{{$}}
262; SIMD128: return $pop0 #
263define i32 @extract_v4i32(<4 x i32> %v) {
264  %elem = extractelement <4 x i32> %v, i32 3
265  ret i32 %elem
266}
267
268; CHECK-LABEL: replace_v4i32:
269; NO-SIMD128-NOT: i32x4
270; SIMD128: .param v128, i32{{$}}
271; SIMD128: .result v128{{$}}
272; SIMD128: i32x4.replace_lane $push0=, $0, 2, $1 # encoding: [0xfd,0x13,0x02]{{$}}
273; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
274define <4 x i32> @replace_v4i32(<4 x i32> %v, i32 %x) {
275  %res = insertelement <4 x i32> %v, i32 %x, i32 2
276  ret <4 x i32> %res
277}
278
279; CHECK-LABEL: build_v4i32:
280; NO-SIMD128-NOT: i32x4
281; SIMD128: .param i32, i32, i32, i32{{$}}
282; SIMD128: .result v128{{$}}
283; SIMD128: i32x4.splat $push0=, $0 # encoding: [0xfd,0x05]
284; SIMD128: i32x4.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x13,0x01]
285; SIMD128: i32x4.replace_lane $push2=, $pop1, 2, $2 # encoding: [0xfd,0x13,0x02]
286; SIMD128: i32x4.replace_lane $push3=, $pop2, 3, $3 # encoding: [0xfd,0x13,0x03]
287; SIMD128: return $pop3 # encoding: [0x0f]
288define <4 x i32> @build_v4i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
289  %t0 = insertelement <4 x i32> undef, i32 %x0, i32 0
290  %t1 = insertelement <4 x i32> %t0, i32 %x1, i32 1
291  %t2 = insertelement <4 x i32> %t1, i32 %x2, i32 2
292  %res = insertelement <4 x i32> %t2, i32 %x3, i32 3
293  ret <4 x i32> %res
294}
295
296; ==============================================================================
297; 2 x i64
298; ==============================================================================
299; CHECK-LABEL: const_v2i64:
300; NO-SIMD128-NOT: i64x2
301; SIMD128-VM-NOT: i64x2
302; SIMD128: .result v128{{$}}
303; SIMD128: v128.const $push0=, 506097522914230528, 1084818905618843912
304; SIMD128-SAME: # encoding: [0xfd,0x00,
305; SIMD128-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
306; SIMD128-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]{{$}}
307define <2 x i64> @const_v2i64() {
308  ret <2 x i64> <i64 506097522914230528, i64 1084818905618843912>
309}
310
311; CHECK-LABEL: splat_v2i64:
312; NO-SIMD128-NOT: i64x2
313; SIMD128-VM-NOT: i64x2
314; SIMD128: .param i64{{$}}
315; SIMD128: .result v128{{$}}
316; SIMD128: i64x2.splat $push0=, $0 # encoding: [0xfd,0x06]{{$}}
317; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
318define <2 x i64> @splat_v2i64(i64 %x) {
319  %t1 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
320  %res = insertelement <2 x i64> %t1, i64 %x, i32 1
321  ret <2 x i64> %res
322}
323
324; CHECK-LABEL: extract_v2i64:
325; NO-SIMD128-NOT: i64x2
326; SIMD128-VM-NOT: i64x2
327; SIMD128: .param v128{{$}}
328; SIMD128: .result i64{{$}}
329; SIMD128: i64x2.extract_lane $push0=, $0, 1 # encoding: [0xfd,0x0e,0x01]{{$}}
330; SIMD128: return $pop0 #
331define i64 @extract_v2i64(<2 x i64> %v) {
332  %elem = extractelement <2 x i64> %v, i64 1
333  ret i64 %elem
334}
335
336; CHECK-LABEL: replace_v2i64:
337; NO-SIMD128-NOT: i64x2
338; SIMD128-VM-NOT: i64x2
339; SIMD128: .param v128, i64{{$}}
340; SIMD128: .result v128{{$}}
341; SIMD128: i64x2.replace_lane $push0=, $0, 0, $1 # encoding: [0xfd,0x14,0x00]{{$}}
342; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
343define <2 x i64> @replace_v2i64(<2 x i64> %v, i64 %x) {
344  %res = insertelement <2 x i64> %v, i64 %x, i32 0
345  ret <2 x i64> %res
346}
347
348; CHECK-LABEL: build_v2i64:
349; NO-SIMD128-NOT: i64x2
350; SIMD128-VM-NOT: i64x2
351; SIMD128: .param i64, i64{{$}}
352; SIMD128: .result v128{{$}}
353; SIMD128: i64x2.splat $push0=, $0 # encoding: [0xfd,0x06]
354; SIMD128: i64x2.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x14,0x01]
355; SIMD128: return $pop1 # encoding: [0x0f]
356define <2 x i64> @build_v2i64(i64 %x0, i64 %x1) {
357  %t0 = insertelement <2 x i64> undef, i64 %x0, i32 0
358  %res = insertelement <2 x i64> %t0, i64 %x1, i32 1
359  ret <2 x i64> %res
360}
361
362; ==============================================================================
363; 4 x f32
364; ==============================================================================
365; CHECK-LABEL: const_v4f32:
366; NO-SIMD128-NOT: f32x4
367; SIMD128: .result v128{{$}}
368; SIMD128: v128.const $push0=,
369; SIMD128-SAME: 0x1.0402p-121, 0x1.0c0a08p-113, 0x1.14121p-105, 0x1.1c1a18p-97
370; SIMD128-SAME: # encoding: [0xfd,0x00,
371; SIMD128-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
372; SIMD128-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]{{$}}
373define <4 x float> @const_v4f32() {
374  ret <4 x float> <float 0x3860402000000000, float 0x38e0c0a080000000,
375                   float 0x3961412100000000, float 0x39e1c1a180000000>
376}
377
378; CHECK-LABEL: splat_v4f32:
379; NO-SIMD128-NOT: f32x4
380; SIMD128: .param f32{{$}}
381; SIMD128: .result v128{{$}}
382; SIMD128: f32x4.splat $push0=, $0 # encoding: [0xfd,0x07]{{$}}
383; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
384define <4 x float> @splat_v4f32(float %x) {
385  %v = insertelement <4 x float> undef, float %x, i32 0
386  %res = shufflevector <4 x float> %v, <4 x float> undef,
387    <4 x i32> <i32 0, i32 0, i32 0, i32 0>
388  ret <4 x float> %res
389}
390
391; CHECK-LABEL: extract_v4f32:
392; NO-SIMD128-NOT: f32x4
393; SIMD128: .param v128{{$}}
394; SIMD128: .result f32{{$}}
395; SIMD128: f32x4.extract_lane $push0=, $0, 3 # encoding: [0xfd,0x0f,0x03]{{$}}
396; SIMD128: return $pop0 #
397define float @extract_v4f32(<4 x float> %v) {
398  %elem = extractelement <4 x float> %v, i32 3
399  ret float %elem
400}
401
402; CHECK-LABEL: replace_v4f32:
403; NO-SIMD128-NOT: f32x4
404; SIMD128: .param v128, f32{{$}}
405; SIMD128: .result v128{{$}}
406; SIMD128: f32x4.replace_lane $push0=, $0, 2, $1 # encoding: [0xfd,0x15,0x02]{{$}}
407; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
408define <4 x float> @replace_v4f32(<4 x float> %v, float %x) {
409  %res = insertelement <4 x float> %v, float %x, i32 2
410  ret <4 x float> %res
411}
412
413; CHECK-LABEL: build_v4f32:
414; NO-SIMD128-NOT: f32x4
415; SIMD128: .param f32, f32, f32, f32{{$}}
416; SIMD128: .result v128{{$}}
417; SIMD128: f32x4.splat $push0=, $0 # encoding: [0xfd,0x07]
418; SIMD128: f32x4.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x15,0x01]
419; SIMD128: f32x4.replace_lane $push2=, $pop1, 2, $2 # encoding: [0xfd,0x15,0x02]
420; SIMD128: f32x4.replace_lane $push3=, $pop2, 3, $3 # encoding: [0xfd,0x15,0x03]
421; SIMD128: return $pop3 # encoding: [0x0f]
422define <4 x float> @build_v4f32(float %x0, float %x1, float %x2, float %x3) {
423  %t0 = insertelement <4 x float> undef, float %x0, i32 0
424  %t1 = insertelement <4 x float> %t0, float %x1, i32 1
425  %t2 = insertelement <4 x float> %t1, float %x2, i32 2
426  %res = insertelement <4 x float> %t2, float %x3, i32 3
427  ret <4 x float> %res
428}
429
430; ==============================================================================
431; 2 x f64
432; ==============================================================================
433; CHECK-LABEL: const_v2f64:
434; NO-SIMD128-NOT: f64x2
435; SIMD128: .result v128{{$}}
436; SIMD128: v128.const $push0=, 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783
437; SIMD128-SAME: # encoding: [0xfd,0x00,
438; SIMD128-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
439; SIMD128-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]{{$}}
440define <2 x double> @const_v2f64() {
441  ret <2 x double> <double 0x0706050403020100, double 0x0F0E0D0C0B0A0908>
442}
443
444; CHECK-LABEL: splat_v2f64:
445; NO-SIMD128-NOT: f64x2
446; SIMD128-VM-NOT: f64x2
447; SIMD128: .param f64{{$}}
448; SIMD128: .result v128{{$}}
449; SIMD128: f64x2.splat $push0=, $0 # encoding: [0xfd,0x08]{{$}}
450; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
451define <2 x double> @splat_v2f64(double %x) {
452  %t1 = insertelement <2 x double> zeroinitializer, double %x, i3 0
453  %res = insertelement <2 x double> %t1, double %x, i32 1
454  ret <2 x double> %res
455}
456
457; CHECK-LABEL: extract_v2f64:
458; NO-SIMD128-NOT: f64x2
459; SIMD128-VM-NOT: f64x2
460; SIMD128: .param v128{{$}}
461; SIMD128: .result f64{{$}}
462; SIMD128: f64x2.extract_lane $push0=, $0, 1 # encoding: [0xfd,0x10,0x01]{{$}}
463; SIMD128: return $pop0 #
464define double @extract_v2f64(<2 x double> %v) {
465  %elem = extractelement <2 x double> %v, i32 1
466  ret double %elem
467}
468
469; CHECK-LABEL: replace_v2f64:
470; NO-SIMD128-NOT: f64x2
471; SIMD128-VM-NOT: f64x2
472; SIMD128: .param v128, f64{{$}}
473; SIMD128: .result v128{{$}}
474; SIMD128: f64x2.replace_lane $push0=, $0, 0, $1 # encoding: [0xfd,0x16,0x00]{{$}}
475; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
476define <2 x double> @replace_v2f64(<2 x double> %v, double %x) {
477  %res = insertelement <2 x double> %v, double %x, i32 0
478  ret <2 x double> %res
479}
480
481; CHECK-LABEL: build_v2f64:
482; NO-SIMD128-NOT: f64x2
483; SIMD128-VM-NOT: f64x2
484; SIMD128: .param f64, f64{{$}}
485; SIMD128: .result v128{{$}}
486; SIMD128: f64x2.splat $push0=, $0 # encoding: [0xfd,0x08]
487; SIMD128: f64x2.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x16,0x01]
488; SIMD128: return $pop1 # encoding: [0x0f]
489define <2 x double> @build_v2f64(double %x0, double %x1) {
490  %t0 = insertelement <2 x double> undef, double %x0, i32 0
491  %res = insertelement <2 x double> %t0, double %x1, i32 1
492  ret <2 x double> %res
493}
494