1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s 2 3; Test that operations that are not supported by SIMD are properly 4; unrolled. 5 6target triple = "wasm32-unknown-unknown" 7 8; ============================================================================== 9; 16 x i8 10; ============================================================================== 11 12; CHECK-LABEL: ctlz_v16i8: 13; CHECK: i8x16.popcnt 14declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) 15define <16 x i8> @ctlz_v16i8(<16 x i8> %x) { 16 %v = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x, i1 false) 17 ret <16 x i8> %v 18} 19 20; CHECK-LABEL: ctlz_v16i8_undef: 21; CHECK: i8x16.popcnt 22define <16 x i8> @ctlz_v16i8_undef(<16 x i8> %x) { 23 %v = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x, i1 true) 24 ret <16 x i8> %v 25} 26 27; CHECK-LABEL: cttz_v16i8: 28; CHECK: i8x16.popcnt 29declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1) 30define <16 x i8> @cttz_v16i8(<16 x i8> %x) { 31 %v = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %x, i1 false) 32 ret <16 x i8> %v 33} 34 35; CHECK-LABEL: cttz_v16i8_undef: 36; CHECK: i8x16.popcnt 37define <16 x i8> @cttz_v16i8_undef(<16 x i8> %x) { 38 %v = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %x, i1 true) 39 ret <16 x i8> %v 40} 41 42; CHECK-LABEL: sdiv_v16i8: 43; CHECK: i32.div_s 44define <16 x i8> @sdiv_v16i8(<16 x i8> %x, <16 x i8> %y) { 45 %v = sdiv <16 x i8> %x, %y 46 ret <16 x i8> %v 47} 48 49; CHECK-LABEL: udiv_v16i8: 50; CHECK: i32.div_u 51define <16 x i8> @udiv_v16i8(<16 x i8> %x, <16 x i8> %y) { 52 %v = udiv <16 x i8> %x, %y 53 ret <16 x i8> %v 54} 55 56; CHECK-LABEL: srem_v16i8: 57; CHECK: i32.rem_s 58define <16 x i8> @srem_v16i8(<16 x i8> %x, <16 x i8> %y) { 59 %v = srem <16 x i8> %x, %y 60 ret <16 x i8> %v 61} 62 63; CHECK-LABEL: urem_v16i8: 64; CHECK: i32.rem_u 65define <16 x i8> @urem_v16i8(<16 x i8> %x, <16 x i8> %y) { 66 %v = urem <16 x i8> %x, %y 67 ret <16 x i8> %v 68} 69 70; CHECK-LABEL: rotl_v16i8: 71; Note: expansion does not use i32.rotl 72; CHECK: i32.shl 73declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 74define <16 x i8> @rotl_v16i8(<16 x i8> %x, <16 x i8> %y) { 75 %v = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> %y) 76 ret <16 x i8> %v 77} 78 79; CHECK-LABEL: rotr_v16i8: 80; Note: expansion does not use i32.rotr 81; CHECK: i32.shr_u 82declare <16 x i8> @llvm.fshr.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 83define <16 x i8> @rotr_v16i8(<16 x i8> %x, <16 x i8> %y) { 84 %v = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> %y) 85 ret <16 x i8> %v 86} 87 88; ============================================================================== 89; 8 x i16 90; ============================================================================== 91 92; CHECK-LABEL: ctlz_v8i16: 93; CHECK: i32.clz 94declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) 95define <8 x i16> @ctlz_v8i16(<8 x i16> %x) { 96 %v = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %x, i1 false) 97 ret <8 x i16> %v 98} 99 100; CHECK-LABEL: ctlz_v8i16_undef: 101; CHECK: i32.clz 102define <8 x i16> @ctlz_v8i16_undef(<8 x i16> %x) { 103 %v = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %x, i1 true) 104 ret <8 x i16> %v 105} 106 107; CHECK-LABEL: cttz_v8i16: 108; CHECK: i32.ctz 109declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1) 110define <8 x i16> @cttz_v8i16(<8 x i16> %x) { 111 %v = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %x, i1 false) 112 ret <8 x i16> %v 113} 114 115; CHECK-LABEL: cttz_v8i16_undef: 116; CHECK: i32.ctz 117define <8 x i16> @cttz_v8i16_undef(<8 x i16> %x) { 118 %v = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %x, i1 true) 119 ret <8 x i16> %v 120} 121 122; CHECK-LABEL: ctpop_v8i16: 123; Note: expansion does not use i32.popcnt 124; CHECK: v128.and 125declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) 126define <8 x i16> @ctpop_v8i16(<8 x i16> %x) { 127 %v = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %x) 128 ret <8 x i16> %v 129} 130 131; CHECK-LABEL: sdiv_v8i16: 132; CHECK: i32.div_s 133define <8 x i16> @sdiv_v8i16(<8 x i16> %x, <8 x i16> %y) { 134 %v = sdiv <8 x i16> %x, %y 135 ret <8 x i16> %v 136} 137 138; CHECK-LABEL: udiv_v8i16: 139; CHECK: i32.div_u 140define <8 x i16> @udiv_v8i16(<8 x i16> %x, <8 x i16> %y) { 141 %v = udiv <8 x i16> %x, %y 142 ret <8 x i16> %v 143} 144 145; CHECK-LABEL: srem_v8i16: 146; CHECK: i32.rem_s 147define <8 x i16> @srem_v8i16(<8 x i16> %x, <8 x i16> %y) { 148 %v = srem <8 x i16> %x, %y 149 ret <8 x i16> %v 150} 151 152; CHECK-LABEL: urem_v8i16: 153; CHECK: i32.rem_u 154define <8 x i16> @urem_v8i16(<8 x i16> %x, <8 x i16> %y) { 155 %v = urem <8 x i16> %x, %y 156 ret <8 x i16> %v 157} 158 159; CHECK-LABEL: rotl_v8i16: 160; Note: expansion does not use i32.rotl 161; CHECK: i32.shl 162declare <8 x i16> @llvm.fshl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 163define <8 x i16> @rotl_v8i16(<8 x i16> %x, <8 x i16> %y) { 164 %v = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %x, <8 x i16> %x, <8 x i16> %y) 165 ret <8 x i16> %v 166} 167 168; CHECK-LABEL: rotr_v8i16: 169; Note: expansion does not use i32.rotr 170; CHECK: i32.shr_u 171declare <8 x i16> @llvm.fshr.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 172define <8 x i16> @rotr_v8i16(<8 x i16> %x, <8 x i16> %y) { 173 %v = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %x, <8 x i16> %x, <8 x i16> %y) 174 ret <8 x i16> %v 175} 176 177; ============================================================================== 178; 4 x i32 179; ============================================================================== 180 181; CHECK-LABEL: ctlz_v4i32: 182; CHECK: i32.clz 183declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) 184define <4 x i32> @ctlz_v4i32(<4 x i32> %x) { 185 %v = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %x, i1 false) 186 ret <4 x i32> %v 187} 188 189; CHECK-LABEL: ctlz_v4i32_undef: 190; CHECK: i32.clz 191define <4 x i32> @ctlz_v4i32_undef(<4 x i32> %x) { 192 %v = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %x, i1 true) 193 ret <4 x i32> %v 194} 195 196; CHECK-LABEL: cttz_v4i32: 197; CHECK: i32.ctz 198declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) 199define <4 x i32> @cttz_v4i32(<4 x i32> %x) { 200 %v = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %x, i1 false) 201 ret <4 x i32> %v 202} 203 204; CHECK-LABEL: cttz_v4i32_undef: 205; CHECK: i32.ctz 206define <4 x i32> @cttz_v4i32_undef(<4 x i32> %x) { 207 %v = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %x, i1 true) 208 ret <4 x i32> %v 209} 210 211; CHECK-LABEL: ctpop_v4i32: 212; Note: expansion does not use i32.popcnt 213; CHECK: v128.and 214declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) 215define <4 x i32> @ctpop_v4i32(<4 x i32> %x) { 216 %v = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %x) 217 ret <4 x i32> %v 218} 219 220; CHECK-LABEL: sdiv_v4i32: 221; CHECK: i32.div_s 222define <4 x i32> @sdiv_v4i32(<4 x i32> %x, <4 x i32> %y) { 223 %v = sdiv <4 x i32> %x, %y 224 ret <4 x i32> %v 225} 226 227; CHECK-LABEL: udiv_v4i32: 228; CHECK: i32.div_u 229define <4 x i32> @udiv_v4i32(<4 x i32> %x, <4 x i32> %y) { 230 %v = udiv <4 x i32> %x, %y 231 ret <4 x i32> %v 232} 233 234; CHECK-LABEL: srem_v4i32: 235; CHECK: i32.rem_s 236define <4 x i32> @srem_v4i32(<4 x i32> %x, <4 x i32> %y) { 237 %v = srem <4 x i32> %x, %y 238 ret <4 x i32> %v 239} 240 241; CHECK-LABEL: urem_v4i32: 242; CHECK: i32.rem_u 243define <4 x i32> @urem_v4i32(<4 x i32> %x, <4 x i32> %y) { 244 %v = urem <4 x i32> %x, %y 245 ret <4 x i32> %v 246} 247 248; CHECK-LABEL: rotl_v4i32: 249; Note: expansion does not use i32.rotl 250; CHECK: i32.shl 251declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 252define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %y) { 253 %v = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %y) 254 ret <4 x i32> %v 255} 256 257; CHECK-LABEL: rotr_v4i32: 258; Note: expansion does not use i32.rotr 259; CHECK: i32.shr_u 260declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 261define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %y) { 262 %v = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %y) 263 ret <4 x i32> %v 264} 265 266; ============================================================================== 267; 2 x i64 268; ============================================================================== 269 270; CHECK-LABEL: ctlz_v2i64: 271; CHECK: i64.clz 272declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) 273define <2 x i64> @ctlz_v2i64(<2 x i64> %x) { 274 %v = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %x, i1 false) 275 ret <2 x i64> %v 276} 277 278; CHECK-LABEL: ctlz_v2i64_undef: 279; CHECK: i64.clz 280define <2 x i64> @ctlz_v2i64_undef(<2 x i64> %x) { 281 %v = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %x, i1 true) 282 ret <2 x i64> %v 283} 284 285; CHECK-LABEL: cttz_v2i64: 286; CHECK: i64.ctz 287declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1) 288define <2 x i64> @cttz_v2i64(<2 x i64> %x) { 289 %v = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %x, i1 false) 290 ret <2 x i64> %v 291} 292 293; CHECK-LABEL: cttz_v2i64_undef: 294; CHECK: i64.ctz 295define <2 x i64> @cttz_v2i64_undef(<2 x i64> %x) { 296 %v = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %x, i1 true) 297 ret <2 x i64> %v 298} 299 300; CHECK-LABEL: ctpop_v2i64: 301; Note: expansion does not use i64.popcnt 302; CHECK: v128.and 303declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) 304define <2 x i64> @ctpop_v2i64(<2 x i64> %x) { 305 %v = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %x) 306 ret <2 x i64> %v 307} 308 309; CHECK-LABEL: sdiv_v2i64: 310; CHECK: i64.div_s 311define <2 x i64> @sdiv_v2i64(<2 x i64> %x, <2 x i64> %y) { 312 %v = sdiv <2 x i64> %x, %y 313 ret <2 x i64> %v 314} 315 316; CHECK-LABEL: udiv_v2i64: 317; CHECK: i64.div_u 318define <2 x i64> @udiv_v2i64(<2 x i64> %x, <2 x i64> %y) { 319 %v = udiv <2 x i64> %x, %y 320 ret <2 x i64> %v 321} 322 323; CHECK-LABEL: srem_v2i64: 324; CHECK: i64.rem_s 325define <2 x i64> @srem_v2i64(<2 x i64> %x, <2 x i64> %y) { 326 %v = srem <2 x i64> %x, %y 327 ret <2 x i64> %v 328} 329 330; CHECK-LABEL: urem_v2i64: 331; CHECK: i64.rem_u 332define <2 x i64> @urem_v2i64(<2 x i64> %x, <2 x i64> %y) { 333 %v = urem <2 x i64> %x, %y 334 ret <2 x i64> %v 335} 336 337; CHECK-LABEL: rotl_v2i64: 338; Note: expansion does not use i64.rotl 339; CHECK: i64.shl 340declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 341define <2 x i64> @rotl_v2i64(<2 x i64> %x, <2 x i64> %y) { 342 %v = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %x, <2 x i64> %x, <2 x i64> %y) 343 ret <2 x i64> %v 344} 345 346; CHECK-LABEL: rotr_v2i64: 347; Note: expansion does not use i64.rotr 348; CHECK: i64.shr_u 349declare <2 x i64> @llvm.fshr.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 350define <2 x i64> @rotr_v2i64(<2 x i64> %x, <2 x i64> %y) { 351 %v = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %x, <2 x i64> %x, <2 x i64> %y) 352 ret <2 x i64> %v 353} 354 355; ============================================================================== 356; 4 x f32 357; ============================================================================== 358 359; CHECK-LABEL: copysign_v4f32: 360; CHECK: f32.copysign 361declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>) 362define <4 x float> @copysign_v4f32(<4 x float> %x, <4 x float> %y) { 363 %v = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %y) 364 ret <4 x float> %v 365} 366 367; CHECK-LABEL: sin_v4f32: 368; CHECK: call $push[[L:[0-9]+]]=, sinf 369declare <4 x float> @llvm.sin.v4f32(<4 x float>) 370define <4 x float> @sin_v4f32(<4 x float> %x) { 371 %v = call <4 x float> @llvm.sin.v4f32(<4 x float> %x) 372 ret <4 x float> %v 373} 374 375; CHECK-LABEL: cos_v4f32: 376; CHECK: call $push[[L:[0-9]+]]=, cosf 377declare <4 x float> @llvm.cos.v4f32(<4 x float>) 378define <4 x float> @cos_v4f32(<4 x float> %x) { 379 %v = call <4 x float> @llvm.cos.v4f32(<4 x float> %x) 380 ret <4 x float> %v 381} 382 383; CHECK-LABEL: powi_v4f32: 384; CHECK: call $push[[L:[0-9]+]]=, __powisf2 385declare <4 x float> @llvm.powi.v4f32.i32(<4 x float>, i32) 386define <4 x float> @powi_v4f32(<4 x float> %x, i32 %y) { 387 %v = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> %x, i32 %y) 388 ret <4 x float> %v 389} 390 391; CHECK-LABEL: pow_v4f32: 392; CHECK: call $push[[L:[0-9]+]]=, powf 393declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) 394define <4 x float> @pow_v4f32(<4 x float> %x, <4 x float> %y) { 395 %v = call <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> %y) 396 ret <4 x float> %v 397} 398 399; CHECK-LABEL: log_v4f32: 400; CHECK: call $push[[L:[0-9]+]]=, logf 401declare <4 x float> @llvm.log.v4f32(<4 x float>) 402define <4 x float> @log_v4f32(<4 x float> %x) { 403 %v = call <4 x float> @llvm.log.v4f32(<4 x float> %x) 404 ret <4 x float> %v 405} 406 407; CHECK-LABEL: log2_v4f32: 408; CHECK: call $push[[L:[0-9]+]]=, log2f 409declare <4 x float> @llvm.log2.v4f32(<4 x float>) 410define <4 x float> @log2_v4f32(<4 x float> %x) { 411 %v = call <4 x float> @llvm.log2.v4f32(<4 x float> %x) 412 ret <4 x float> %v 413} 414 415; CHECK-LABEL: log10_v4f32: 416; CHECK: call $push[[L:[0-9]+]]=, log10f 417declare <4 x float> @llvm.log10.v4f32(<4 x float>) 418define <4 x float> @log10_v4f32(<4 x float> %x) { 419 %v = call <4 x float> @llvm.log10.v4f32(<4 x float> %x) 420 ret <4 x float> %v 421} 422 423; CHECK-LABEL: exp_v4f32: 424; CHECK: call $push[[L:[0-9]+]]=, expf 425declare <4 x float> @llvm.exp.v4f32(<4 x float>) 426define <4 x float> @exp_v4f32(<4 x float> %x) { 427 %v = call <4 x float> @llvm.exp.v4f32(<4 x float> %x) 428 ret <4 x float> %v 429} 430 431; CHECK-LABEL: exp2_v4f32: 432; CHECK: call $push[[L:[0-9]+]]=, exp2f 433declare <4 x float> @llvm.exp2.v4f32(<4 x float>) 434define <4 x float> @exp2_v4f32(<4 x float> %x) { 435 %v = call <4 x float> @llvm.exp2.v4f32(<4 x float> %x) 436 ret <4 x float> %v 437} 438 439; CHECK-LABEL: rint_v4f32: 440; CHECK: f32.nearest 441declare <4 x float> @llvm.rint.v4f32(<4 x float>) 442define <4 x float> @rint_v4f32(<4 x float> %x) { 443 %v = call <4 x float> @llvm.rint.v4f32(<4 x float> %x) 444 ret <4 x float> %v 445} 446 447; CHECK-LABEL: round_v4f32: 448; CHECK: call $push[[L:[0-9]+]]=, roundf 449declare <4 x float> @llvm.round.v4f32(<4 x float>) 450define <4 x float> @round_v4f32(<4 x float> %x) { 451 %v = call <4 x float> @llvm.round.v4f32(<4 x float> %x) 452 ret <4 x float> %v 453} 454 455; ============================================================================== 456; 2 x f64 457; ============================================================================== 458 459; CHECK-LABEL: copysign_v2f64: 460; CHECK: f64.copysign 461declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) 462define <2 x double> @copysign_v2f64(<2 x double> %x, <2 x double> %y) { 463 %v = call <2 x double> @llvm.copysign.v2f64(<2 x double> %x, <2 x double> %y) 464 ret <2 x double> %v 465} 466 467; CHECK-LABEL: sin_v2f64: 468; CHECK: call $push[[L:[0-9]+]]=, sin 469declare <2 x double> @llvm.sin.v2f64(<2 x double>) 470define <2 x double> @sin_v2f64(<2 x double> %x) { 471 %v = call <2 x double> @llvm.sin.v2f64(<2 x double> %x) 472 ret <2 x double> %v 473} 474 475; CHECK-LABEL: cos_v2f64: 476; CHECK: call $push[[L:[0-9]+]]=, cos 477declare <2 x double> @llvm.cos.v2f64(<2 x double>) 478define <2 x double> @cos_v2f64(<2 x double> %x) { 479 %v = call <2 x double> @llvm.cos.v2f64(<2 x double> %x) 480 ret <2 x double> %v 481} 482 483; CHECK-LABEL: powi_v2f64: 484; CHECK: call $push[[L:[0-9]+]]=, __powidf2 485declare <2 x double> @llvm.powi.v2f64.i32(<2 x double>, i32) 486define <2 x double> @powi_v2f64(<2 x double> %x, i32 %y) { 487 %v = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> %x, i32 %y) 488 ret <2 x double> %v 489} 490 491; CHECK-LABEL: pow_v2f64: 492; CHECK: call $push[[L:[0-9]+]]=, pow 493declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) 494define <2 x double> @pow_v2f64(<2 x double> %x, <2 x double> %y) { 495 %v = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> %y) 496 ret <2 x double> %v 497} 498 499; CHECK-LABEL: log_v2f64: 500; CHECK: call $push[[L:[0-9]+]]=, log 501declare <2 x double> @llvm.log.v2f64(<2 x double>) 502define <2 x double> @log_v2f64(<2 x double> %x) { 503 %v = call <2 x double> @llvm.log.v2f64(<2 x double> %x) 504 ret <2 x double> %v 505} 506 507; CHECK-LABEL: log2_v2f64: 508; CHECK: call $push[[L:[0-9]+]]=, log2 509declare <2 x double> @llvm.log2.v2f64(<2 x double>) 510define <2 x double> @log2_v2f64(<2 x double> %x) { 511 %v = call <2 x double> @llvm.log2.v2f64(<2 x double> %x) 512 ret <2 x double> %v 513} 514 515; CHECK-LABEL: log10_v2f64: 516; CHECK: call $push[[L:[0-9]+]]=, log10 517declare <2 x double> @llvm.log10.v2f64(<2 x double>) 518define <2 x double> @log10_v2f64(<2 x double> %x) { 519 %v = call <2 x double> @llvm.log10.v2f64(<2 x double> %x) 520 ret <2 x double> %v 521} 522 523; CHECK-LABEL: exp_v2f64: 524; CHECK: call $push[[L:[0-9]+]]=, exp 525declare <2 x double> @llvm.exp.v2f64(<2 x double>) 526define <2 x double> @exp_v2f64(<2 x double> %x) { 527 %v = call <2 x double> @llvm.exp.v2f64(<2 x double> %x) 528 ret <2 x double> %v 529} 530 531; CHECK-LABEL: exp2_v2f64: 532; CHECK: call $push[[L:[0-9]+]]=, exp2 533declare <2 x double> @llvm.exp2.v2f64(<2 x double>) 534define <2 x double> @exp2_v2f64(<2 x double> %x) { 535 %v = call <2 x double> @llvm.exp2.v2f64(<2 x double> %x) 536 ret <2 x double> %v 537} 538 539; CHECK-LABEL: rint_v2f64: 540; CHECK: f64.nearest 541declare <2 x double> @llvm.rint.v2f64(<2 x double>) 542define <2 x double> @rint_v2f64(<2 x double> %x) { 543 %v = call <2 x double> @llvm.rint.v2f64(<2 x double> %x) 544 ret <2 x double> %v 545} 546 547; CHECK-LABEL: round_v2f64: 548; CHECK: call $push[[L:[0-9]+]]=, round 549declare <2 x double> @llvm.round.v2f64(<2 x double>) 550define <2 x double> @round_v2f64(<2 x double> %x) { 551 %v = call <2 x double> @llvm.round.v2f64(<2 x double> %x) 552 ret <2 x double> %v 553} 554