1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s 2 3; Test that operations that are not supported by SIMD are properly 4; unrolled. 5 6target triple = "wasm32-unknown-unknown" 7 8; ============================================================================== 9; 16 x i8 10; ============================================================================== 11 12; CHECK-LABEL: ctlz_v16i8: 13; CHECK: i8x16.popcnt 14declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) 15define <16 x i8> @ctlz_v16i8(<16 x i8> %x) { 16 %v = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x, i1 false) 17 ret <16 x i8> %v 18} 19 20; CHECK-LABEL: ctlz_v16i8_undef: 21; CHECK: i8x16.popcnt 22define <16 x i8> @ctlz_v16i8_undef(<16 x i8> %x) { 23 %v = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x, i1 true) 24 ret <16 x i8> %v 25} 26 27; CHECK-LABEL: cttz_v16i8: 28; CHECK: i8x16.popcnt 29declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1) 30define <16 x i8> @cttz_v16i8(<16 x i8> %x) { 31 %v = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %x, i1 false) 32 ret <16 x i8> %v 33} 34 35; CHECK-LABEL: cttz_v16i8_undef: 36; CHECK: i8x16.popcnt 37define <16 x i8> @cttz_v16i8_undef(<16 x i8> %x) { 38 %v = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %x, i1 true) 39 ret <16 x i8> %v 40} 41 42; CHECK-LABEL: sdiv_v16i8: 43; CHECK: i32.div_s 44define <16 x i8> @sdiv_v16i8(<16 x i8> %x, <16 x i8> %y) { 45 %v = sdiv <16 x i8> %x, %y 46 ret <16 x i8> %v 47} 48 49; CHECK-LABEL: udiv_v16i8: 50; CHECK: i32.div_u 51define <16 x i8> @udiv_v16i8(<16 x i8> %x, <16 x i8> %y) { 52 %v = udiv <16 x i8> %x, %y 53 ret <16 x i8> %v 54} 55 56; CHECK-LABEL: srem_v16i8: 57; CHECK: i32.rem_s 58define <16 x i8> @srem_v16i8(<16 x i8> %x, <16 x i8> %y) { 59 %v = srem <16 x i8> %x, %y 60 ret <16 x i8> %v 61} 62 63; CHECK-LABEL: urem_v16i8: 64; CHECK: i32.rem_u 65define <16 x i8> @urem_v16i8(<16 x i8> %x, <16 x i8> %y) { 66 %v = urem <16 x i8> %x, %y 67 ret <16 x i8> %v 68} 69 70; CHECK-LABEL: rotl_v16i8: 71; Note: expansion does not use i32.rotl 72; CHECK: i32.shl 73declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 74define <16 x i8> @rotl_v16i8(<16 x i8> %x, <16 x i8> %y) { 75 %v = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> %y) 76 ret <16 x i8> %v 77} 78 79; CHECK-LABEL: rotr_v16i8: 80; Note: expansion does not use i32.rotr 81; CHECK: i32.shr_u 82declare <16 x i8> @llvm.fshr.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 83define <16 x i8> @rotr_v16i8(<16 x i8> %x, <16 x i8> %y) { 84 %v = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> %y) 85 ret <16 x i8> %v 86} 87 88; ============================================================================== 89; 8 x i16 90; ============================================================================== 91 92; CHECK-LABEL: ctlz_v8i16: 93; CHECK: i32.clz 94declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) 95define <8 x i16> @ctlz_v8i16(<8 x i16> %x) { 96 %v = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %x, i1 false) 97 ret <8 x i16> %v 98} 99 100; CHECK-LABEL: ctlz_v8i16_undef: 101; CHECK: i32.clz 102define <8 x i16> @ctlz_v8i16_undef(<8 x i16> %x) { 103 %v = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %x, i1 true) 104 ret <8 x i16> %v 105} 106 107; CHECK-LABEL: cttz_v8i16: 108; CHECK: i32.ctz 109declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1) 110define <8 x i16> @cttz_v8i16(<8 x i16> %x) { 111 %v = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %x, i1 false) 112 ret <8 x i16> %v 113} 114 115; CHECK-LABEL: cttz_v8i16_undef: 116; CHECK: i32.ctz 117define <8 x i16> @cttz_v8i16_undef(<8 x i16> %x) { 118 %v = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %x, i1 true) 119 ret <8 x i16> %v 120} 121 122; CHECK-LABEL: ctpop_v8i16: 123; CHECK: i32.popcnt 124declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) 125define <8 x i16> @ctpop_v8i16(<8 x i16> %x) { 126 %v = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %x) 127 ret <8 x i16> %v 128} 129 130; CHECK-LABEL: sdiv_v8i16: 131; CHECK: i32.div_s 132define <8 x i16> @sdiv_v8i16(<8 x i16> %x, <8 x i16> %y) { 133 %v = sdiv <8 x i16> %x, %y 134 ret <8 x i16> %v 135} 136 137; CHECK-LABEL: udiv_v8i16: 138; CHECK: i32.div_u 139define <8 x i16> @udiv_v8i16(<8 x i16> %x, <8 x i16> %y) { 140 %v = udiv <8 x i16> %x, %y 141 ret <8 x i16> %v 142} 143 144; CHECK-LABEL: srem_v8i16: 145; CHECK: i32.rem_s 146define <8 x i16> @srem_v8i16(<8 x i16> %x, <8 x i16> %y) { 147 %v = srem <8 x i16> %x, %y 148 ret <8 x i16> %v 149} 150 151; CHECK-LABEL: urem_v8i16: 152; CHECK: i32.rem_u 153define <8 x i16> @urem_v8i16(<8 x i16> %x, <8 x i16> %y) { 154 %v = urem <8 x i16> %x, %y 155 ret <8 x i16> %v 156} 157 158; CHECK-LABEL: rotl_v8i16: 159; Note: expansion does not use i32.rotl 160; CHECK: i32.shl 161declare <8 x i16> @llvm.fshl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 162define <8 x i16> @rotl_v8i16(<8 x i16> %x, <8 x i16> %y) { 163 %v = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %x, <8 x i16> %x, <8 x i16> %y) 164 ret <8 x i16> %v 165} 166 167; CHECK-LABEL: rotr_v8i16: 168; Note: expansion does not use i32.rotr 169; CHECK: i32.shr_u 170declare <8 x i16> @llvm.fshr.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 171define <8 x i16> @rotr_v8i16(<8 x i16> %x, <8 x i16> %y) { 172 %v = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %x, <8 x i16> %x, <8 x i16> %y) 173 ret <8 x i16> %v 174} 175 176; ============================================================================== 177; 4 x i32 178; ============================================================================== 179 180; CHECK-LABEL: ctlz_v4i32: 181; CHECK: i32.clz 182declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) 183define <4 x i32> @ctlz_v4i32(<4 x i32> %x) { 184 %v = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %x, i1 false) 185 ret <4 x i32> %v 186} 187 188; CHECK-LABEL: ctlz_v4i32_undef: 189; CHECK: i32.clz 190define <4 x i32> @ctlz_v4i32_undef(<4 x i32> %x) { 191 %v = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %x, i1 true) 192 ret <4 x i32> %v 193} 194 195; CHECK-LABEL: cttz_v4i32: 196; CHECK: i32.ctz 197declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) 198define <4 x i32> @cttz_v4i32(<4 x i32> %x) { 199 %v = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %x, i1 false) 200 ret <4 x i32> %v 201} 202 203; CHECK-LABEL: cttz_v4i32_undef: 204; CHECK: i32.ctz 205define <4 x i32> @cttz_v4i32_undef(<4 x i32> %x) { 206 %v = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %x, i1 true) 207 ret <4 x i32> %v 208} 209 210; CHECK-LABEL: ctpop_v4i32: 211; CHECK: i32.popcnt 212declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) 213define <4 x i32> @ctpop_v4i32(<4 x i32> %x) { 214 %v = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %x) 215 ret <4 x i32> %v 216} 217 218; CHECK-LABEL: sdiv_v4i32: 219; CHECK: i32.div_s 220define <4 x i32> @sdiv_v4i32(<4 x i32> %x, <4 x i32> %y) { 221 %v = sdiv <4 x i32> %x, %y 222 ret <4 x i32> %v 223} 224 225; CHECK-LABEL: udiv_v4i32: 226; CHECK: i32.div_u 227define <4 x i32> @udiv_v4i32(<4 x i32> %x, <4 x i32> %y) { 228 %v = udiv <4 x i32> %x, %y 229 ret <4 x i32> %v 230} 231 232; CHECK-LABEL: srem_v4i32: 233; CHECK: i32.rem_s 234define <4 x i32> @srem_v4i32(<4 x i32> %x, <4 x i32> %y) { 235 %v = srem <4 x i32> %x, %y 236 ret <4 x i32> %v 237} 238 239; CHECK-LABEL: urem_v4i32: 240; CHECK: i32.rem_u 241define <4 x i32> @urem_v4i32(<4 x i32> %x, <4 x i32> %y) { 242 %v = urem <4 x i32> %x, %y 243 ret <4 x i32> %v 244} 245 246; CHECK-LABEL: rotl_v4i32: 247; Note: expansion does not use i32.rotl 248; CHECK: i32.shl 249declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 250define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %y) { 251 %v = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %y) 252 ret <4 x i32> %v 253} 254 255; CHECK-LABEL: rotr_v4i32: 256; Note: expansion does not use i32.rotr 257; CHECK: i32.shr_u 258declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 259define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %y) { 260 %v = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %y) 261 ret <4 x i32> %v 262} 263 264; ============================================================================== 265; 2 x i64 266; ============================================================================== 267 268; CHECK-LABEL: ctlz_v2i64: 269; CHECK: i64.clz 270declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) 271define <2 x i64> @ctlz_v2i64(<2 x i64> %x) { 272 %v = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %x, i1 false) 273 ret <2 x i64> %v 274} 275 276; CHECK-LABEL: ctlz_v2i64_undef: 277; CHECK: i64.clz 278define <2 x i64> @ctlz_v2i64_undef(<2 x i64> %x) { 279 %v = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %x, i1 true) 280 ret <2 x i64> %v 281} 282 283; CHECK-LABEL: cttz_v2i64: 284; CHECK: i64.ctz 285declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1) 286define <2 x i64> @cttz_v2i64(<2 x i64> %x) { 287 %v = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %x, i1 false) 288 ret <2 x i64> %v 289} 290 291; CHECK-LABEL: cttz_v2i64_undef: 292; CHECK: i64.ctz 293define <2 x i64> @cttz_v2i64_undef(<2 x i64> %x) { 294 %v = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %x, i1 true) 295 ret <2 x i64> %v 296} 297 298; CHECK-LABEL: ctpop_v2i64: 299; CHECK: i64.popcnt 300declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) 301define <2 x i64> @ctpop_v2i64(<2 x i64> %x) { 302 %v = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %x) 303 ret <2 x i64> %v 304} 305 306; CHECK-LABEL: sdiv_v2i64: 307; CHECK: i64.div_s 308define <2 x i64> @sdiv_v2i64(<2 x i64> %x, <2 x i64> %y) { 309 %v = sdiv <2 x i64> %x, %y 310 ret <2 x i64> %v 311} 312 313; CHECK-LABEL: udiv_v2i64: 314; CHECK: i64.div_u 315define <2 x i64> @udiv_v2i64(<2 x i64> %x, <2 x i64> %y) { 316 %v = udiv <2 x i64> %x, %y 317 ret <2 x i64> %v 318} 319 320; CHECK-LABEL: srem_v2i64: 321; CHECK: i64.rem_s 322define <2 x i64> @srem_v2i64(<2 x i64> %x, <2 x i64> %y) { 323 %v = srem <2 x i64> %x, %y 324 ret <2 x i64> %v 325} 326 327; CHECK-LABEL: urem_v2i64: 328; CHECK: i64.rem_u 329define <2 x i64> @urem_v2i64(<2 x i64> %x, <2 x i64> %y) { 330 %v = urem <2 x i64> %x, %y 331 ret <2 x i64> %v 332} 333 334; CHECK-LABEL: rotl_v2i64: 335; Note: expansion does not use i64.rotl 336; CHECK: i64.shl 337declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 338define <2 x i64> @rotl_v2i64(<2 x i64> %x, <2 x i64> %y) { 339 %v = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %x, <2 x i64> %x, <2 x i64> %y) 340 ret <2 x i64> %v 341} 342 343; CHECK-LABEL: rotr_v2i64: 344; Note: expansion does not use i64.rotr 345; CHECK: i64.shr_u 346declare <2 x i64> @llvm.fshr.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 347define <2 x i64> @rotr_v2i64(<2 x i64> %x, <2 x i64> %y) { 348 %v = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %x, <2 x i64> %x, <2 x i64> %y) 349 ret <2 x i64> %v 350} 351 352; ============================================================================== 353; 4 x f32 354; ============================================================================== 355 356; CHECK-LABEL: copysign_v4f32: 357; CHECK: f32.copysign 358declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>) 359define <4 x float> @copysign_v4f32(<4 x float> %x, <4 x float> %y) { 360 %v = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %y) 361 ret <4 x float> %v 362} 363 364; CHECK-LABEL: sin_v4f32: 365; CHECK: call $push[[L:[0-9]+]]=, sinf 366declare <4 x float> @llvm.sin.v4f32(<4 x float>) 367define <4 x float> @sin_v4f32(<4 x float> %x) { 368 %v = call <4 x float> @llvm.sin.v4f32(<4 x float> %x) 369 ret <4 x float> %v 370} 371 372; CHECK-LABEL: cos_v4f32: 373; CHECK: call $push[[L:[0-9]+]]=, cosf 374declare <4 x float> @llvm.cos.v4f32(<4 x float>) 375define <4 x float> @cos_v4f32(<4 x float> %x) { 376 %v = call <4 x float> @llvm.cos.v4f32(<4 x float> %x) 377 ret <4 x float> %v 378} 379 380; CHECK-LABEL: powi_v4f32: 381; CHECK: call $push[[L:[0-9]+]]=, __powisf2 382declare <4 x float> @llvm.powi.v4f32.i32(<4 x float>, i32) 383define <4 x float> @powi_v4f32(<4 x float> %x, i32 %y) { 384 %v = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> %x, i32 %y) 385 ret <4 x float> %v 386} 387 388; CHECK-LABEL: pow_v4f32: 389; CHECK: call $push[[L:[0-9]+]]=, powf 390declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) 391define <4 x float> @pow_v4f32(<4 x float> %x, <4 x float> %y) { 392 %v = call <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> %y) 393 ret <4 x float> %v 394} 395 396; CHECK-LABEL: log_v4f32: 397; CHECK: call $push[[L:[0-9]+]]=, logf 398declare <4 x float> @llvm.log.v4f32(<4 x float>) 399define <4 x float> @log_v4f32(<4 x float> %x) { 400 %v = call <4 x float> @llvm.log.v4f32(<4 x float> %x) 401 ret <4 x float> %v 402} 403 404; CHECK-LABEL: log2_v4f32: 405; CHECK: call $push[[L:[0-9]+]]=, log2f 406declare <4 x float> @llvm.log2.v4f32(<4 x float>) 407define <4 x float> @log2_v4f32(<4 x float> %x) { 408 %v = call <4 x float> @llvm.log2.v4f32(<4 x float> %x) 409 ret <4 x float> %v 410} 411 412; CHECK-LABEL: log10_v4f32: 413; CHECK: call $push[[L:[0-9]+]]=, log10f 414declare <4 x float> @llvm.log10.v4f32(<4 x float>) 415define <4 x float> @log10_v4f32(<4 x float> %x) { 416 %v = call <4 x float> @llvm.log10.v4f32(<4 x float> %x) 417 ret <4 x float> %v 418} 419 420; CHECK-LABEL: exp_v4f32: 421; CHECK: call $push[[L:[0-9]+]]=, expf 422declare <4 x float> @llvm.exp.v4f32(<4 x float>) 423define <4 x float> @exp_v4f32(<4 x float> %x) { 424 %v = call <4 x float> @llvm.exp.v4f32(<4 x float> %x) 425 ret <4 x float> %v 426} 427 428; CHECK-LABEL: exp2_v4f32: 429; CHECK: call $push[[L:[0-9]+]]=, exp2f 430declare <4 x float> @llvm.exp2.v4f32(<4 x float>) 431define <4 x float> @exp2_v4f32(<4 x float> %x) { 432 %v = call <4 x float> @llvm.exp2.v4f32(<4 x float> %x) 433 ret <4 x float> %v 434} 435 436; CHECK-LABEL: rint_v4f32: 437; CHECK: f32.nearest 438declare <4 x float> @llvm.rint.v4f32(<4 x float>) 439define <4 x float> @rint_v4f32(<4 x float> %x) { 440 %v = call <4 x float> @llvm.rint.v4f32(<4 x float> %x) 441 ret <4 x float> %v 442} 443 444; CHECK-LABEL: round_v4f32: 445; CHECK: call $push[[L:[0-9]+]]=, roundf 446declare <4 x float> @llvm.round.v4f32(<4 x float>) 447define <4 x float> @round_v4f32(<4 x float> %x) { 448 %v = call <4 x float> @llvm.round.v4f32(<4 x float> %x) 449 ret <4 x float> %v 450} 451 452; ============================================================================== 453; 2 x f64 454; ============================================================================== 455 456; CHECK-LABEL: copysign_v2f64: 457; CHECK: f64.copysign 458declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) 459define <2 x double> @copysign_v2f64(<2 x double> %x, <2 x double> %y) { 460 %v = call <2 x double> @llvm.copysign.v2f64(<2 x double> %x, <2 x double> %y) 461 ret <2 x double> %v 462} 463 464; CHECK-LABEL: sin_v2f64: 465; CHECK: call $push[[L:[0-9]+]]=, sin 466declare <2 x double> @llvm.sin.v2f64(<2 x double>) 467define <2 x double> @sin_v2f64(<2 x double> %x) { 468 %v = call <2 x double> @llvm.sin.v2f64(<2 x double> %x) 469 ret <2 x double> %v 470} 471 472; CHECK-LABEL: cos_v2f64: 473; CHECK: call $push[[L:[0-9]+]]=, cos 474declare <2 x double> @llvm.cos.v2f64(<2 x double>) 475define <2 x double> @cos_v2f64(<2 x double> %x) { 476 %v = call <2 x double> @llvm.cos.v2f64(<2 x double> %x) 477 ret <2 x double> %v 478} 479 480; CHECK-LABEL: powi_v2f64: 481; CHECK: call $push[[L:[0-9]+]]=, __powidf2 482declare <2 x double> @llvm.powi.v2f64.i32(<2 x double>, i32) 483define <2 x double> @powi_v2f64(<2 x double> %x, i32 %y) { 484 %v = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> %x, i32 %y) 485 ret <2 x double> %v 486} 487 488; CHECK-LABEL: pow_v2f64: 489; CHECK: call $push[[L:[0-9]+]]=, pow 490declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) 491define <2 x double> @pow_v2f64(<2 x double> %x, <2 x double> %y) { 492 %v = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> %y) 493 ret <2 x double> %v 494} 495 496; CHECK-LABEL: log_v2f64: 497; CHECK: call $push[[L:[0-9]+]]=, log 498declare <2 x double> @llvm.log.v2f64(<2 x double>) 499define <2 x double> @log_v2f64(<2 x double> %x) { 500 %v = call <2 x double> @llvm.log.v2f64(<2 x double> %x) 501 ret <2 x double> %v 502} 503 504; CHECK-LABEL: log2_v2f64: 505; CHECK: call $push[[L:[0-9]+]]=, log2 506declare <2 x double> @llvm.log2.v2f64(<2 x double>) 507define <2 x double> @log2_v2f64(<2 x double> %x) { 508 %v = call <2 x double> @llvm.log2.v2f64(<2 x double> %x) 509 ret <2 x double> %v 510} 511 512; CHECK-LABEL: log10_v2f64: 513; CHECK: call $push[[L:[0-9]+]]=, log10 514declare <2 x double> @llvm.log10.v2f64(<2 x double>) 515define <2 x double> @log10_v2f64(<2 x double> %x) { 516 %v = call <2 x double> @llvm.log10.v2f64(<2 x double> %x) 517 ret <2 x double> %v 518} 519 520; CHECK-LABEL: exp_v2f64: 521; CHECK: call $push[[L:[0-9]+]]=, exp 522declare <2 x double> @llvm.exp.v2f64(<2 x double>) 523define <2 x double> @exp_v2f64(<2 x double> %x) { 524 %v = call <2 x double> @llvm.exp.v2f64(<2 x double> %x) 525 ret <2 x double> %v 526} 527 528; CHECK-LABEL: exp2_v2f64: 529; CHECK: call $push[[L:[0-9]+]]=, exp2 530declare <2 x double> @llvm.exp2.v2f64(<2 x double>) 531define <2 x double> @exp2_v2f64(<2 x double> %x) { 532 %v = call <2 x double> @llvm.exp2.v2f64(<2 x double> %x) 533 ret <2 x double> %v 534} 535 536; CHECK-LABEL: rint_v2f64: 537; CHECK: f64.nearest 538declare <2 x double> @llvm.rint.v2f64(<2 x double>) 539define <2 x double> @rint_v2f64(<2 x double> %x) { 540 %v = call <2 x double> @llvm.rint.v2f64(<2 x double> %x) 541 ret <2 x double> %v 542} 543 544; CHECK-LABEL: round_v2f64: 545; CHECK: call $push[[L:[0-9]+]]=, round 546declare <2 x double> @llvm.round.v2f64(<2 x double>) 547define <2 x double> @round_v2f64(<2 x double> %x) { 548 %v = call <2 x double> @llvm.round.v2f64(<2 x double> %x) 549 ret <2 x double> %v 550} 551