1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s 2 3; Test that SIMD shifts can be lowered correctly even with shift 4; values that are more complex than plain splats. 5 6target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" 7target triple = "wasm32-unknown-unknown" 8 9;; TODO: Optimize this further by scalarizing the add 10 11; CHECK-LABEL: shl_add: 12; CHECK-NEXT: .functype shl_add (v128, i32, i32) -> (v128) 13; CHECK-NEXT: i8x16.splat $push1=, $1 14; CHECK-NEXT: i8x16.splat $push0=, $2 15; CHECK-NEXT: i8x16.add $push2=, $pop1, $pop0 16; CHECK-NEXT: i8x16.extract_lane_u $push3=, $pop2, 0 17; CHECK-NEXT: i8x16.shl $push4=, $0, $pop3 18; CHECK-NEXT: return $pop4 19define <16 x i8> @shl_add(<16 x i8> %v, i8 %a, i8 %b) { 20 %t1 = insertelement <16 x i8> undef, i8 %a, i32 0 21 %va = shufflevector <16 x i8> %t1, <16 x i8> undef, <16 x i32> zeroinitializer 22 %t2 = insertelement <16 x i8> undef, i8 %b, i32 0 23 %vb = shufflevector <16 x i8> %t2, <16 x i8> undef, <16 x i32> zeroinitializer 24 %shift = add <16 x i8> %va, %vb 25 %r = shl <16 x i8> %v, %shift 26 ret <16 x i8> %r 27} 28 29; CHECK-LABEL: shl_abs: 30; CHECK-NEXT: .functype shl_abs (v128, i32) -> (v128) 31; CHECK-NEXT: i8x16.extract_lane_u $push8=, $0, 0 32; CHECK-NEXT: i8x16.splat $push0=, $1 33; CHECK-NEXT: i8x16.abs $push98=, $pop0 34; CHECK-NEXT: local.tee $push97=, $2=, $pop98 35; CHECK-NEXT: i8x16.extract_lane_u $push6=, $pop97, 0 36; CHECK-NEXT: i32.const $push2=, 7 37; CHECK-NEXT: i32.and $push7=, $pop6, $pop2 38; CHECK-NEXT: i32.shl $push9=, $pop8, $pop7 39; CHECK-NEXT: i8x16.splat $push10=, $pop9 40; CHECK-NEXT: i8x16.extract_lane_u $push4=, $0, 1 41; CHECK-NEXT: i8x16.extract_lane_u $push1=, $2, 1 42; CHECK-NEXT: i32.const $push96=, 7 43; CHECK-NEXT: i32.and $push3=, $pop1, $pop96 44; CHECK-NEXT: i32.shl $push5=, $pop4, $pop3 45; CHECK-NEXT: i8x16.replace_lane $push11=, $pop10, 1, $pop5 46; ... 47; CHECK: i8x16.extract_lane_u $push79=, $0, 15 48; CHECK-NEXT: i8x16.extract_lane_u $push77=, $2, 15 49; CHECK-NEXT: i32.const $push82=, 7 50; CHECK-NEXT: i32.and $push78=, $pop77, $pop82 51; CHECK-NEXT: i32.shl $push80=, $pop79, $pop78 52; CHECK-NEXT: i8x16.replace_lane $push81=, $pop76, 15, $pop80 53; CHECK-NEXT: return $pop81 54define <16 x i8> @shl_abs(<16 x i8> %v, i8 %a) { 55 %t1 = insertelement <16 x i8> undef, i8 %a, i32 0 56 %va = shufflevector <16 x i8> %t1, <16 x i8> undef, <16 x i32> zeroinitializer 57 %nva = sub <16 x i8> zeroinitializer, %va 58 %c = icmp sgt <16 x i8> %va, zeroinitializer 59 %shift = select <16 x i1> %c, <16 x i8> %va, <16 x i8> %nva 60 %r = shl <16 x i8> %v, %shift 61 ret <16 x i8> %r 62} 63 64; CHECK-LABEL: shl_abs_add: 65; CHECK-NEXT: .functype shl_abs_add (v128, i32, i32) -> (v128) 66; CHECK-NEXT: i8x16.extract_lane_u $push11=, $0, 0 67; CHECK-NEXT: i8x16.splat $push1=, $1 68; CHECK-NEXT: i8x16.splat $push0=, $2 69; CHECK-NEXT: i8x16.add $push2=, $pop1, $pop0 70; CHECK-NEXT: v8x16.shuffle $push3=, $pop2, $0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 71; CHECK-NEXT: i8x16.abs $push101=, $pop3 72; CHECK-NEXT: local.tee $push100=, $3=, $pop101 73; CHECK-NEXT: i8x16.extract_lane_u $push9=, $pop100, 0 74; CHECK-NEXT: i32.const $push5=, 7 75; CHECK-NEXT: i32.and $push10=, $pop9, $pop5 76; CHECK-NEXT: i32.shl $push12=, $pop11, $pop10 77; CHECK-NEXT: i8x16.splat $push13=, $pop12 78; CHECK-NEXT: i8x16.extract_lane_u $push7=, $0, 1 79; CHECK-NEXT: i8x16.extract_lane_u $push4=, $3, 1 80; CHECK-NEXT: i32.const $push99=, 7 81; CHECK-NEXT: i32.and $push6=, $pop4, $pop99 82; CHECK-NEXT: i32.shl $push8=, $pop7, $pop6 83; CHECK-NEXT: i8x16.replace_lane $push14=, $pop13, 1, $pop8 84; ... 85; CHECK: i8x16.extract_lane_u $push82=, $0, 15 86; CHECK-NEXT: i8x16.extract_lane_u $push80=, $3, 15 87; CHECK-NEXT: i32.const $push85=, 7 88; CHECK-NEXT: i32.and $push81=, $pop80, $pop85 89; CHECK-NEXT: i32.shl $push83=, $pop82, $pop81 90; CHECK-NEXT: i8x16.replace_lane $push84=, $pop79, 15, $pop83 91; CHECK-NEXT: return $pop84 92define <16 x i8> @shl_abs_add(<16 x i8> %v, i8 %a, i8 %b) { 93 %t1 = insertelement <16 x i8> undef, i8 %a, i32 0 94 %va = shufflevector <16 x i8> %t1, <16 x i8> undef, <16 x i32> zeroinitializer 95 %t2 = insertelement <16 x i8> undef, i8 %b, i32 0 96 %vb = shufflevector <16 x i8> %t2, <16 x i8> undef, <16 x i32> zeroinitializer 97 %vadd = add <16 x i8> %va, %vb 98 %nvadd = sub <16 x i8> zeroinitializer, %vadd 99 %c = icmp sgt <16 x i8> %vadd, zeroinitializer 100 %shift = select <16 x i1> %c, <16 x i8> %vadd, <16 x i8> %nvadd 101 %r = shl <16 x i8> %v, %shift 102 ret <16 x i8> %r 103} 104