1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128 2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128 3 4; Test that SIMD128 intrinsics lower as expected. These intrinsics are 5; only expected to lower successfully if the simd128 attribute is 6; enabled and legal types are used. 7 8target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" 9target triple = "wasm32-unknown-unknown" 10 11; ============================================================================== 12; 16 x i8 13; ============================================================================== 14; CHECK-LABEL: swizzle_v16i8: 15; SIMD128-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}} 16; SIMD128-NEXT: v8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}} 17; SIMD128-NEXT: return $pop[[R]]{{$}} 18declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>) 19define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) { 20 %a = call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y) 21 ret <16 x i8> %a 22} 23 24; CHECK-LABEL: add_sat_s_v16i8: 25; SIMD128-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}} 26; SIMD128-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 27; SIMD128-NEXT: return $pop[[R]]{{$}} 28declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>) 29define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 30 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 31 ret <16 x i8> %a 32} 33 34; CHECK-LABEL: add_sat_u_v16i8: 35; SIMD128-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}} 36; SIMD128-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 37; SIMD128-NEXT: return $pop[[R]]{{$}} 38declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) 39define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 40 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 41 ret <16 x i8> %a 42} 43 44; CHECK-LABEL: sub_sat_s_v16i8: 45; SIMD128-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}} 46; SIMD128-NEXT: i8x16.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 47; SIMD128-NEXT: return $pop[[R]]{{$}} 48declare <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(<16 x i8>, <16 x i8>) 49define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 50 %a = call <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8( 51 <16 x i8> %x, <16 x i8> %y 52 ) 53 ret <16 x i8> %a 54} 55 56; CHECK-LABEL: sub_sat_u_v16i8: 57; SIMD128-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}} 58; SIMD128-NEXT: i8x16.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 59; SIMD128-NEXT: return $pop[[R]]{{$}} 60declare <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(<16 x i8>, <16 x i8>) 61define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 62 %a = call <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8( 63 <16 x i8> %x, <16 x i8> %y 64 ) 65 ret <16 x i8> %a 66} 67 68; CHECK-LABEL: min_s_v16i8: 69; SIMD128-NEXT: .functype min_s_v16i8 (v128, v128) -> (v128){{$}} 70; SIMD128-NEXT: i8x16.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 71; SIMD128-NEXT: return $pop[[R]]{{$}} 72declare <16 x i8> @llvm.wasm.min.signed.v16i8(<16 x i8>, <16 x i8>) 73define <16 x i8> @min_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 74 %a = call <16 x i8> @llvm.wasm.min.signed.v16i8(<16 x i8> %x, <16 x i8> %y) 75 ret <16 x i8> %a 76} 77 78; CHECK-LABEL: min_u_v16i8: 79; SIMD128-NEXT: .functype min_u_v16i8 (v128, v128) -> (v128){{$}} 80; SIMD128-NEXT: i8x16.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 81; SIMD128-NEXT: return $pop[[R]]{{$}} 82declare <16 x i8> @llvm.wasm.min.unsigned.v16i8(<16 x i8>, <16 x i8>) 83define <16 x i8> @min_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 84 %a = call <16 x i8> @llvm.wasm.min.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y) 85 ret <16 x i8> %a 86} 87 88; CHECK-LABEL: max_s_v16i8: 89; SIMD128-NEXT: .functype max_s_v16i8 (v128, v128) -> (v128){{$}} 90; SIMD128-NEXT: i8x16.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 91; SIMD128-NEXT: return $pop[[R]]{{$}} 92declare <16 x i8> @llvm.wasm.max.signed.v16i8(<16 x i8>, <16 x i8>) 93define <16 x i8> @max_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 94 %a = call <16 x i8> @llvm.wasm.max.signed.v16i8(<16 x i8> %x, <16 x i8> %y) 95 ret <16 x i8> %a 96} 97 98; CHECK-LABEL: max_u_v16i8: 99; SIMD128-NEXT: .functype max_u_v16i8 (v128, v128) -> (v128){{$}} 100; SIMD128-NEXT: i8x16.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 101; SIMD128-NEXT: return $pop[[R]]{{$}} 102declare <16 x i8> @llvm.wasm.max.unsigned.v16i8(<16 x i8>, <16 x i8>) 103define <16 x i8> @max_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 104 %a = call <16 x i8> @llvm.wasm.max.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y) 105 ret <16 x i8> %a 106} 107 108; CHECK-LABEL: any_v16i8: 109; SIMD128-NEXT: .functype any_v16i8 (v128) -> (i32){{$}} 110; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}} 111; SIMD128-NEXT: return $pop[[R]]{{$}} 112declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>) 113define i32 @any_v16i8(<16 x i8> %x) { 114 %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x) 115 ret i32 %a 116} 117 118; CHECK-LABEL: all_v16i8: 119; SIMD128-NEXT: .functype all_v16i8 (v128) -> (i32){{$}} 120; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}} 121; SIMD128-NEXT: return $pop[[R]]{{$}} 122declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>) 123define i32 @all_v16i8(<16 x i8> %x) { 124 %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x) 125 ret i32 %a 126} 127 128; CHECK-LABEL: bitselect_v16i8: 129; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}} 130; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 131; SIMD128-NEXT: return $pop[[R]]{{$}} 132declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 133define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) { 134 %a = call <16 x i8> @llvm.wasm.bitselect.v16i8( 135 <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c 136 ) 137 ret <16 x i8> %a 138} 139 140; CHECK-LABEL: narrow_signed_v16i8: 141; SIMD128-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}} 142; SIMD128-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 143; SIMD128-NEXT: return $pop[[R]]{{$}} 144declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>) 145define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) { 146 %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16( 147 <8 x i16> %low, <8 x i16> %high 148 ) 149 ret <16 x i8> %a 150} 151 152; CHECK-LABEL: narrow_unsigned_v16i8: 153; SIMD128-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}} 154; SIMD128-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 155; SIMD128-NEXT: return $pop[[R]]{{$}} 156declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>) 157define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) { 158 %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16( 159 <8 x i16> %low, <8 x i16> %high 160 ) 161 ret <16 x i8> %a 162} 163 164; ============================================================================== 165; 8 x i16 166; ============================================================================== 167; CHECK-LABEL: add_sat_s_v8i16: 168; SIMD128-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}} 169; SIMD128-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 170; SIMD128-NEXT: return $pop[[R]]{{$}} 171declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) 172define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 173 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 174 ret <8 x i16> %a 175} 176 177; CHECK-LABEL: add_sat_u_v8i16: 178; SIMD128-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}} 179; SIMD128-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 180; SIMD128-NEXT: return $pop[[R]]{{$}} 181declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>) 182define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 183 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 184 ret <8 x i16> %a 185} 186 187; CHECK-LABEL: sub_sat_s_v8i16: 188; SIMD128-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}} 189; SIMD128-NEXT: i16x8.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 190; SIMD128-NEXT: return $pop[[R]]{{$}} 191declare <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(<8 x i16>, <8 x i16>) 192define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 193 %a = call <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16( 194 <8 x i16> %x, <8 x i16> %y 195 ) 196 ret <8 x i16> %a 197} 198 199; CHECK-LABEL: sub_sat_u_v8i16: 200; SIMD128-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}} 201; SIMD128-NEXT: i16x8.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 202; SIMD128-NEXT: return $pop[[R]]{{$}} 203declare <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(<8 x i16>, <8 x i16>) 204define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 205 %a = call <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16( 206 <8 x i16> %x, <8 x i16> %y 207 ) 208 ret <8 x i16> %a 209} 210 211; CHECK-LABEL: min_s_v8i16: 212; SIMD128-NEXT: .functype min_s_v8i16 (v128, v128) -> (v128){{$}} 213; SIMD128-NEXT: i16x8.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 214; SIMD128-NEXT: return $pop[[R]]{{$}} 215declare <8 x i16> @llvm.wasm.min.signed.v8i16(<8 x i16>, <8 x i16>) 216define <8 x i16> @min_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 217 %a = call <8 x i16> @llvm.wasm.min.signed.v8i16(<8 x i16> %x, <8 x i16> %y) 218 ret <8 x i16> %a 219} 220 221; CHECK-LABEL: min_u_v8i16: 222; SIMD128-NEXT: .functype min_u_v8i16 (v128, v128) -> (v128){{$}} 223; SIMD128-NEXT: i16x8.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 224; SIMD128-NEXT: return $pop[[R]]{{$}} 225declare <8 x i16> @llvm.wasm.min.unsigned.v8i16(<8 x i16>, <8 x i16>) 226define <8 x i16> @min_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 227 %a = call <8 x i16> @llvm.wasm.min.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y) 228 ret <8 x i16> %a 229} 230 231; CHECK-LABEL: max_s_v8i16: 232; SIMD128-NEXT: .functype max_s_v8i16 (v128, v128) -> (v128){{$}} 233; SIMD128-NEXT: i16x8.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 234; SIMD128-NEXT: return $pop[[R]]{{$}} 235declare <8 x i16> @llvm.wasm.max.signed.v8i16(<8 x i16>, <8 x i16>) 236define <8 x i16> @max_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 237 %a = call <8 x i16> @llvm.wasm.max.signed.v8i16(<8 x i16> %x, <8 x i16> %y) 238 ret <8 x i16> %a 239} 240 241; CHECK-LABEL: max_u_v8i16: 242; SIMD128-NEXT: .functype max_u_v8i16 (v128, v128) -> (v128){{$}} 243; SIMD128-NEXT: i16x8.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 244; SIMD128-NEXT: return $pop[[R]]{{$}} 245declare <8 x i16> @llvm.wasm.max.unsigned.v8i16(<8 x i16>, <8 x i16>) 246define <8 x i16> @max_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 247 %a = call <8 x i16> @llvm.wasm.max.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y) 248 ret <8 x i16> %a 249} 250 251; CHECK-LABEL: any_v8i16: 252; SIMD128-NEXT: .functype any_v8i16 (v128) -> (i32){{$}} 253; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}} 254; SIMD128-NEXT: return $pop[[R]]{{$}} 255declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>) 256define i32 @any_v8i16(<8 x i16> %x) { 257 %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x) 258 ret i32 %a 259} 260 261; CHECK-LABEL: all_v8i16: 262; SIMD128-NEXT: .functype all_v8i16 (v128) -> (i32){{$}} 263; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}} 264; SIMD128-NEXT: return $pop[[R]]{{$}} 265declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>) 266define i32 @all_v8i16(<8 x i16> %x) { 267 %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x) 268 ret i32 %a 269} 270 271; CHECK-LABEL: bitselect_v8i16: 272; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}} 273; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 274; SIMD128-NEXT: return $pop[[R]]{{$}} 275declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 276define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) { 277 %a = call <8 x i16> @llvm.wasm.bitselect.v8i16( 278 <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c 279 ) 280 ret <8 x i16> %a 281} 282 283; CHECK-LABEL: narrow_signed_v8i16: 284; SIMD128-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}} 285; SIMD128-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 286; SIMD128-NEXT: return $pop[[R]]{{$}} 287declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>) 288define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) { 289 %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32( 290 <4 x i32> %low, <4 x i32> %high 291 ) 292 ret <8 x i16> %a 293} 294 295; CHECK-LABEL: narrow_unsigned_v8i16: 296; SIMD128-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}} 297; SIMD128-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 298; SIMD128-NEXT: return $pop[[R]]{{$}} 299declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>) 300define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) { 301 %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32( 302 <4 x i32> %low, <4 x i32> %high 303 ) 304 ret <8 x i16> %a 305} 306 307; CHECK-LABEL: widen_low_signed_v8i16: 308; SIMD128-NEXT: .functype widen_low_signed_v8i16 (v128) -> (v128){{$}} 309; SIMD128-NEXT: i16x8.widen_low_i8x16_s $push[[R:[0-9]+]]=, $0{{$}} 310; SIMD128-NEXT: return $pop[[R]]{{$}} 311declare <8 x i16> @llvm.wasm.widen.low.signed.v8i16.v16i8(<16 x i8>) 312define <8 x i16> @widen_low_signed_v8i16(<16 x i8> %v) { 313 %a = call <8 x i16> @llvm.wasm.widen.low.signed.v8i16.v16i8(<16 x i8> %v) 314 ret <8 x i16> %a 315} 316 317; CHECK-LABEL: widen_high_signed_v8i16: 318; SIMD128-NEXT: .functype widen_high_signed_v8i16 (v128) -> (v128){{$}} 319; SIMD128-NEXT: i16x8.widen_high_i8x16_s $push[[R:[0-9]+]]=, $0{{$}} 320; SIMD128-NEXT: return $pop[[R]]{{$}} 321declare <8 x i16> @llvm.wasm.widen.high.signed.v8i16.v16i8(<16 x i8>) 322define <8 x i16> @widen_high_signed_v8i16(<16 x i8> %v) { 323 %a = call <8 x i16> @llvm.wasm.widen.high.signed.v8i16.v16i8(<16 x i8> %v) 324 ret <8 x i16> %a 325} 326 327; CHECK-LABEL: widen_low_unsigned_v8i16: 328; SIMD128-NEXT: .functype widen_low_unsigned_v8i16 (v128) -> (v128){{$}} 329; SIMD128-NEXT: i16x8.widen_low_i8x16_u $push[[R:[0-9]+]]=, $0{{$}} 330; SIMD128-NEXT: return $pop[[R]]{{$}} 331declare <8 x i16> @llvm.wasm.widen.low.unsigned.v8i16.v16i8(<16 x i8>) 332define <8 x i16> @widen_low_unsigned_v8i16(<16 x i8> %v) { 333 %a = call <8 x i16> @llvm.wasm.widen.low.unsigned.v8i16.v16i8(<16 x i8> %v) 334 ret <8 x i16> %a 335} 336 337; CHECK-LABEL: widen_high_unsigned_v8i16: 338; SIMD128-NEXT: .functype widen_high_unsigned_v8i16 (v128) -> (v128){{$}} 339; SIMD128-NEXT: i16x8.widen_high_i8x16_u $push[[R:[0-9]+]]=, $0{{$}} 340; SIMD128-NEXT: return $pop[[R]]{{$}} 341declare <8 x i16> @llvm.wasm.widen.high.unsigned.v8i16.v16i8(<16 x i8>) 342define <8 x i16> @widen_high_unsigned_v8i16(<16 x i8> %v) { 343 %a = call <8 x i16> @llvm.wasm.widen.high.unsigned.v8i16.v16i8(<16 x i8> %v) 344 ret <8 x i16> %a 345} 346 347; ============================================================================== 348; 4 x i32 349; ============================================================================== 350; CHECK-LABEL: min_s_v4i32: 351; SIMD128-NEXT: .functype min_s_v4i32 (v128, v128) -> (v128){{$}} 352; SIMD128-NEXT: i32x4.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 353; SIMD128-NEXT: return $pop[[R]]{{$}} 354declare <4 x i32> @llvm.wasm.min.signed.v4i32(<4 x i32>, <4 x i32>) 355define <4 x i32> @min_s_v4i32(<4 x i32> %x, <4 x i32> %y) { 356 %a = call <4 x i32> @llvm.wasm.min.signed.v4i32(<4 x i32> %x, <4 x i32> %y) 357 ret <4 x i32> %a 358} 359 360; CHECK-LABEL: min_u_v4i32: 361; SIMD128-NEXT: .functype min_u_v4i32 (v128, v128) -> (v128){{$}} 362; SIMD128-NEXT: i32x4.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 363; SIMD128-NEXT: return $pop[[R]]{{$}} 364declare <4 x i32> @llvm.wasm.min.unsigned.v4i32(<4 x i32>, <4 x i32>) 365define <4 x i32> @min_u_v4i32(<4 x i32> %x, <4 x i32> %y) { 366 %a = call <4 x i32> @llvm.wasm.min.unsigned.v4i32(<4 x i32> %x, <4 x i32> %y) 367 ret <4 x i32> %a 368} 369 370; CHECK-LABEL: max_s_v4i32: 371; SIMD128-NEXT: .functype max_s_v4i32 (v128, v128) -> (v128){{$}} 372; SIMD128-NEXT: i32x4.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 373; SIMD128-NEXT: return $pop[[R]]{{$}} 374declare <4 x i32> @llvm.wasm.max.signed.v4i32(<4 x i32>, <4 x i32>) 375define <4 x i32> @max_s_v4i32(<4 x i32> %x, <4 x i32> %y) { 376 %a = call <4 x i32> @llvm.wasm.max.signed.v4i32(<4 x i32> %x, <4 x i32> %y) 377 ret <4 x i32> %a 378} 379 380; CHECK-LABEL: max_u_v4i32: 381; SIMD128-NEXT: .functype max_u_v4i32 (v128, v128) -> (v128){{$}} 382; SIMD128-NEXT: i32x4.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 383; SIMD128-NEXT: return $pop[[R]]{{$}} 384declare <4 x i32> @llvm.wasm.max.unsigned.v4i32(<4 x i32>, <4 x i32>) 385define <4 x i32> @max_u_v4i32(<4 x i32> %x, <4 x i32> %y) { 386 %a = call <4 x i32> @llvm.wasm.max.unsigned.v4i32(<4 x i32> %x, <4 x i32> %y) 387 ret <4 x i32> %a 388} 389 390; CHECK-LABEL: dot: 391; SIMD128-NEXT: .functype dot (v128, v128) -> (v128){{$}} 392; SIMD128-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 393; SIMD128-NEXT: return $pop[[R]]{{$}} 394declare <4 x i32> @llvm.wasm.dot(<8 x i16>, <8 x i16>) 395define <4 x i32> @dot(<8 x i16> %x, <8 x i16> %y) { 396 %a = call <4 x i32> @llvm.wasm.dot(<8 x i16> %x, <8 x i16> %y) 397 ret <4 x i32> %a 398} 399 400; CHECK-LABEL: any_v4i32: 401; SIMD128-NEXT: .functype any_v4i32 (v128) -> (i32){{$}} 402; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}} 403; SIMD128-NEXT: return $pop[[R]]{{$}} 404declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>) 405define i32 @any_v4i32(<4 x i32> %x) { 406 %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x) 407 ret i32 %a 408} 409 410; CHECK-LABEL: all_v4i32: 411; SIMD128-NEXT: .functype all_v4i32 (v128) -> (i32){{$}} 412; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}} 413; SIMD128-NEXT: return $pop[[R]]{{$}} 414declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>) 415define i32 @all_v4i32(<4 x i32> %x) { 416 %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x) 417 ret i32 %a 418} 419 420; CHECK-LABEL: bitselect_v4i32: 421; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}} 422; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 423; SIMD128-NEXT: return $pop[[R]]{{$}} 424declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 425define <4 x i32> @bitselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) { 426 %a = call <4 x i32> @llvm.wasm.bitselect.v4i32( 427 <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c 428 ) 429 ret <4 x i32> %a 430} 431 432; CHECK-LABEL: trunc_sat_s_v4i32: 433; NO-SIMD128-NOT: f32x4 434; SIMD128-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}} 435; SIMD128-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0 436; SIMD128-NEXT: return $pop[[R]] 437declare <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float>) 438define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) { 439 %a = call <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float> %x) 440 ret <4 x i32> %a 441} 442 443; CHECK-LABEL: trunc_sat_u_v4i32: 444; NO-SIMD128-NOT: f32x4 445; SIMD128-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}} 446; SIMD128-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0 447; SIMD128-NEXT: return $pop[[R]] 448declare <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float>) 449define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) { 450 %a = call <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float> %x) 451 ret <4 x i32> %a 452} 453 454; CHECK-LABEL: widen_low_signed_v4i32: 455; SIMD128-NEXT: .functype widen_low_signed_v4i32 (v128) -> (v128){{$}} 456; SIMD128-NEXT: i32x4.widen_low_i16x8_s $push[[R:[0-9]+]]=, $0{{$}} 457; SIMD128-NEXT: return $pop[[R]]{{$}} 458declare <4 x i32> @llvm.wasm.widen.low.signed.v4i32.v8i16(<8 x i16>) 459define <4 x i32> @widen_low_signed_v4i32(<8 x i16> %v) { 460 %a = call <4 x i32> @llvm.wasm.widen.low.signed.v4i32.v8i16(<8 x i16> %v) 461 ret <4 x i32> %a 462} 463 464; CHECK-LABEL: widen_high_signed_v4i32: 465; SIMD128-NEXT: .functype widen_high_signed_v4i32 (v128) -> (v128){{$}} 466; SIMD128-NEXT: i32x4.widen_high_i16x8_s $push[[R:[0-9]+]]=, $0{{$}} 467; SIMD128-NEXT: return $pop[[R]]{{$}} 468declare <4 x i32> @llvm.wasm.widen.high.signed.v4i32.v8i16(<8 x i16>) 469define <4 x i32> @widen_high_signed_v4i32(<8 x i16> %v) { 470 %a = call <4 x i32> @llvm.wasm.widen.high.signed.v4i32.v8i16(<8 x i16> %v) 471 ret <4 x i32> %a 472} 473 474; CHECK-LABEL: widen_low_unsigned_v4i32: 475; SIMD128-NEXT: .functype widen_low_unsigned_v4i32 (v128) -> (v128){{$}} 476; SIMD128-NEXT: i32x4.widen_low_i16x8_u $push[[R:[0-9]+]]=, $0{{$}} 477; SIMD128-NEXT: return $pop[[R]]{{$}} 478declare <4 x i32> @llvm.wasm.widen.low.unsigned.v4i32.v8i16(<8 x i16>) 479define <4 x i32> @widen_low_unsigned_v4i32(<8 x i16> %v) { 480 %a = call <4 x i32> @llvm.wasm.widen.low.unsigned.v4i32.v8i16(<8 x i16> %v) 481 ret <4 x i32> %a 482} 483 484; CHECK-LABEL: widen_high_unsigned_v4i32: 485; SIMD128-NEXT: .functype widen_high_unsigned_v4i32 (v128) -> (v128){{$}} 486; SIMD128-NEXT: i32x4.widen_high_i16x8_u $push[[R:[0-9]+]]=, $0{{$}} 487; SIMD128-NEXT: return $pop[[R]]{{$}} 488declare <4 x i32> @llvm.wasm.widen.high.unsigned.v4i32.v8i16(<8 x i16>) 489define <4 x i32> @widen_high_unsigned_v4i32(<8 x i16> %v) { 490 %a = call <4 x i32> @llvm.wasm.widen.high.unsigned.v4i32.v8i16(<8 x i16> %v) 491 ret <4 x i32> %a 492} 493 494; ============================================================================== 495; 2 x i64 496; ============================================================================== 497; CHECK-LABEL: any_v2i64: 498; SIMD128-NEXT: .functype any_v2i64 (v128) -> (i32){{$}} 499; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}} 500; SIMD128-NEXT: return $pop[[R]]{{$}} 501declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>) 502define i32 @any_v2i64(<2 x i64> %x) { 503 %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x) 504 ret i32 %a 505} 506 507; CHECK-LABEL: all_v2i64: 508; SIMD128-NEXT: .functype all_v2i64 (v128) -> (i32){{$}} 509; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}} 510; SIMD128-NEXT: return $pop[[R]]{{$}} 511declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>) 512define i32 @all_v2i64(<2 x i64> %x) { 513 %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x) 514 ret i32 %a 515} 516 517; CHECK-LABEL: bitselect_v2i64: 518; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}} 519; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 520; SIMD128-NEXT: return $pop[[R]]{{$}} 521declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 522define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) { 523 %a = call <2 x i64> @llvm.wasm.bitselect.v2i64( 524 <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c 525 ) 526 ret <2 x i64> %a 527} 528 529; CHECK-LABEL: trunc_sat_s_v2i64: 530; NO-SIMD128-NOT: f32x4 531; SIMD128-NEXT: .functype trunc_sat_s_v2i64 (v128) -> (v128){{$}} 532; SIMD128-NEXT: i64x2.trunc_sat_f64x2_s $push[[R:[0-9]+]]=, $0 533; SIMD128-NEXT: return $pop[[R]] 534declare <2 x i64> @llvm.wasm.trunc.saturate.signed.v2i64.v2f64(<2 x double>) 535define <2 x i64> @trunc_sat_s_v2i64(<2 x double> %x) { 536 %a = call <2 x i64> @llvm.wasm.trunc.saturate.signed.v2i64.v2f64(<2 x double> %x) 537 ret <2 x i64> %a 538} 539 540; CHECK-LABEL: trunc_sat_u_v2i64: 541; NO-SIMD128-NOT: f32x4 542; SIMD128-NEXT: .functype trunc_sat_u_v2i64 (v128) -> (v128){{$}} 543; SIMD128-NEXT: i64x2.trunc_sat_f64x2_u $push[[R:[0-9]+]]=, $0 544; SIMD128-NEXT: return $pop[[R]] 545declare <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double>) 546define <2 x i64> @trunc_sat_u_v2i64(<2 x double> %x) { 547 %a = call <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double> %x) 548 ret <2 x i64> %a 549} 550 551; ============================================================================== 552; 4 x f32 553; ============================================================================== 554; CHECK-LABEL: bitselect_v4f32: 555; SIMD128-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}} 556; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 557; SIMD128-NEXT: return $pop[[R]]{{$}} 558declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>) 559define <4 x float> @bitselect_v4f32(<4 x float> %v1, <4 x float> %v2, <4 x float> %c) { 560 %a = call <4 x float> @llvm.wasm.bitselect.v4f32( 561 <4 x float> %v1, <4 x float> %v2, <4 x float> %c 562 ) 563 ret <4 x float> %a 564} 565 566; CHECK-LABEL: qfma_v4f32: 567; SIMD128-NEXT: .functype qfma_v4f32 (v128, v128, v128) -> (v128){{$}} 568; SIMD128-NEXT: f32x4.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 569; SIMD128-NEXT: return $pop[[R]]{{$}} 570declare <4 x float> @llvm.wasm.qfma.v4f32(<4 x float>, <4 x float>, <4 x float>) 571define <4 x float> @qfma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 572 %v = call <4 x float> @llvm.wasm.qfma.v4f32( 573 <4 x float> %a, <4 x float> %b, <4 x float> %c 574 ) 575 ret <4 x float> %v 576} 577 578; CHECK-LABEL: qfms_v4f32: 579; SIMD128-NEXT: .functype qfms_v4f32 (v128, v128, v128) -> (v128){{$}} 580; SIMD128-NEXT: f32x4.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 581; SIMD128-NEXT: return $pop[[R]]{{$}} 582declare <4 x float> @llvm.wasm.qfms.v4f32(<4 x float>, <4 x float>, <4 x float>) 583define <4 x float> @qfms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 584 %v = call <4 x float> @llvm.wasm.qfms.v4f32( 585 <4 x float> %a, <4 x float> %b, <4 x float> %c 586 ) 587 ret <4 x float> %v 588} 589 590; ============================================================================== 591; 2 x f64 592; ============================================================================== 593; CHECK-LABEL: bitselect_v2f64: 594; SIMD128-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}} 595; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 596; SIMD128-NEXT: return $pop[[R]]{{$}} 597declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>) 598define <2 x double> @bitselect_v2f64(<2 x double> %v1, <2 x double> %v2, <2 x double> %c) { 599 %a = call <2 x double> @llvm.wasm.bitselect.v2f64( 600 <2 x double> %v1, <2 x double> %v2, <2 x double> %c 601 ) 602 ret <2 x double> %a 603} 604 605; CHECK-LABEL: qfma_v2f64: 606; SIMD128-NEXT: .functype qfma_v2f64 (v128, v128, v128) -> (v128){{$}} 607; SIMD128-NEXT: f64x2.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 608; SIMD128-NEXT: return $pop[[R]]{{$}} 609declare <2 x double> @llvm.wasm.qfma.v2f64(<2 x double>, <2 x double>, <2 x double>) 610define <2 x double> @qfma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 611 %v = call <2 x double> @llvm.wasm.qfma.v2f64( 612 <2 x double> %a, <2 x double> %b, <2 x double> %c 613 ) 614 ret <2 x double> %v 615} 616 617; CHECK-LABEL: qfms_v2f64: 618; SIMD128-NEXT: .functype qfms_v2f64 (v128, v128, v128) -> (v128){{$}} 619; SIMD128-NEXT: f64x2.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 620; SIMD128-NEXT: return $pop[[R]]{{$}} 621declare <2 x double> @llvm.wasm.qfms.v2f64(<2 x double>, <2 x double>, <2 x double>) 622define <2 x double> @qfms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 623 %v = call <2 x double> @llvm.wasm.qfms.v2f64( 624 <2 x double> %a, <2 x double> %b, <2 x double> %c 625 ) 626 ret <2 x double> %v 627} 628