1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd | FileCheck %s --check-prefixes=CHECK,SLOW 2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd -fast-isel | FileCheck %s 3 4; Test that SIMD128 intrinsics lower as expected. These intrinsics are 5; only expected to lower successfully if the simd128 attribute is 6; enabled and legal types are used. 7 8target triple = "wasm32-unknown-unknown" 9 10; ============================================================================== 11; 16 x i8 12; ============================================================================== 13; CHECK-LABEL: swizzle_v16i8: 14; CHECK-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}} 15; CHECK-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}} 16; CHECK-NEXT: return $pop[[R]]{{$}} 17declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>) 18define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) { 19 %a = call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y) 20 ret <16 x i8> %a 21} 22 23; CHECK-LABEL: add_sat_s_v16i8: 24; CHECK-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}} 25; CHECK-NEXT: i8x16.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 26; CHECK-NEXT: return $pop[[R]]{{$}} 27declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>) 28define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 29 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 30 ret <16 x i8> %a 31} 32 33; CHECK-LABEL: add_sat_u_v16i8: 34; CHECK-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}} 35; CHECK-NEXT: i8x16.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 36; CHECK-NEXT: return $pop[[R]]{{$}} 37declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) 38define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 39 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 40 ret <16 x i8> %a 41} 42 43; CHECK-LABEL: sub_sat_s_v16i8: 44; CHECK-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}} 45; CHECK-NEXT: i8x16.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 46; CHECK-NEXT: return $pop[[R]]{{$}} 47declare <16 x i8> @llvm.wasm.sub.sat.signed.v16i8(<16 x i8>, <16 x i8>) 48define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 49 %a = call <16 x i8> @llvm.wasm.sub.sat.signed.v16i8( 50 <16 x i8> %x, <16 x i8> %y 51 ) 52 ret <16 x i8> %a 53} 54 55; CHECK-LABEL: sub_sat_u_v16i8: 56; CHECK-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}} 57; CHECK-NEXT: i8x16.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 58; CHECK-NEXT: return $pop[[R]]{{$}} 59declare <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8(<16 x i8>, <16 x i8>) 60define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 61 %a = call <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8( 62 <16 x i8> %x, <16 x i8> %y 63 ) 64 ret <16 x i8> %a 65} 66 67; CHECK-LABEL: avgr_u_v16i8: 68; CHECK-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}} 69; CHECK-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 70; CHECK-NEXT: return $pop[[R]]{{$}} 71declare <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8>, <16 x i8>) 72define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 73 %a = call <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y) 74 ret <16 x i8> %a 75} 76 77; CHECK-LABEL: popcnt_v16i8: 78; CHECK-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}} 79; CHECK-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}} 80; CHECK-NEXT: return $pop[[R]]{{$}} 81declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) 82define <16 x i8> @popcnt_v16i8(<16 x i8> %x) { 83 %a = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %x) 84 ret <16 x i8> %a 85} 86 87; CHECK-LABEL: any_v16i8: 88; CHECK-NEXT: .functype any_v16i8 (v128) -> (i32){{$}} 89; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 90; CHECK-NEXT: return $pop[[R]]{{$}} 91declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>) 92define i32 @any_v16i8(<16 x i8> %x) { 93 %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x) 94 ret i32 %a 95} 96 97; CHECK-LABEL: all_v16i8: 98; CHECK-NEXT: .functype all_v16i8 (v128) -> (i32){{$}} 99; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}} 100; CHECK-NEXT: return $pop[[R]]{{$}} 101declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>) 102define i32 @all_v16i8(<16 x i8> %x) { 103 %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x) 104 ret i32 %a 105} 106 107; CHECK-LABEL: bitmask_v16i8: 108; CHECK-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}} 109; CHECK-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}} 110; CHECK-NEXT: return $pop[[R]]{{$}} 111declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>) 112define i32 @bitmask_v16i8(<16 x i8> %x) { 113 %a = call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x) 114 ret i32 %a 115} 116 117; CHECK-LABEL: bitselect_v16i8: 118; CHECK-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}} 119; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 120; CHECK-NEXT: return $pop[[R]]{{$}} 121declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 122define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) { 123 %a = call <16 x i8> @llvm.wasm.bitselect.v16i8( 124 <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c 125 ) 126 ret <16 x i8> %a 127} 128 129; CHECK-LABEL: narrow_signed_v16i8: 130; CHECK-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}} 131; CHECK-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 132; CHECK-NEXT: return $pop[[R]]{{$}} 133declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>) 134define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) { 135 %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16( 136 <8 x i16> %low, <8 x i16> %high 137 ) 138 ret <16 x i8> %a 139} 140 141; CHECK-LABEL: narrow_unsigned_v16i8: 142; CHECK-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}} 143; CHECK-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 144; CHECK-NEXT: return $pop[[R]]{{$}} 145declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>) 146define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) { 147 %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16( 148 <8 x i16> %low, <8 x i16> %high 149 ) 150 ret <16 x i8> %a 151} 152 153; CHECK-LABEL: shuffle_v16i8: 154; NO-CHECK-NOT: i8x16 155; CHECK-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}} 156; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 157; CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}} 158; CHECK-NEXT: return $pop[[R]]{{$}} 159declare <16 x i8> @llvm.wasm.shuffle( 160 <16 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, 161 i32, i32, i32, i32, i32) 162define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) { 163 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 164 i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, 165 i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 35) 166 ret <16 x i8> %res 167} 168 169; CHECK-LABEL: shuffle_undef_v16i8: 170; NO-CHECK-NOT: i8x16 171; CHECK-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}} 172; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 173; CHECK-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}} 174; CHECK-NEXT: return $pop[[R]]{{$}} 175define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) { 176 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 177 i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 178 i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 179 i32 undef, i32 undef, i32 undef, i32 2) 180 ret <16 x i8> %res 181} 182 183; CHECK-LABEL: laneselect_v16i8: 184; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}} 185; CHECK-NEXT: i8x16.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 186; CHECK-NEXT: return $pop[[R]]{{$}} 187declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 188define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 189 %v = call <16 x i8> @llvm.wasm.laneselect.v16i8( 190 <16 x i8> %a, <16 x i8> %b, <16 x i8> %c 191 ) 192 ret <16 x i8> %v 193} 194 195; CHECK-LABEL: relaxed_swizzle_v16i8: 196; CHECK-NEXT: .functype relaxed_swizzle_v16i8 (v128, v128) -> (v128){{$}} 197; CHECK-NEXT: i8x16.relaxed_swizzle $push[[R:[0-9]+]]=, $0, $1{{$}} 198; CHECK-NEXT: return $pop[[R]]{{$}} 199declare <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8>, <16 x i8>) 200define <16 x i8> @relaxed_swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) { 201 %a = call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y) 202 ret <16 x i8> %a 203} 204 205; ============================================================================== 206; 8 x i16 207; ============================================================================== 208; CHECK-LABEL: add_sat_s_v8i16: 209; CHECK-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}} 210; CHECK-NEXT: i16x8.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 211; CHECK-NEXT: return $pop[[R]]{{$}} 212declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) 213define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 214 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 215 ret <8 x i16> %a 216} 217 218; CHECK-LABEL: add_sat_u_v8i16: 219; CHECK-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}} 220; CHECK-NEXT: i16x8.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 221; CHECK-NEXT: return $pop[[R]]{{$}} 222declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>) 223define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 224 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 225 ret <8 x i16> %a 226} 227 228; CHECK-LABEL: sub_sat_s_v8i16: 229; CHECK-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}} 230; CHECK-NEXT: i16x8.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 231; CHECK-NEXT: return $pop[[R]]{{$}} 232declare <8 x i16> @llvm.wasm.sub.sat.signed.v8i16(<8 x i16>, <8 x i16>) 233define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 234 %a = call <8 x i16> @llvm.wasm.sub.sat.signed.v8i16( 235 <8 x i16> %x, <8 x i16> %y 236 ) 237 ret <8 x i16> %a 238} 239 240; CHECK-LABEL: sub_sat_u_v8i16: 241; CHECK-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}} 242; CHECK-NEXT: i16x8.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 243; CHECK-NEXT: return $pop[[R]]{{$}} 244declare <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16(<8 x i16>, <8 x i16>) 245define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 246 %a = call <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16( 247 <8 x i16> %x, <8 x i16> %y 248 ) 249 ret <8 x i16> %a 250} 251 252; CHECK-LABEL: avgr_u_v8i16: 253; CHECK-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}} 254; CHECK-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 255; CHECK-NEXT: return $pop[[R]]{{$}} 256declare <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16>, <8 x i16>) 257define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 258 %a = call <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y) 259 ret <8 x i16> %a 260} 261 262; CHECK-LABEL: q15mulr_sat_s_v8i16: 263; CHECK-NEXT: .functype q15mulr_sat_s_v8i16 (v128, v128) -> (v128){{$}} 264; CHECK-NEXT: i16x8.q15mulr_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 265; CHECK-NEXT: return $pop[[R]]{{$}} 266declare <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16>, <8 x i16>) 267define <8 x i16> @q15mulr_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 268 %a = call <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16> %x, 269 <8 x i16> %y) 270 ret <8 x i16> %a 271} 272 273; CHECK-LABEL: extadd_pairwise_s_v8i16: 274; CHECK-NEXT: .functype extadd_pairwise_s_v8i16 (v128) -> (v128){{$}} 275; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_s $push[[R:[0-9]+]]=, $0{{$}} 276; CHECK-NEXT: return $pop[[R]]{{$}} 277declare <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8>) 278define <8 x i16> @extadd_pairwise_s_v8i16(<16 x i8> %x) { 279 %a = call <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8> %x) 280 ret <8 x i16> %a 281} 282 283; CHECK-LABEL: extadd_pairwise_u_v8i16: 284; CHECK-NEXT: .functype extadd_pairwise_u_v8i16 (v128) -> (v128){{$}} 285; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_u $push[[R:[0-9]+]]=, $0{{$}} 286; CHECK-NEXT: return $pop[[R]]{{$}} 287declare <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8>) 288define <8 x i16> @extadd_pairwise_u_v8i16(<16 x i8> %x) { 289 %a = call <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8> %x) 290 ret <8 x i16> %a 291} 292 293; CHECK-LABEL: any_v8i16: 294; CHECK-NEXT: .functype any_v8i16 (v128) -> (i32){{$}} 295; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 296; CHECK-NEXT: return $pop[[R]]{{$}} 297declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>) 298define i32 @any_v8i16(<8 x i16> %x) { 299 %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x) 300 ret i32 %a 301} 302 303; CHECK-LABEL: all_v8i16: 304; CHECK-NEXT: .functype all_v8i16 (v128) -> (i32){{$}} 305; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}} 306; CHECK-NEXT: return $pop[[R]]{{$}} 307declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>) 308define i32 @all_v8i16(<8 x i16> %x) { 309 %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x) 310 ret i32 %a 311} 312 313; CHECK-LABEL: bitmask_v8i16: 314; CHECK-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}} 315; CHECK-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}} 316; CHECK-NEXT: return $pop[[R]]{{$}} 317declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>) 318define i32 @bitmask_v8i16(<8 x i16> %x) { 319 %a = call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x) 320 ret i32 %a 321} 322 323; CHECK-LABEL: bitselect_v8i16: 324; CHECK-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}} 325; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 326; CHECK-NEXT: return $pop[[R]]{{$}} 327declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 328define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) { 329 %a = call <8 x i16> @llvm.wasm.bitselect.v8i16( 330 <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c 331 ) 332 ret <8 x i16> %a 333} 334 335; CHECK-LABEL: narrow_signed_v8i16: 336; CHECK-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}} 337; CHECK-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 338; CHECK-NEXT: return $pop[[R]]{{$}} 339declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>) 340define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) { 341 %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32( 342 <4 x i32> %low, <4 x i32> %high 343 ) 344 ret <8 x i16> %a 345} 346 347; CHECK-LABEL: narrow_unsigned_v8i16: 348; CHECK-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}} 349; CHECK-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 350; CHECK-NEXT: return $pop[[R]]{{$}} 351declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>) 352define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) { 353 %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32( 354 <4 x i32> %low, <4 x i32> %high 355 ) 356 ret <8 x i16> %a 357} 358 359; CHECK-LABEL: laneselect_v8i16: 360; CHECK-NEXT: .functype laneselect_v8i16 (v128, v128, v128) -> (v128){{$}} 361; CHECK-NEXT: i16x8.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 362; CHECK-NEXT: return $pop[[R]]{{$}} 363declare <8 x i16> @llvm.wasm.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 364define <8 x i16> @laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 365 %v = call <8 x i16> @llvm.wasm.laneselect.v8i16( 366 <8 x i16> %a, <8 x i16> %b, <8 x i16> %c 367 ) 368 ret <8 x i16> %v 369} 370 371; CHECK-LABEL: relaxed_q15mulr_s_i16x8: 372; CHECK-NEXT: .functype relaxed_q15mulr_s_i16x8 (v128, v128) -> (v128){{$}} 373; CHECK-NEXT: i16x8.relaxed_q15mulr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 374; CHECK-NEXT: return $pop[[R]]{{$}} 375declare <8 x i16> @llvm.wasm.relaxed.q15mulr.signed(<8 x i16>, <8 x i16>) 376define <8 x i16> @relaxed_q15mulr_s_i16x8(<8 x i16> %a, <8 x i16> %b) { 377 %v = call <8 x i16> @llvm.wasm.relaxed.q15mulr.signed( 378 <8 x i16> %a, <8 x i16> %b 379 ) 380 ret <8 x i16> %v 381} 382 383; CHECK-LABEL: dot_i8x16_i7x16_s_i16x8: 384; CHECK-NEXT: .functype dot_i8x16_i7x16_s_i16x8 (v128, v128) -> (v128){{$}} 385; CHECK-NEXT: i16x8.dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}} 386; CHECK-NEXT: return $pop[[R]]{{$}} 387declare <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>) 388define <8 x i16> @dot_i8x16_i7x16_s_i16x8(<16 x i8> %a, <16 x i8> %b) { 389 %v = call <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed( 390 <16 x i8> %a, <16 x i8> %b 391 ) 392 ret <8 x i16> %v 393} 394 395; ============================================================================== 396; 4 x i32 397; ============================================================================== 398; CHECK-LABEL: dot: 399; CHECK-NEXT: .functype dot (v128, v128) -> (v128){{$}} 400; CHECK-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 401; CHECK-NEXT: return $pop[[R]]{{$}} 402declare <4 x i32> @llvm.wasm.dot(<8 x i16>, <8 x i16>) 403define <4 x i32> @dot(<8 x i16> %x, <8 x i16> %y) { 404 %a = call <4 x i32> @llvm.wasm.dot(<8 x i16> %x, <8 x i16> %y) 405 ret <4 x i32> %a 406} 407 408; CHECK-LABEL: extadd_pairwise_s_v4i32: 409; CHECK-NEXT: .functype extadd_pairwise_s_v4i32 (v128) -> (v128){{$}} 410; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_s $push[[R:[0-9]+]]=, $0{{$}} 411; CHECK-NEXT: return $pop[[R]]{{$}} 412declare <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16>) 413define <4 x i32> @extadd_pairwise_s_v4i32(<8 x i16> %x) { 414 %a = call <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16> %x) 415 ret <4 x i32> %a 416} 417 418; CHECK-LABEL: extadd_pairwise_u_v4i32: 419; CHECK-NEXT: .functype extadd_pairwise_u_v4i32 (v128) -> (v128){{$}} 420; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_u $push[[R:[0-9]+]]=, $0{{$}} 421; CHECK-NEXT: return $pop[[R]]{{$}} 422declare <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16>) 423define <4 x i32> @extadd_pairwise_u_v4i32(<8 x i16> %x) { 424 %a = call <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16> %x) 425 ret <4 x i32> %a 426} 427 428 429; CHECK-LABEL: any_v4i32: 430; CHECK-NEXT: .functype any_v4i32 (v128) -> (i32){{$}} 431; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 432; CHECK-NEXT: return $pop[[R]]{{$}} 433declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>) 434define i32 @any_v4i32(<4 x i32> %x) { 435 %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x) 436 ret i32 %a 437} 438 439; CHECK-LABEL: all_v4i32: 440; CHECK-NEXT: .functype all_v4i32 (v128) -> (i32){{$}} 441; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}} 442; CHECK-NEXT: return $pop[[R]]{{$}} 443declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>) 444define i32 @all_v4i32(<4 x i32> %x) { 445 %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x) 446 ret i32 %a 447} 448 449; CHECK-LABEL: bitmask_v4i32: 450; CHECK-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}} 451; CHECK-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}} 452; CHECK-NEXT: return $pop[[R]]{{$}} 453declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>) 454define i32 @bitmask_v4i32(<4 x i32> %x) { 455 %a = call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x) 456 ret i32 %a 457} 458 459; CHECK-LABEL: bitselect_v4i32: 460; CHECK-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}} 461; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 462; CHECK-NEXT: return $pop[[R]]{{$}} 463declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 464define <4 x i32> @bitselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) { 465 %a = call <4 x i32> @llvm.wasm.bitselect.v4i32( 466 <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c 467 ) 468 ret <4 x i32> %a 469} 470 471; CHECK-LABEL: trunc_sat_s_v4i32: 472; NO-CHECK-NOT: f32x4 473; CHECK-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}} 474; CHECK-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0 475; CHECK-NEXT: return $pop[[R]] 476declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float>) 477define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) { 478 %a = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %x) 479 ret <4 x i32> %a 480} 481 482; CHECK-LABEL: trunc_sat_u_v4i32: 483; NO-CHECK-NOT: f32x4 484; CHECK-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}} 485; CHECK-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0 486; CHECK-NEXT: return $pop[[R]] 487declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float>) 488define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) { 489 %a = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %x) 490 ret <4 x i32> %a 491} 492 493; CHECK-LABEL: trunc_sat_s_zero_v4i32: 494; CHECK-NEXT: .functype trunc_sat_s_zero_v4i32 (v128) -> (v128){{$}} 495; CHECK-NEXT: i32x4.trunc_sat_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}} 496; CHECK-NEXT: return $pop[[R]]{{$}} 497declare <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double>) 498define <4 x i32> @trunc_sat_s_zero_v4i32(<2 x double> %x) { 499 %v = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %x) 500 %a = shufflevector <2 x i32> %v, <2 x i32> <i32 0, i32 0>, 501 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 502 ret <4 x i32> %a 503} 504 505; CHECK-LABEL: trunc_sat_s_zero_v4i32_2: 506; CHECK-NEXT: .functype trunc_sat_s_zero_v4i32_2 (v128) -> (v128){{$}} 507; SLOW-NEXT: i32x4.trunc_sat_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}} 508; SLOW-NEXT: return $pop[[R]]{{$}} 509declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double>) 510define <4 x i32> @trunc_sat_s_zero_v4i32_2(<2 x double> %x) { 511 %v = shufflevector <2 x double> %x, <2 x double> zeroinitializer, 512 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 513 %a = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double> %v) 514 ret <4 x i32> %a 515} 516 517; CHECK-LABEL: trunc_sat_u_zero_v4i32: 518; CHECK-NEXT: .functype trunc_sat_u_zero_v4i32 (v128) -> (v128){{$}} 519; CHECK-NEXT: i32x4.trunc_sat_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}} 520; CHECK-NEXT: return $pop[[R]]{{$}} 521declare <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double>) 522define <4 x i32> @trunc_sat_u_zero_v4i32(<2 x double> %x) { 523 %v = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %x) 524 %a = shufflevector <2 x i32> %v, <2 x i32> <i32 0, i32 0>, 525 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 526 ret <4 x i32> %a 527} 528 529; CHECK-LABEL: trunc_sat_u_zero_v4i32_2: 530; CHECK-NEXT: .functype trunc_sat_u_zero_v4i32_2 (v128) -> (v128){{$}} 531; SLOW-NEXT: i32x4.trunc_sat_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}} 532; SLOW-NEXT: return $pop[[R]]{{$}} 533declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double>) 534define <4 x i32> @trunc_sat_u_zero_v4i32_2(<2 x double> %x) { 535 %v = shufflevector <2 x double> %x, <2 x double> zeroinitializer, 536 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 537 %a = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double> %v) 538 ret <4 x i32> %a 539} 540 541; CHECK-LABEL: laneselect_v4i32: 542; CHECK-NEXT: .functype laneselect_v4i32 (v128, v128, v128) -> (v128){{$}} 543; CHECK-NEXT: i32x4.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 544; CHECK-NEXT: return $pop[[R]]{{$}} 545declare <4 x i32> @llvm.wasm.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 546define <4 x i32> @laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 547 %v = call <4 x i32> @llvm.wasm.laneselect.v4i32( 548 <4 x i32> %a, <4 x i32> %b, <4 x i32> %c 549 ) 550 ret <4 x i32> %v 551} 552 553; CHECK-LABEL: relaxed_trunc_s: 554; NO-CHECK-NOT: f32x4 555; CHECK-NEXT: .functype relaxed_trunc_s (v128) -> (v128){{$}} 556; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_s $push[[R:[0-9]+]]=, $0 557; CHECK-NEXT: return $pop[[R]] 558declare <4 x i32> @llvm.wasm.relaxed.trunc.signed(<4 x float>) 559define <4 x i32> @relaxed_trunc_s(<4 x float> %x) { 560 %a = call <4 x i32> @llvm.wasm.relaxed.trunc.signed(<4 x float> %x) 561 ret <4 x i32> %a 562} 563 564; CHECK-LABEL: relaxed_trunc_u: 565; NO-CHECK-NOT: f32x4 566; CHECK-NEXT: .functype relaxed_trunc_u (v128) -> (v128){{$}} 567; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_u $push[[R:[0-9]+]]=, $0 568; CHECK-NEXT: return $pop[[R]] 569declare <4 x i32> @llvm.wasm.relaxed.trunc.unsigned(<4 x float>) 570define <4 x i32> @relaxed_trunc_u(<4 x float> %x) { 571 %a = call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned(<4 x float> %x) 572 ret <4 x i32> %a 573} 574 575; CHECK-LABEL: relaxed_trunc_s_zero: 576; CHECK-NEXT: .functype relaxed_trunc_s_zero (v128) -> (v128){{$}} 577; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}} 578; CHECK-NEXT: return $pop[[R]]{{$}} 579declare <4 x i32> @llvm.wasm.relaxed.trunc.signed.zero(<2 x double>) 580define <4 x i32> @relaxed_trunc_s_zero(<2 x double> %x) { 581 %a = call <4 x i32> @llvm.wasm.relaxed.trunc.signed.zero(<2 x double> %x) 582 ret <4 x i32> %a 583} 584 585; CHECK-LABEL: relaxed_trunc_u_zero: 586; CHECK-NEXT: .functype relaxed_trunc_u_zero (v128) -> (v128){{$}} 587; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}} 588; CHECK-NEXT: return $pop[[R]]{{$}} 589declare <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.zero(<2 x double>) 590define <4 x i32> @relaxed_trunc_u_zero(<2 x double> %x) { 591 %a = call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.zero(<2 x double> %x) 592 ret <4 x i32> %a 593} 594 595; CHECK-LABEL: dot_i8x16_i7x16_add_s_i32x4: 596; CHECK-NEXT: .functype dot_i8x16_i7x16_add_s_i32x4 (v128, v128, v128) -> (v128){{$}} 597; CHECK-NEXT: i32x4.dot_i8x16_i7x16_add_s $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 598; CHECK-NEXT: return $pop[[R]]{{$}} 599declare <4 x i32> @llvm.wasm.dot.i8x16.i7x16.add.signed(<16 x i8>, <16 x i8>, 600 <4 x i32>) 601define <4 x i32> @dot_i8x16_i7x16_add_s_i32x4(<16 x i8> %a, <16 x i8> %b, 602 <4 x i32> %c) { 603 %v = call <4 x i32> @llvm.wasm.dot.i8x16.i7x16.add.signed( 604 <16 x i8> %a, <16 x i8> %b, <4 x i32> %c 605 ) 606 ret <4 x i32> %v 607} 608 609; ============================================================================== 610; 2 x i64 611; ============================================================================== 612; CHECK-LABEL: any_v2i64: 613; CHECK-NEXT: .functype any_v2i64 (v128) -> (i32){{$}} 614; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 615; CHECK-NEXT: return $pop[[R]]{{$}} 616declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>) 617define i32 @any_v2i64(<2 x i64> %x) { 618 %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x) 619 ret i32 %a 620} 621 622; CHECK-LABEL: all_v2i64: 623; CHECK-NEXT: .functype all_v2i64 (v128) -> (i32){{$}} 624; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}} 625; CHECK-NEXT: return $pop[[R]]{{$}} 626declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>) 627define i32 @all_v2i64(<2 x i64> %x) { 628 %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x) 629 ret i32 %a 630} 631 632; CHECK-LABEL: bitmask_v2i64: 633; CHECK-NEXT: .functype bitmask_v2i64 (v128) -> (i32){{$}} 634; CHECK-NEXT: i64x2.bitmask $push[[R:[0-9]+]]=, $0{{$}} 635; CHECK-NEXT: return $pop[[R]]{{$}} 636declare i32 @llvm.wasm.bitmask.v2i64(<2 x i64>) 637define i32 @bitmask_v2i64(<2 x i64> %x) { 638 %a = call i32 @llvm.wasm.bitmask.v2i64(<2 x i64> %x) 639 ret i32 %a 640} 641 642; CHECK-LABEL: bitselect_v2i64: 643; CHECK-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}} 644; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 645; CHECK-NEXT: return $pop[[R]]{{$}} 646declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 647define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) { 648 %a = call <2 x i64> @llvm.wasm.bitselect.v2i64( 649 <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c 650 ) 651 ret <2 x i64> %a 652} 653 654; CHECK-LABEL: laneselect_v2i64: 655; CHECK-NEXT: .functype laneselect_v2i64 (v128, v128, v128) -> (v128){{$}} 656; CHECK-NEXT: i64x2.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 657; CHECK-NEXT: return $pop[[R]]{{$}} 658declare <2 x i64> @llvm.wasm.laneselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 659define <2 x i64> @laneselect_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { 660 %v = call <2 x i64> @llvm.wasm.laneselect.v2i64( 661 <2 x i64> %a, <2 x i64> %b, <2 x i64> %c 662 ) 663 ret <2 x i64> %v 664} 665 666; ============================================================================== 667; 4 x f32 668; ============================================================================== 669; CHECK-LABEL: bitselect_v4f32: 670; CHECK-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}} 671; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 672; CHECK-NEXT: return $pop[[R]]{{$}} 673declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>) 674define <4 x float> @bitselect_v4f32(<4 x float> %v1, <4 x float> %v2, <4 x float> %c) { 675 %a = call <4 x float> @llvm.wasm.bitselect.v4f32( 676 <4 x float> %v1, <4 x float> %v2, <4 x float> %c 677 ) 678 ret <4 x float> %a 679} 680 681; CHECK-LABEL: pmin_v4f32: 682; CHECK-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}} 683; CHECK-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 684; CHECK-NEXT: return $pop[[R]]{{$}} 685declare <4 x float> @llvm.wasm.pmin.v4f32(<4 x float>, <4 x float>) 686define <4 x float> @pmin_v4f32(<4 x float> %a, <4 x float> %b) { 687 %v = call <4 x float> @llvm.wasm.pmin.v4f32(<4 x float> %a, <4 x float> %b) 688 ret <4 x float> %v 689} 690 691; CHECK-LABEL: pmax_v4f32: 692; CHECK-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}} 693; CHECK-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 694; CHECK-NEXT: return $pop[[R]]{{$}} 695declare <4 x float> @llvm.wasm.pmax.v4f32(<4 x float>, <4 x float>) 696define <4 x float> @pmax_v4f32(<4 x float> %a, <4 x float> %b) { 697 %v = call <4 x float> @llvm.wasm.pmax.v4f32(<4 x float> %a, <4 x float> %b) 698 ret <4 x float> %v 699} 700 701; CHECK-LABEL: ceil_v4f32: 702; CHECK-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}} 703; CHECK-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}} 704; CHECK-NEXT: return $pop[[R]]{{$}} 705declare <4 x float> @llvm.ceil.v4f32(<4 x float>) 706define <4 x float> @ceil_v4f32(<4 x float> %a) { 707 %v = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a) 708 ret <4 x float> %v 709} 710 711; CHECK-LABEL: floor_v4f32: 712; CHECK-NEXT: .functype floor_v4f32 (v128) -> (v128){{$}} 713; CHECK-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}} 714; CHECK-NEXT: return $pop[[R]]{{$}} 715declare <4 x float> @llvm.floor.v4f32(<4 x float>) 716define <4 x float> @floor_v4f32(<4 x float> %a) { 717 %v = call <4 x float> @llvm.floor.v4f32(<4 x float> %a) 718 ret <4 x float> %v 719} 720 721; CHECK-LABEL: trunc_v4f32: 722; CHECK-NEXT: .functype trunc_v4f32 (v128) -> (v128){{$}} 723; CHECK-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}} 724; CHECK-NEXT: return $pop[[R]]{{$}} 725declare <4 x float> @llvm.trunc.v4f32(<4 x float>) 726define <4 x float> @trunc_v4f32(<4 x float> %a) { 727 %v = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a) 728 ret <4 x float> %v 729} 730 731; CHECK-LABEL: nearest_v4f32: 732; CHECK-NEXT: .functype nearest_v4f32 (v128) -> (v128){{$}} 733; CHECK-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}} 734; CHECK-NEXT: return $pop[[R]]{{$}} 735declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) 736define <4 x float> @nearest_v4f32(<4 x float> %a) { 737 %v = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a) 738 ret <4 x float> %v 739} 740 741; CHECK-LABEL: fma_v4f32: 742; CHECK-NEXT: .functype fma_v4f32 (v128, v128, v128) -> (v128){{$}} 743; CHECK-NEXT: f32x4.relaxed_fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 744; CHECK-NEXT: return $pop[[R]]{{$}} 745declare <4 x float> @llvm.wasm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) 746define <4 x float> @fma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 747 %v = call <4 x float> @llvm.wasm.fma.v4f32( 748 <4 x float> %a, <4 x float> %b, <4 x float> %c 749 ) 750 ret <4 x float> %v 751} 752 753; CHECK-LABEL: fms_v4f32: 754; CHECK-NEXT: .functype fms_v4f32 (v128, v128, v128) -> (v128){{$}} 755; CHECK-NEXT: f32x4.relaxed_fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 756; CHECK-NEXT: return $pop[[R]]{{$}} 757declare <4 x float> @llvm.wasm.fms.v4f32(<4 x float>, <4 x float>, <4 x float>) 758define <4 x float> @fms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 759 %v = call <4 x float> @llvm.wasm.fms.v4f32( 760 <4 x float> %a, <4 x float> %b, <4 x float> %c 761 ) 762 ret <4 x float> %v 763} 764 765; CHECK-LABEL: relaxed_min_v4f32: 766; CHECK-NEXT: .functype relaxed_min_v4f32 (v128, v128) -> (v128){{$}} 767; CHECK-NEXT: f32x4.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}} 768; CHECK-NEXT: return $pop[[R]]{{$}} 769declare <4 x float> @llvm.wasm.relaxed.min.v4f32(<4 x float>, <4 x float>) 770define <4 x float> @relaxed_min_v4f32(<4 x float> %a, <4 x float> %b) { 771 %v = call <4 x float> @llvm.wasm.relaxed.min.v4f32( 772 <4 x float> %a, <4 x float> %b 773 ) 774 ret <4 x float> %v 775} 776 777; CHECK-LABEL: relaxed_max_v4f32: 778; CHECK-NEXT: .functype relaxed_max_v4f32 (v128, v128) -> (v128){{$}} 779; CHECK-NEXT: f32x4.relaxed_max $push[[R:[0-9]+]]=, $0, $1{{$}} 780; CHECK-NEXT: return $pop[[R]]{{$}} 781declare <4 x float> @llvm.wasm.relaxed.max.v4f32(<4 x float>, <4 x float>) 782define <4 x float> @relaxed_max_v4f32(<4 x float> %a, <4 x float> %b) { 783 %v = call <4 x float> @llvm.wasm.relaxed.max.v4f32( 784 <4 x float> %a, <4 x float> %b 785 ) 786 ret <4 x float> %v 787} 788 789; ============================================================================== 790; 2 x f64 791; ============================================================================== 792; CHECK-LABEL: bitselect_v2f64: 793; CHECK-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}} 794; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 795; CHECK-NEXT: return $pop[[R]]{{$}} 796declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>) 797define <2 x double> @bitselect_v2f64(<2 x double> %v1, <2 x double> %v2, <2 x double> %c) { 798 %a = call <2 x double> @llvm.wasm.bitselect.v2f64( 799 <2 x double> %v1, <2 x double> %v2, <2 x double> %c 800 ) 801 ret <2 x double> %a 802} 803 804; CHECK-LABEL: pmin_v2f64: 805; CHECK-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}} 806; CHECK-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 807; CHECK-NEXT: return $pop[[R]]{{$}} 808declare <2 x double> @llvm.wasm.pmin.v2f64(<2 x double>, <2 x double>) 809define <2 x double> @pmin_v2f64(<2 x double> %a, <2 x double> %b) { 810 %v = call <2 x double> @llvm.wasm.pmin.v2f64(<2 x double> %a, <2 x double> %b) 811 ret <2 x double> %v 812} 813 814; CHECK-LABEL: pmax_v2f64: 815; CHECK-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}} 816; CHECK-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 817; CHECK-NEXT: return $pop[[R]]{{$}} 818declare <2 x double> @llvm.wasm.pmax.v2f64(<2 x double>, <2 x double>) 819define <2 x double> @pmax_v2f64(<2 x double> %a, <2 x double> %b) { 820 %v = call <2 x double> @llvm.wasm.pmax.v2f64(<2 x double> %a, <2 x double> %b) 821 ret <2 x double> %v 822} 823 824; CHECK-LABEL: ceil_v2f64: 825; CHECK-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}} 826; CHECK-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}} 827; CHECK-NEXT: return $pop[[R]]{{$}} 828declare <2 x double> @llvm.ceil.v2f64(<2 x double>) 829define <2 x double> @ceil_v2f64(<2 x double> %a) { 830 %v = call <2 x double> @llvm.ceil.v2f64(<2 x double> %a) 831 ret <2 x double> %v 832} 833 834; CHECK-LABEL: floor_v2f64: 835; CHECK-NEXT: .functype floor_v2f64 (v128) -> (v128){{$}} 836; CHECK-NEXT: f64x2.floor $push[[R:[0-9]+]]=, $0{{$}} 837; CHECK-NEXT: return $pop[[R]]{{$}} 838declare <2 x double> @llvm.floor.v2f64(<2 x double>) 839define <2 x double> @floor_v2f64(<2 x double> %a) { 840 %v = call <2 x double> @llvm.floor.v2f64(<2 x double> %a) 841 ret <2 x double> %v 842} 843 844; CHECK-LABEL: trunc_v2f64: 845; CHECK-NEXT: .functype trunc_v2f64 (v128) -> (v128){{$}} 846; CHECK-NEXT: f64x2.trunc $push[[R:[0-9]+]]=, $0{{$}} 847; CHECK-NEXT: return $pop[[R]]{{$}} 848declare <2 x double> @llvm.trunc.v2f64(<2 x double>) 849define <2 x double> @trunc_v2f64(<2 x double> %a) { 850 %v = call <2 x double> @llvm.trunc.v2f64(<2 x double> %a) 851 ret <2 x double> %v 852} 853 854; CHECK-LABEL: nearest_v2f64: 855; CHECK-NEXT: .functype nearest_v2f64 (v128) -> (v128){{$}} 856; CHECK-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}} 857; CHECK-NEXT: return $pop[[R]]{{$}} 858declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) 859define <2 x double> @nearest_v2f64(<2 x double> %a) { 860 %v = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %a) 861 ret <2 x double> %v 862} 863 864; CHECK-LABEL: fma_v2f64: 865; CHECK-NEXT: .functype fma_v2f64 (v128, v128, v128) -> (v128){{$}} 866; CHECK-NEXT: f64x2.relaxed_fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 867; CHECK-NEXT: return $pop[[R]]{{$}} 868declare <2 x double> @llvm.wasm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) 869define <2 x double> @fma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 870 %v = call <2 x double> @llvm.wasm.fma.v2f64( 871 <2 x double> %a, <2 x double> %b, <2 x double> %c 872 ) 873 ret <2 x double> %v 874} 875 876; CHECK-LABEL: fms_v2f64: 877; CHECK-NEXT: .functype fms_v2f64 (v128, v128, v128) -> (v128){{$}} 878; CHECK-NEXT: f64x2.relaxed_fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 879; CHECK-NEXT: return $pop[[R]]{{$}} 880declare <2 x double> @llvm.wasm.fms.v2f64(<2 x double>, <2 x double>, <2 x double>) 881define <2 x double> @fms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 882 %v = call <2 x double> @llvm.wasm.fms.v2f64( 883 <2 x double> %a, <2 x double> %b, <2 x double> %c 884 ) 885 ret <2 x double> %v 886} 887 888; CHECK-LABEL: relaxed_min_v2f64: 889; CHECK-NEXT: .functype relaxed_min_v2f64 (v128, v128) -> (v128){{$}} 890; CHECK-NEXT: f64x2.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}} 891; CHECK-NEXT: return $pop[[R]]{{$}} 892declare <2 x double> @llvm.wasm.relaxed.min.v2f64(<2 x double>, <2 x double>) 893define <2 x double> @relaxed_min_v2f64(<2 x double> %a, <2 x double> %b) { 894 %v = call <2 x double> @llvm.wasm.relaxed.min.v2f64( 895 <2 x double> %a, <2 x double> %b 896 ) 897 ret <2 x double> %v 898} 899 900; CHECK-LABEL: relaxed_max_v2f64: 901; CHECK-NEXT: .functype relaxed_max_v2f64 (v128, v128) -> (v128){{$}} 902; CHECK-NEXT: f64x2.relaxed_max $push[[R:[0-9]+]]=, $0, $1{{$}} 903; CHECK-NEXT: return $pop[[R]]{{$}} 904declare <2 x double> @llvm.wasm.relaxed.max.v2f64(<2 x double>, <2 x double>) 905define <2 x double> @relaxed_max_v2f64(<2 x double> %a, <2 x double> %b) { 906 %v = call <2 x double> @llvm.wasm.relaxed.max.v2f64( 907 <2 x double> %a, <2 x double> %b 908 ) 909 ret <2 x double> %v 910} 911