1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd | FileCheck %s --check-prefixes=CHECK,SLOW 2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd -fast-isel | FileCheck %s 3 4; Test that SIMD128 intrinsics lower as expected. These intrinsics are 5; only expected to lower successfully if the simd128 attribute is 6; enabled and legal types are used. 7 8target triple = "wasm32-unknown-unknown" 9 10; ============================================================================== 11; 16 x i8 12; ============================================================================== 13; CHECK-LABEL: swizzle_v16i8: 14; CHECK-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}} 15; CHECK-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}} 16; CHECK-NEXT: return $pop[[R]]{{$}} 17declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>) 18define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) { 19 %a = call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y) 20 ret <16 x i8> %a 21} 22 23; CHECK-LABEL: add_sat_s_v16i8: 24; CHECK-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}} 25; CHECK-NEXT: i8x16.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 26; CHECK-NEXT: return $pop[[R]]{{$}} 27declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>) 28define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 29 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 30 ret <16 x i8> %a 31} 32 33; CHECK-LABEL: add_sat_u_v16i8: 34; CHECK-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}} 35; CHECK-NEXT: i8x16.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 36; CHECK-NEXT: return $pop[[R]]{{$}} 37declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) 38define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 39 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 40 ret <16 x i8> %a 41} 42 43; CHECK-LABEL: sub_sat_s_v16i8: 44; CHECK-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}} 45; CHECK-NEXT: i8x16.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 46; CHECK-NEXT: return $pop[[R]]{{$}} 47declare <16 x i8> @llvm.wasm.sub.sat.signed.v16i8(<16 x i8>, <16 x i8>) 48define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 49 %a = call <16 x i8> @llvm.wasm.sub.sat.signed.v16i8( 50 <16 x i8> %x, <16 x i8> %y 51 ) 52 ret <16 x i8> %a 53} 54 55; CHECK-LABEL: sub_sat_u_v16i8: 56; CHECK-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}} 57; CHECK-NEXT: i8x16.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 58; CHECK-NEXT: return $pop[[R]]{{$}} 59declare <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8(<16 x i8>, <16 x i8>) 60define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 61 %a = call <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8( 62 <16 x i8> %x, <16 x i8> %y 63 ) 64 ret <16 x i8> %a 65} 66 67; CHECK-LABEL: avgr_u_v16i8: 68; CHECK-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}} 69; CHECK-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 70; CHECK-NEXT: return $pop[[R]]{{$}} 71declare <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8>, <16 x i8>) 72define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 73 %a = call <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y) 74 ret <16 x i8> %a 75} 76 77; CHECK-LABEL: popcnt_v16i8: 78; CHECK-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}} 79; CHECK-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}} 80; CHECK-NEXT: return $pop[[R]]{{$}} 81declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) 82define <16 x i8> @popcnt_v16i8(<16 x i8> %x) { 83 %a = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %x) 84 ret <16 x i8> %a 85} 86 87; CHECK-LABEL: any_v16i8: 88; CHECK-NEXT: .functype any_v16i8 (v128) -> (i32){{$}} 89; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 90; CHECK-NEXT: return $pop[[R]]{{$}} 91declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>) 92define i32 @any_v16i8(<16 x i8> %x) { 93 %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x) 94 ret i32 %a 95} 96 97; CHECK-LABEL: all_v16i8: 98; CHECK-NEXT: .functype all_v16i8 (v128) -> (i32){{$}} 99; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}} 100; CHECK-NEXT: return $pop[[R]]{{$}} 101declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>) 102define i32 @all_v16i8(<16 x i8> %x) { 103 %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x) 104 ret i32 %a 105} 106 107; CHECK-LABEL: bitmask_v16i8: 108; CHECK-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}} 109; CHECK-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}} 110; CHECK-NEXT: return $pop[[R]]{{$}} 111declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>) 112define i32 @bitmask_v16i8(<16 x i8> %x) { 113 %a = call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x) 114 ret i32 %a 115} 116 117; CHECK-LABEL: bitselect_v16i8: 118; CHECK-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}} 119; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 120; CHECK-NEXT: return $pop[[R]]{{$}} 121declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 122define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) { 123 %a = call <16 x i8> @llvm.wasm.bitselect.v16i8( 124 <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c 125 ) 126 ret <16 x i8> %a 127} 128 129; CHECK-LABEL: narrow_signed_v16i8: 130; CHECK-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}} 131; CHECK-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 132; CHECK-NEXT: return $pop[[R]]{{$}} 133declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>) 134define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) { 135 %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16( 136 <8 x i16> %low, <8 x i16> %high 137 ) 138 ret <16 x i8> %a 139} 140 141; CHECK-LABEL: narrow_unsigned_v16i8: 142; CHECK-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}} 143; CHECK-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 144; CHECK-NEXT: return $pop[[R]]{{$}} 145declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>) 146define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) { 147 %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16( 148 <8 x i16> %low, <8 x i16> %high 149 ) 150 ret <16 x i8> %a 151} 152 153; CHECK-LABEL: shuffle_v16i8: 154; NO-CHECK-NOT: i8x16 155; CHECK-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}} 156; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 157; CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}} 158; CHECK-NEXT: return $pop[[R]]{{$}} 159declare <16 x i8> @llvm.wasm.shuffle( 160 <16 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, 161 i32, i32, i32, i32, i32) 162define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) { 163 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 164 i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, 165 i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 35) 166 ret <16 x i8> %res 167} 168 169; CHECK-LABEL: shuffle_undef_v16i8: 170; NO-CHECK-NOT: i8x16 171; CHECK-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}} 172; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 173; CHECK-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}} 174; CHECK-NEXT: return $pop[[R]]{{$}} 175define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) { 176 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 177 i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 178 i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 179 i32 undef, i32 undef, i32 undef, i32 2) 180 ret <16 x i8> %res 181} 182 183; CHECK-LABEL: laneselect_v16i8: 184; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}} 185; CHECK-NEXT: i8x16.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 186; CHECK-NEXT: return $pop[[R]]{{$}} 187declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 188define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 189 %v = call <16 x i8> @llvm.wasm.laneselect.v16i8( 190 <16 x i8> %a, <16 x i8> %b, <16 x i8> %c 191 ) 192 ret <16 x i8> %v 193} 194 195; CHECK-LABEL: relaxed_swizzle_v16i8: 196; CHECK-NEXT: .functype relaxed_swizzle_v16i8 (v128, v128) -> (v128){{$}} 197; CHECK-NEXT: i8x16.relaxed_swizzle $push[[R:[0-9]+]]=, $0, $1{{$}} 198; CHECK-NEXT: return $pop[[R]]{{$}} 199declare <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8>, <16 x i8>) 200define <16 x i8> @relaxed_swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) { 201 %a = call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y) 202 ret <16 x i8> %a 203} 204 205; ============================================================================== 206; 8 x i16 207; ============================================================================== 208; CHECK-LABEL: add_sat_s_v8i16: 209; CHECK-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}} 210; CHECK-NEXT: i16x8.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 211; CHECK-NEXT: return $pop[[R]]{{$}} 212declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) 213define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 214 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 215 ret <8 x i16> %a 216} 217 218; CHECK-LABEL: add_sat_u_v8i16: 219; CHECK-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}} 220; CHECK-NEXT: i16x8.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 221; CHECK-NEXT: return $pop[[R]]{{$}} 222declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>) 223define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 224 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 225 ret <8 x i16> %a 226} 227 228; CHECK-LABEL: sub_sat_s_v8i16: 229; CHECK-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}} 230; CHECK-NEXT: i16x8.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 231; CHECK-NEXT: return $pop[[R]]{{$}} 232declare <8 x i16> @llvm.wasm.sub.sat.signed.v8i16(<8 x i16>, <8 x i16>) 233define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 234 %a = call <8 x i16> @llvm.wasm.sub.sat.signed.v8i16( 235 <8 x i16> %x, <8 x i16> %y 236 ) 237 ret <8 x i16> %a 238} 239 240; CHECK-LABEL: sub_sat_u_v8i16: 241; CHECK-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}} 242; CHECK-NEXT: i16x8.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 243; CHECK-NEXT: return $pop[[R]]{{$}} 244declare <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16(<8 x i16>, <8 x i16>) 245define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 246 %a = call <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16( 247 <8 x i16> %x, <8 x i16> %y 248 ) 249 ret <8 x i16> %a 250} 251 252; CHECK-LABEL: avgr_u_v8i16: 253; CHECK-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}} 254; CHECK-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 255; CHECK-NEXT: return $pop[[R]]{{$}} 256declare <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16>, <8 x i16>) 257define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 258 %a = call <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y) 259 ret <8 x i16> %a 260} 261 262; CHECK-LABEL: q15mulr_sat_s_v8i16: 263; CHECK-NEXT: .functype q15mulr_sat_s_v8i16 (v128, v128) -> (v128){{$}} 264; CHECK-NEXT: i16x8.q15mulr_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 265; CHECK-NEXT: return $pop[[R]]{{$}} 266declare <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16>, <8 x i16>) 267define <8 x i16> @q15mulr_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 268 %a = call <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16> %x, 269 <8 x i16> %y) 270 ret <8 x i16> %a 271} 272 273; CHECK-LABEL: extadd_pairwise_s_v8i16: 274; CHECK-NEXT: .functype extadd_pairwise_s_v8i16 (v128) -> (v128){{$}} 275; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_s $push[[R:[0-9]+]]=, $0{{$}} 276; CHECK-NEXT: return $pop[[R]]{{$}} 277declare <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8>) 278define <8 x i16> @extadd_pairwise_s_v8i16(<16 x i8> %x) { 279 %a = call <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8> %x) 280 ret <8 x i16> %a 281} 282 283; CHECK-LABEL: extadd_pairwise_u_v8i16: 284; CHECK-NEXT: .functype extadd_pairwise_u_v8i16 (v128) -> (v128){{$}} 285; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_u $push[[R:[0-9]+]]=, $0{{$}} 286; CHECK-NEXT: return $pop[[R]]{{$}} 287declare <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8>) 288define <8 x i16> @extadd_pairwise_u_v8i16(<16 x i8> %x) { 289 %a = call <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8> %x) 290 ret <8 x i16> %a 291} 292 293; CHECK-LABEL: any_v8i16: 294; CHECK-NEXT: .functype any_v8i16 (v128) -> (i32){{$}} 295; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 296; CHECK-NEXT: return $pop[[R]]{{$}} 297declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>) 298define i32 @any_v8i16(<8 x i16> %x) { 299 %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x) 300 ret i32 %a 301} 302 303; CHECK-LABEL: all_v8i16: 304; CHECK-NEXT: .functype all_v8i16 (v128) -> (i32){{$}} 305; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}} 306; CHECK-NEXT: return $pop[[R]]{{$}} 307declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>) 308define i32 @all_v8i16(<8 x i16> %x) { 309 %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x) 310 ret i32 %a 311} 312 313; CHECK-LABEL: bitmask_v8i16: 314; CHECK-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}} 315; CHECK-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}} 316; CHECK-NEXT: return $pop[[R]]{{$}} 317declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>) 318define i32 @bitmask_v8i16(<8 x i16> %x) { 319 %a = call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x) 320 ret i32 %a 321} 322 323; CHECK-LABEL: bitselect_v8i16: 324; CHECK-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}} 325; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 326; CHECK-NEXT: return $pop[[R]]{{$}} 327declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 328define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) { 329 %a = call <8 x i16> @llvm.wasm.bitselect.v8i16( 330 <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c 331 ) 332 ret <8 x i16> %a 333} 334 335; CHECK-LABEL: narrow_signed_v8i16: 336; CHECK-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}} 337; CHECK-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 338; CHECK-NEXT: return $pop[[R]]{{$}} 339declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>) 340define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) { 341 %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32( 342 <4 x i32> %low, <4 x i32> %high 343 ) 344 ret <8 x i16> %a 345} 346 347; CHECK-LABEL: narrow_unsigned_v8i16: 348; CHECK-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}} 349; CHECK-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 350; CHECK-NEXT: return $pop[[R]]{{$}} 351declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>) 352define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) { 353 %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32( 354 <4 x i32> %low, <4 x i32> %high 355 ) 356 ret <8 x i16> %a 357} 358 359; CHECK-LABEL: laneselect_v8i16: 360; CHECK-NEXT: .functype laneselect_v8i16 (v128, v128, v128) -> (v128){{$}} 361; CHECK-NEXT: i16x8.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 362; CHECK-NEXT: return $pop[[R]]{{$}} 363declare <8 x i16> @llvm.wasm.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 364define <8 x i16> @laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 365 %v = call <8 x i16> @llvm.wasm.laneselect.v8i16( 366 <8 x i16> %a, <8 x i16> %b, <8 x i16> %c 367 ) 368 ret <8 x i16> %v 369} 370 371; ============================================================================== 372; 4 x i32 373; ============================================================================== 374; CHECK-LABEL: dot: 375; CHECK-NEXT: .functype dot (v128, v128) -> (v128){{$}} 376; CHECK-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 377; CHECK-NEXT: return $pop[[R]]{{$}} 378declare <4 x i32> @llvm.wasm.dot(<8 x i16>, <8 x i16>) 379define <4 x i32> @dot(<8 x i16> %x, <8 x i16> %y) { 380 %a = call <4 x i32> @llvm.wasm.dot(<8 x i16> %x, <8 x i16> %y) 381 ret <4 x i32> %a 382} 383 384; CHECK-LABEL: extadd_pairwise_s_v4i32: 385; CHECK-NEXT: .functype extadd_pairwise_s_v4i32 (v128) -> (v128){{$}} 386; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_s $push[[R:[0-9]+]]=, $0{{$}} 387; CHECK-NEXT: return $pop[[R]]{{$}} 388declare <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16>) 389define <4 x i32> @extadd_pairwise_s_v4i32(<8 x i16> %x) { 390 %a = call <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16> %x) 391 ret <4 x i32> %a 392} 393 394; CHECK-LABEL: extadd_pairwise_u_v4i32: 395; CHECK-NEXT: .functype extadd_pairwise_u_v4i32 (v128) -> (v128){{$}} 396; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_u $push[[R:[0-9]+]]=, $0{{$}} 397; CHECK-NEXT: return $pop[[R]]{{$}} 398declare <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16>) 399define <4 x i32> @extadd_pairwise_u_v4i32(<8 x i16> %x) { 400 %a = call <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16> %x) 401 ret <4 x i32> %a 402} 403 404 405; CHECK-LABEL: any_v4i32: 406; CHECK-NEXT: .functype any_v4i32 (v128) -> (i32){{$}} 407; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 408; CHECK-NEXT: return $pop[[R]]{{$}} 409declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>) 410define i32 @any_v4i32(<4 x i32> %x) { 411 %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x) 412 ret i32 %a 413} 414 415; CHECK-LABEL: all_v4i32: 416; CHECK-NEXT: .functype all_v4i32 (v128) -> (i32){{$}} 417; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}} 418; CHECK-NEXT: return $pop[[R]]{{$}} 419declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>) 420define i32 @all_v4i32(<4 x i32> %x) { 421 %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x) 422 ret i32 %a 423} 424 425; CHECK-LABEL: bitmask_v4i32: 426; CHECK-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}} 427; CHECK-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}} 428; CHECK-NEXT: return $pop[[R]]{{$}} 429declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>) 430define i32 @bitmask_v4i32(<4 x i32> %x) { 431 %a = call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x) 432 ret i32 %a 433} 434 435; CHECK-LABEL: bitselect_v4i32: 436; CHECK-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}} 437; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 438; CHECK-NEXT: return $pop[[R]]{{$}} 439declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 440define <4 x i32> @bitselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) { 441 %a = call <4 x i32> @llvm.wasm.bitselect.v4i32( 442 <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c 443 ) 444 ret <4 x i32> %a 445} 446 447; CHECK-LABEL: trunc_sat_s_v4i32: 448; NO-CHECK-NOT: f32x4 449; CHECK-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}} 450; CHECK-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0 451; CHECK-NEXT: return $pop[[R]] 452declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float>) 453define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) { 454 %a = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %x) 455 ret <4 x i32> %a 456} 457 458; CHECK-LABEL: trunc_sat_u_v4i32: 459; NO-CHECK-NOT: f32x4 460; CHECK-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}} 461; CHECK-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0 462; CHECK-NEXT: return $pop[[R]] 463declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float>) 464define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) { 465 %a = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %x) 466 ret <4 x i32> %a 467} 468 469; CHECK-LABEL: trunc_sat_zero_s_v4i32: 470; CHECK-NEXT: .functype trunc_sat_zero_s_v4i32 (v128) -> (v128){{$}} 471; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}} 472; CHECK-NEXT: return $pop[[R]]{{$}} 473declare <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double>) 474define <4 x i32> @trunc_sat_zero_s_v4i32(<2 x double> %x) { 475 %v = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %x) 476 %a = shufflevector <2 x i32> %v, <2 x i32> <i32 0, i32 0>, 477 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 478 ret <4 x i32> %a 479} 480 481; CHECK-LABEL: trunc_sat_zero_s_v4i32_2: 482; CHECK-NEXT: .functype trunc_sat_zero_s_v4i32_2 (v128) -> (v128){{$}} 483; SLOW-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}} 484; SLOW-NEXT: return $pop[[R]]{{$}} 485declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double>) 486define <4 x i32> @trunc_sat_zero_s_v4i32_2(<2 x double> %x) { 487 %v = shufflevector <2 x double> %x, <2 x double> zeroinitializer, 488 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 489 %a = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double> %v) 490 ret <4 x i32> %a 491} 492 493; CHECK-LABEL: trunc_sat_zero_u_v4i32: 494; CHECK-NEXT: .functype trunc_sat_zero_u_v4i32 (v128) -> (v128){{$}} 495; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}} 496; CHECK-NEXT: return $pop[[R]]{{$}} 497declare <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double>) 498define <4 x i32> @trunc_sat_zero_u_v4i32(<2 x double> %x) { 499 %v = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %x) 500 %a = shufflevector <2 x i32> %v, <2 x i32> <i32 0, i32 0>, 501 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 502 ret <4 x i32> %a 503} 504 505; CHECK-LABEL: trunc_sat_zero_u_v4i32_2: 506; CHECK-NEXT: .functype trunc_sat_zero_u_v4i32_2 (v128) -> (v128){{$}} 507; SLOW-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}} 508; SLOW-NEXT: return $pop[[R]]{{$}} 509declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double>) 510define <4 x i32> @trunc_sat_zero_u_v4i32_2(<2 x double> %x) { 511 %v = shufflevector <2 x double> %x, <2 x double> zeroinitializer, 512 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 513 %a = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double> %v) 514 ret <4 x i32> %a 515} 516 517; CHECK-LABEL: laneselect_v4i32: 518; CHECK-NEXT: .functype laneselect_v4i32 (v128, v128, v128) -> (v128){{$}} 519; CHECK-NEXT: i32x4.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 520; CHECK-NEXT: return $pop[[R]]{{$}} 521declare <4 x i32> @llvm.wasm.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 522define <4 x i32> @laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 523 %v = call <4 x i32> @llvm.wasm.laneselect.v4i32( 524 <4 x i32> %a, <4 x i32> %b, <4 x i32> %c 525 ) 526 ret <4 x i32> %v 527} 528 529; ============================================================================== 530; 2 x i64 531; ============================================================================== 532; CHECK-LABEL: any_v2i64: 533; CHECK-NEXT: .functype any_v2i64 (v128) -> (i32){{$}} 534; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 535; CHECK-NEXT: return $pop[[R]]{{$}} 536declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>) 537define i32 @any_v2i64(<2 x i64> %x) { 538 %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x) 539 ret i32 %a 540} 541 542; CHECK-LABEL: all_v2i64: 543; CHECK-NEXT: .functype all_v2i64 (v128) -> (i32){{$}} 544; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}} 545; CHECK-NEXT: return $pop[[R]]{{$}} 546declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>) 547define i32 @all_v2i64(<2 x i64> %x) { 548 %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x) 549 ret i32 %a 550} 551 552; CHECK-LABEL: bitmask_v2i64: 553; CHECK-NEXT: .functype bitmask_v2i64 (v128) -> (i32){{$}} 554; CHECK-NEXT: i64x2.bitmask $push[[R:[0-9]+]]=, $0{{$}} 555; CHECK-NEXT: return $pop[[R]]{{$}} 556declare i32 @llvm.wasm.bitmask.v2i64(<2 x i64>) 557define i32 @bitmask_v2i64(<2 x i64> %x) { 558 %a = call i32 @llvm.wasm.bitmask.v2i64(<2 x i64> %x) 559 ret i32 %a 560} 561 562; CHECK-LABEL: bitselect_v2i64: 563; CHECK-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}} 564; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 565; CHECK-NEXT: return $pop[[R]]{{$}} 566declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 567define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) { 568 %a = call <2 x i64> @llvm.wasm.bitselect.v2i64( 569 <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c 570 ) 571 ret <2 x i64> %a 572} 573 574; CHECK-LABEL: laneselect_v2i64: 575; CHECK-NEXT: .functype laneselect_v2i64 (v128, v128, v128) -> (v128){{$}} 576; CHECK-NEXT: i64x2.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 577; CHECK-NEXT: return $pop[[R]]{{$}} 578declare <2 x i64> @llvm.wasm.laneselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 579define <2 x i64> @laneselect_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { 580 %v = call <2 x i64> @llvm.wasm.laneselect.v2i64( 581 <2 x i64> %a, <2 x i64> %b, <2 x i64> %c 582 ) 583 ret <2 x i64> %v 584} 585 586; ============================================================================== 587; 4 x f32 588; ============================================================================== 589; CHECK-LABEL: bitselect_v4f32: 590; CHECK-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}} 591; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 592; CHECK-NEXT: return $pop[[R]]{{$}} 593declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>) 594define <4 x float> @bitselect_v4f32(<4 x float> %v1, <4 x float> %v2, <4 x float> %c) { 595 %a = call <4 x float> @llvm.wasm.bitselect.v4f32( 596 <4 x float> %v1, <4 x float> %v2, <4 x float> %c 597 ) 598 ret <4 x float> %a 599} 600 601; CHECK-LABEL: pmin_v4f32: 602; CHECK-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}} 603; CHECK-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 604; CHECK-NEXT: return $pop[[R]]{{$}} 605declare <4 x float> @llvm.wasm.pmin.v4f32(<4 x float>, <4 x float>) 606define <4 x float> @pmin_v4f32(<4 x float> %a, <4 x float> %b) { 607 %v = call <4 x float> @llvm.wasm.pmin.v4f32(<4 x float> %a, <4 x float> %b) 608 ret <4 x float> %v 609} 610 611; CHECK-LABEL: pmax_v4f32: 612; CHECK-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}} 613; CHECK-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 614; CHECK-NEXT: return $pop[[R]]{{$}} 615declare <4 x float> @llvm.wasm.pmax.v4f32(<4 x float>, <4 x float>) 616define <4 x float> @pmax_v4f32(<4 x float> %a, <4 x float> %b) { 617 %v = call <4 x float> @llvm.wasm.pmax.v4f32(<4 x float> %a, <4 x float> %b) 618 ret <4 x float> %v 619} 620 621; CHECK-LABEL: ceil_v4f32: 622; CHECK-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}} 623; CHECK-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}} 624; CHECK-NEXT: return $pop[[R]]{{$}} 625declare <4 x float> @llvm.ceil.v4f32(<4 x float>) 626define <4 x float> @ceil_v4f32(<4 x float> %a) { 627 %v = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a) 628 ret <4 x float> %v 629} 630 631; CHECK-LABEL: floor_v4f32: 632; CHECK-NEXT: .functype floor_v4f32 (v128) -> (v128){{$}} 633; CHECK-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}} 634; CHECK-NEXT: return $pop[[R]]{{$}} 635declare <4 x float> @llvm.floor.v4f32(<4 x float>) 636define <4 x float> @floor_v4f32(<4 x float> %a) { 637 %v = call <4 x float> @llvm.floor.v4f32(<4 x float> %a) 638 ret <4 x float> %v 639} 640 641; CHECK-LABEL: trunc_v4f32: 642; CHECK-NEXT: .functype trunc_v4f32 (v128) -> (v128){{$}} 643; CHECK-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}} 644; CHECK-NEXT: return $pop[[R]]{{$}} 645declare <4 x float> @llvm.trunc.v4f32(<4 x float>) 646define <4 x float> @trunc_v4f32(<4 x float> %a) { 647 %v = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a) 648 ret <4 x float> %v 649} 650 651; CHECK-LABEL: nearest_v4f32: 652; CHECK-NEXT: .functype nearest_v4f32 (v128) -> (v128){{$}} 653; CHECK-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}} 654; CHECK-NEXT: return $pop[[R]]{{$}} 655declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) 656define <4 x float> @nearest_v4f32(<4 x float> %a) { 657 %v = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a) 658 ret <4 x float> %v 659} 660 661; CHECK-LABEL: fma_v4f32: 662; CHECK-NEXT: .functype fma_v4f32 (v128, v128, v128) -> (v128){{$}} 663; CHECK-NEXT: f32x4.fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 664; CHECK-NEXT: return $pop[[R]]{{$}} 665declare <4 x float> @llvm.wasm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) 666define <4 x float> @fma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 667 %v = call <4 x float> @llvm.wasm.fma.v4f32( 668 <4 x float> %a, <4 x float> %b, <4 x float> %c 669 ) 670 ret <4 x float> %v 671} 672 673; CHECK-LABEL: fms_v4f32: 674; CHECK-NEXT: .functype fms_v4f32 (v128, v128, v128) -> (v128){{$}} 675; CHECK-NEXT: f32x4.fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 676; CHECK-NEXT: return $pop[[R]]{{$}} 677declare <4 x float> @llvm.wasm.fms.v4f32(<4 x float>, <4 x float>, <4 x float>) 678define <4 x float> @fms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 679 %v = call <4 x float> @llvm.wasm.fms.v4f32( 680 <4 x float> %a, <4 x float> %b, <4 x float> %c 681 ) 682 ret <4 x float> %v 683} 684 685; CHECK-LABEL: relaxed_min_v4f32: 686; CHECK-NEXT: .functype relaxed_min_v4f32 (v128, v128) -> (v128){{$}} 687; CHECK-NEXT: f32x4.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}} 688; CHECK-NEXT: return $pop[[R]]{{$}} 689declare <4 x float> @llvm.wasm.relaxed.min.v4f32(<4 x float>, <4 x float>) 690define <4 x float> @relaxed_min_v4f32(<4 x float> %a, <4 x float> %b) { 691 %v = call <4 x float> @llvm.wasm.relaxed.min.v4f32( 692 <4 x float> %a, <4 x float> %b 693 ) 694 ret <4 x float> %v 695} 696 697; CHECK-LABEL: relaxed_max_v4f32: 698; CHECK-NEXT: .functype relaxed_max_v4f32 (v128, v128) -> (v128){{$}} 699; CHECK-NEXT: f32x4.relaxed_max $push[[R:[0-9]+]]=, $0, $1{{$}} 700; CHECK-NEXT: return $pop[[R]]{{$}} 701declare <4 x float> @llvm.wasm.relaxed.max.v4f32(<4 x float>, <4 x float>) 702define <4 x float> @relaxed_max_v4f32(<4 x float> %a, <4 x float> %b) { 703 %v = call <4 x float> @llvm.wasm.relaxed.max.v4f32( 704 <4 x float> %a, <4 x float> %b 705 ) 706 ret <4 x float> %v 707} 708 709; ============================================================================== 710; 2 x f64 711; ============================================================================== 712; CHECK-LABEL: bitselect_v2f64: 713; CHECK-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}} 714; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 715; CHECK-NEXT: return $pop[[R]]{{$}} 716declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>) 717define <2 x double> @bitselect_v2f64(<2 x double> %v1, <2 x double> %v2, <2 x double> %c) { 718 %a = call <2 x double> @llvm.wasm.bitselect.v2f64( 719 <2 x double> %v1, <2 x double> %v2, <2 x double> %c 720 ) 721 ret <2 x double> %a 722} 723 724; CHECK-LABEL: pmin_v2f64: 725; CHECK-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}} 726; CHECK-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 727; CHECK-NEXT: return $pop[[R]]{{$}} 728declare <2 x double> @llvm.wasm.pmin.v2f64(<2 x double>, <2 x double>) 729define <2 x double> @pmin_v2f64(<2 x double> %a, <2 x double> %b) { 730 %v = call <2 x double> @llvm.wasm.pmin.v2f64(<2 x double> %a, <2 x double> %b) 731 ret <2 x double> %v 732} 733 734; CHECK-LABEL: pmax_v2f64: 735; CHECK-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}} 736; CHECK-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 737; CHECK-NEXT: return $pop[[R]]{{$}} 738declare <2 x double> @llvm.wasm.pmax.v2f64(<2 x double>, <2 x double>) 739define <2 x double> @pmax_v2f64(<2 x double> %a, <2 x double> %b) { 740 %v = call <2 x double> @llvm.wasm.pmax.v2f64(<2 x double> %a, <2 x double> %b) 741 ret <2 x double> %v 742} 743 744; CHECK-LABEL: ceil_v2f64: 745; CHECK-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}} 746; CHECK-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}} 747; CHECK-NEXT: return $pop[[R]]{{$}} 748declare <2 x double> @llvm.ceil.v2f64(<2 x double>) 749define <2 x double> @ceil_v2f64(<2 x double> %a) { 750 %v = call <2 x double> @llvm.ceil.v2f64(<2 x double> %a) 751 ret <2 x double> %v 752} 753 754; CHECK-LABEL: floor_v2f64: 755; CHECK-NEXT: .functype floor_v2f64 (v128) -> (v128){{$}} 756; CHECK-NEXT: f64x2.floor $push[[R:[0-9]+]]=, $0{{$}} 757; CHECK-NEXT: return $pop[[R]]{{$}} 758declare <2 x double> @llvm.floor.v2f64(<2 x double>) 759define <2 x double> @floor_v2f64(<2 x double> %a) { 760 %v = call <2 x double> @llvm.floor.v2f64(<2 x double> %a) 761 ret <2 x double> %v 762} 763 764; CHECK-LABEL: trunc_v2f64: 765; CHECK-NEXT: .functype trunc_v2f64 (v128) -> (v128){{$}} 766; CHECK-NEXT: f64x2.trunc $push[[R:[0-9]+]]=, $0{{$}} 767; CHECK-NEXT: return $pop[[R]]{{$}} 768declare <2 x double> @llvm.trunc.v2f64(<2 x double>) 769define <2 x double> @trunc_v2f64(<2 x double> %a) { 770 %v = call <2 x double> @llvm.trunc.v2f64(<2 x double> %a) 771 ret <2 x double> %v 772} 773 774; CHECK-LABEL: nearest_v2f64: 775; CHECK-NEXT: .functype nearest_v2f64 (v128) -> (v128){{$}} 776; CHECK-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}} 777; CHECK-NEXT: return $pop[[R]]{{$}} 778declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) 779define <2 x double> @nearest_v2f64(<2 x double> %a) { 780 %v = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %a) 781 ret <2 x double> %v 782} 783 784; CHECK-LABEL: fma_v2f64: 785; CHECK-NEXT: .functype fma_v2f64 (v128, v128, v128) -> (v128){{$}} 786; CHECK-NEXT: f64x2.fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 787; CHECK-NEXT: return $pop[[R]]{{$}} 788declare <2 x double> @llvm.wasm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) 789define <2 x double> @fma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 790 %v = call <2 x double> @llvm.wasm.fma.v2f64( 791 <2 x double> %a, <2 x double> %b, <2 x double> %c 792 ) 793 ret <2 x double> %v 794} 795 796; CHECK-LABEL: fms_v2f64: 797; CHECK-NEXT: .functype fms_v2f64 (v128, v128, v128) -> (v128){{$}} 798; CHECK-NEXT: f64x2.fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 799; CHECK-NEXT: return $pop[[R]]{{$}} 800declare <2 x double> @llvm.wasm.fms.v2f64(<2 x double>, <2 x double>, <2 x double>) 801define <2 x double> @fms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 802 %v = call <2 x double> @llvm.wasm.fms.v2f64( 803 <2 x double> %a, <2 x double> %b, <2 x double> %c 804 ) 805 ret <2 x double> %v 806} 807 808; CHECK-LABEL: relaxed_min_v2f64: 809; CHECK-NEXT: .functype relaxed_min_v2f64 (v128, v128) -> (v128){{$}} 810; CHECK-NEXT: f64x2.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}} 811; CHECK-NEXT: return $pop[[R]]{{$}} 812declare <2 x double> @llvm.wasm.relaxed.min.v2f64(<2 x double>, <2 x double>) 813define <2 x double> @relaxed_min_v2f64(<2 x double> %a, <2 x double> %b) { 814 %v = call <2 x double> @llvm.wasm.relaxed.min.v2f64( 815 <2 x double> %a, <2 x double> %b 816 ) 817 ret <2 x double> %v 818} 819 820; CHECK-LABEL: relaxed_max_v2f64: 821; CHECK-NEXT: .functype relaxed_max_v2f64 (v128, v128) -> (v128){{$}} 822; CHECK-NEXT: f64x2.relaxed_max $push[[R:[0-9]+]]=, $0, $1{{$}} 823; CHECK-NEXT: return $pop[[R]]{{$}} 824declare <2 x double> @llvm.wasm.relaxed.max.v2f64(<2 x double>, <2 x double>) 825define <2 x double> @relaxed_max_v2f64(<2 x double> %a, <2 x double> %b) { 826 %v = call <2 x double> @llvm.wasm.relaxed.max.v2f64( 827 <2 x double> %a, <2 x double> %b 828 ) 829 ret <2 x double> %v 830} 831