1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s 2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s 3 4; Test that SIMD128 intrinsics lower as expected. These intrinsics are 5; only expected to lower successfully if the simd128 attribute is 6; enabled and legal types are used. 7 8target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" 9target triple = "wasm32-unknown-unknown" 10 11; ============================================================================== 12; 16 x i8 13; ============================================================================== 14; CHECK-LABEL: swizzle_v16i8: 15; CHECK-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}} 16; CHECK-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}} 17; CHECK-NEXT: return $pop[[R]]{{$}} 18declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>) 19define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) { 20 %a = call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y) 21 ret <16 x i8> %a 22} 23 24; CHECK-LABEL: add_sat_s_v16i8: 25; CHECK-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}} 26; CHECK-NEXT: i8x16.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 27; CHECK-NEXT: return $pop[[R]]{{$}} 28declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>) 29define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 30 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 31 ret <16 x i8> %a 32} 33 34; CHECK-LABEL: add_sat_u_v16i8: 35; CHECK-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}} 36; CHECK-NEXT: i8x16.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 37; CHECK-NEXT: return $pop[[R]]{{$}} 38declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) 39define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 40 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 41 ret <16 x i8> %a 42} 43 44; CHECK-LABEL: sub_sat_s_v16i8: 45; CHECK-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}} 46; CHECK-NEXT: i8x16.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 47; CHECK-NEXT: return $pop[[R]]{{$}} 48declare <16 x i8> @llvm.wasm.sub.sat.signed.v16i8(<16 x i8>, <16 x i8>) 49define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 50 %a = call <16 x i8> @llvm.wasm.sub.sat.signed.v16i8( 51 <16 x i8> %x, <16 x i8> %y 52 ) 53 ret <16 x i8> %a 54} 55 56; CHECK-LABEL: sub_sat_u_v16i8: 57; CHECK-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}} 58; CHECK-NEXT: i8x16.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 59; CHECK-NEXT: return $pop[[R]]{{$}} 60declare <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8(<16 x i8>, <16 x i8>) 61define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 62 %a = call <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8( 63 <16 x i8> %x, <16 x i8> %y 64 ) 65 ret <16 x i8> %a 66} 67 68; CHECK-LABEL: avgr_u_v16i8: 69; CHECK-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}} 70; CHECK-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 71; CHECK-NEXT: return $pop[[R]]{{$}} 72declare <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8>, <16 x i8>) 73define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 74 %a = call <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y) 75 ret <16 x i8> %a 76} 77 78; CHECK-LABEL: popcnt_v16i8: 79; CHECK-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}} 80; CHECK-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}} 81; CHECK-NEXT: return $pop[[R]]{{$}} 82declare <16 x i8> @llvm.wasm.popcnt(<16 x i8>) 83define <16 x i8> @popcnt_v16i8(<16 x i8> %x) { 84 %a = call <16 x i8> @llvm.wasm.popcnt(<16 x i8> %x) 85 ret <16 x i8> %a 86} 87 88; CHECK-LABEL: any_v16i8: 89; CHECK-NEXT: .functype any_v16i8 (v128) -> (i32){{$}} 90; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 91; CHECK-NEXT: return $pop[[R]]{{$}} 92declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>) 93define i32 @any_v16i8(<16 x i8> %x) { 94 %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x) 95 ret i32 %a 96} 97 98; CHECK-LABEL: all_v16i8: 99; CHECK-NEXT: .functype all_v16i8 (v128) -> (i32){{$}} 100; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}} 101; CHECK-NEXT: return $pop[[R]]{{$}} 102declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>) 103define i32 @all_v16i8(<16 x i8> %x) { 104 %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x) 105 ret i32 %a 106} 107 108; CHECK-LABEL: bitmask_v16i8: 109; CHECK-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}} 110; CHECK-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}} 111; CHECK-NEXT: return $pop[[R]]{{$}} 112declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>) 113define i32 @bitmask_v16i8(<16 x i8> %x) { 114 %a = call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x) 115 ret i32 %a 116} 117 118; CHECK-LABEL: bitselect_v16i8: 119; CHECK-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}} 120; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 121; CHECK-NEXT: return $pop[[R]]{{$}} 122declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 123define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) { 124 %a = call <16 x i8> @llvm.wasm.bitselect.v16i8( 125 <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c 126 ) 127 ret <16 x i8> %a 128} 129 130; CHECK-LABEL: narrow_signed_v16i8: 131; CHECK-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}} 132; CHECK-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 133; CHECK-NEXT: return $pop[[R]]{{$}} 134declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>) 135define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) { 136 %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16( 137 <8 x i16> %low, <8 x i16> %high 138 ) 139 ret <16 x i8> %a 140} 141 142; CHECK-LABEL: narrow_unsigned_v16i8: 143; CHECK-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}} 144; CHECK-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 145; CHECK-NEXT: return $pop[[R]]{{$}} 146declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>) 147define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) { 148 %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16( 149 <8 x i16> %low, <8 x i16> %high 150 ) 151 ret <16 x i8> %a 152} 153 154; CHECK-LABEL: shuffle_v16i8: 155; NO-CHECK-NOT: i8x16 156; CHECK-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}} 157; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 158; CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}} 159; CHECK-NEXT: return $pop[[R]]{{$}} 160declare <16 x i8> @llvm.wasm.shuffle( 161 <16 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, 162 i32, i32, i32, i32, i32) 163define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) { 164 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 165 i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, 166 i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 35) 167 ret <16 x i8> %res 168} 169 170; CHECK-LABEL: shuffle_undef_v16i8: 171; NO-CHECK-NOT: i8x16 172; CHECK-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}} 173; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 174; CHECK-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}} 175; CHECK-NEXT: return $pop[[R]]{{$}} 176define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) { 177 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 178 i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 179 i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 180 i32 undef, i32 undef, i32 undef, i32 2) 181 ret <16 x i8> %res 182} 183 184; ============================================================================== 185; 8 x i16 186; ============================================================================== 187; CHECK-LABEL: add_sat_s_v8i16: 188; CHECK-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}} 189; CHECK-NEXT: i16x8.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 190; CHECK-NEXT: return $pop[[R]]{{$}} 191declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) 192define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 193 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 194 ret <8 x i16> %a 195} 196 197; CHECK-LABEL: add_sat_u_v8i16: 198; CHECK-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}} 199; CHECK-NEXT: i16x8.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 200; CHECK-NEXT: return $pop[[R]]{{$}} 201declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>) 202define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 203 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 204 ret <8 x i16> %a 205} 206 207; CHECK-LABEL: sub_sat_s_v8i16: 208; CHECK-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}} 209; CHECK-NEXT: i16x8.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 210; CHECK-NEXT: return $pop[[R]]{{$}} 211declare <8 x i16> @llvm.wasm.sub.sat.signed.v8i16(<8 x i16>, <8 x i16>) 212define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 213 %a = call <8 x i16> @llvm.wasm.sub.sat.signed.v8i16( 214 <8 x i16> %x, <8 x i16> %y 215 ) 216 ret <8 x i16> %a 217} 218 219; CHECK-LABEL: sub_sat_u_v8i16: 220; CHECK-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}} 221; CHECK-NEXT: i16x8.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 222; CHECK-NEXT: return $pop[[R]]{{$}} 223declare <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16(<8 x i16>, <8 x i16>) 224define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 225 %a = call <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16( 226 <8 x i16> %x, <8 x i16> %y 227 ) 228 ret <8 x i16> %a 229} 230 231; CHECK-LABEL: avgr_u_v8i16: 232; CHECK-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}} 233; CHECK-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 234; CHECK-NEXT: return $pop[[R]]{{$}} 235declare <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16>, <8 x i16>) 236define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 237 %a = call <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y) 238 ret <8 x i16> %a 239} 240 241; CHECK-LABEL: q15mulr_sat_s_v8i16: 242; CHECK-NEXT: .functype q15mulr_sat_s_v8i16 (v128, v128) -> (v128){{$}} 243; CHECK-NEXT: i16x8.q15mulr_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 244; CHECK-NEXT: return $pop[[R]]{{$}} 245declare <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16>, <8 x i16>) 246define <8 x i16> @q15mulr_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 247 %a = call <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16> %x, 248 <8 x i16> %y) 249 ret <8 x i16> %a 250} 251 252; CHECK-LABEL: extmul_low_s_v8i16: 253; CHECK-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}} 254; CHECK-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}} 255; CHECK-NEXT: return $pop[[R]]{{$}} 256declare <8 x i16> @llvm.wasm.extmul.low.signed.v8i16(<16 x i8>, <16 x i8>) 257define <8 x i16> @extmul_low_s_v8i16(<16 x i8> %x, <16 x i8> %y) { 258 %a = call <8 x i16> @llvm.wasm.extmul.low.signed.v8i16( 259 <16 x i8> %x, <16 x i8> %y 260 ) 261 ret <8 x i16> %a 262} 263 264; CHECK-LABEL: extmul_high_s_v8i16: 265; CHECK-NEXT: .functype extmul_high_s_v8i16 (v128, v128) -> (v128){{$}} 266; CHECK-NEXT: i16x8.extmul_high_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}} 267; CHECK-NEXT: return $pop[[R]]{{$}} 268declare <8 x i16> @llvm.wasm.extmul.high.signed.v8i16(<16 x i8>, <16 x i8>) 269define <8 x i16> @extmul_high_s_v8i16(<16 x i8> %x, <16 x i8> %y) { 270 %a = call <8 x i16> @llvm.wasm.extmul.high.signed.v8i16( 271 <16 x i8> %x, <16 x i8> %y 272 ) 273 ret <8 x i16> %a 274} 275 276; CHECK-LABEL: extmul_low_u_v8i16: 277; CHECK-NEXT: .functype extmul_low_u_v8i16 (v128, v128) -> (v128){{$}} 278; CHECK-NEXT: i16x8.extmul_low_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}} 279; CHECK-NEXT: return $pop[[R]]{{$}} 280declare <8 x i16> @llvm.wasm.extmul.low.unsigned.v8i16(<16 x i8>, <16 x i8>) 281define <8 x i16> @extmul_low_u_v8i16(<16 x i8> %x, <16 x i8> %y) { 282 %a = call <8 x i16> @llvm.wasm.extmul.low.unsigned.v8i16( 283 <16 x i8> %x, <16 x i8> %y 284 ) 285 ret <8 x i16> %a 286} 287 288; CHECK-LABEL: extmul_high_u_v8i16: 289; CHECK-NEXT: .functype extmul_high_u_v8i16 (v128, v128) -> (v128){{$}} 290; CHECK-NEXT: i16x8.extmul_high_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}} 291; CHECK-NEXT: return $pop[[R]]{{$}} 292declare <8 x i16> @llvm.wasm.extmul.high.unsigned.v8i16(<16 x i8>, <16 x i8>) 293define <8 x i16> @extmul_high_u_v8i16(<16 x i8> %x, <16 x i8> %y) { 294 %a = call <8 x i16> @llvm.wasm.extmul.high.unsigned.v8i16( 295 <16 x i8> %x, <16 x i8> %y 296 ) 297 ret <8 x i16> %a 298} 299 300; CHECK-LABEL: extadd_pairwise_s_v8i16: 301; CHECK-NEXT: .functype extadd_pairwise_s_v8i16 (v128) -> (v128){{$}} 302; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_s $push[[R:[0-9]+]]=, $0{{$}} 303; CHECK-NEXT: return $pop[[R]]{{$}} 304declare <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8>) 305define <8 x i16> @extadd_pairwise_s_v8i16(<16 x i8> %x) { 306 %a = call <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8> %x) 307 ret <8 x i16> %a 308} 309 310; CHECK-LABEL: extadd_pairwise_u_v8i16: 311; CHECK-NEXT: .functype extadd_pairwise_u_v8i16 (v128) -> (v128){{$}} 312; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_u $push[[R:[0-9]+]]=, $0{{$}} 313; CHECK-NEXT: return $pop[[R]]{{$}} 314declare <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8>) 315define <8 x i16> @extadd_pairwise_u_v8i16(<16 x i8> %x) { 316 %a = call <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8> %x) 317 ret <8 x i16> %a 318} 319 320; CHECK-LABEL: any_v8i16: 321; CHECK-NEXT: .functype any_v8i16 (v128) -> (i32){{$}} 322; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 323; CHECK-NEXT: return $pop[[R]]{{$}} 324declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>) 325define i32 @any_v8i16(<8 x i16> %x) { 326 %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x) 327 ret i32 %a 328} 329 330; CHECK-LABEL: all_v8i16: 331; CHECK-NEXT: .functype all_v8i16 (v128) -> (i32){{$}} 332; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}} 333; CHECK-NEXT: return $pop[[R]]{{$}} 334declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>) 335define i32 @all_v8i16(<8 x i16> %x) { 336 %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x) 337 ret i32 %a 338} 339 340; CHECK-LABEL: bitmask_v8i16: 341; CHECK-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}} 342; CHECK-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}} 343; CHECK-NEXT: return $pop[[R]]{{$}} 344declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>) 345define i32 @bitmask_v8i16(<8 x i16> %x) { 346 %a = call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x) 347 ret i32 %a 348} 349 350; CHECK-LABEL: bitselect_v8i16: 351; CHECK-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}} 352; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 353; CHECK-NEXT: return $pop[[R]]{{$}} 354declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 355define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) { 356 %a = call <8 x i16> @llvm.wasm.bitselect.v8i16( 357 <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c 358 ) 359 ret <8 x i16> %a 360} 361 362; CHECK-LABEL: narrow_signed_v8i16: 363; CHECK-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}} 364; CHECK-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 365; CHECK-NEXT: return $pop[[R]]{{$}} 366declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>) 367define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) { 368 %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32( 369 <4 x i32> %low, <4 x i32> %high 370 ) 371 ret <8 x i16> %a 372} 373 374; CHECK-LABEL: narrow_unsigned_v8i16: 375; CHECK-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}} 376; CHECK-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 377; CHECK-NEXT: return $pop[[R]]{{$}} 378declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>) 379define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) { 380 %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32( 381 <4 x i32> %low, <4 x i32> %high 382 ) 383 ret <8 x i16> %a 384} 385 386; ============================================================================== 387; 4 x i32 388; ============================================================================== 389; CHECK-LABEL: dot: 390; CHECK-NEXT: .functype dot (v128, v128) -> (v128){{$}} 391; CHECK-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 392; CHECK-NEXT: return $pop[[R]]{{$}} 393declare <4 x i32> @llvm.wasm.dot(<8 x i16>, <8 x i16>) 394define <4 x i32> @dot(<8 x i16> %x, <8 x i16> %y) { 395 %a = call <4 x i32> @llvm.wasm.dot(<8 x i16> %x, <8 x i16> %y) 396 ret <4 x i32> %a 397} 398 399 400; CHECK-LABEL: extmul_low_s_v4i32: 401; CHECK-NEXT: .functype extmul_low_s_v4i32 (v128, v128) -> (v128){{$}} 402; CHECK-NEXT: i32x4.extmul_low_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 403; CHECK-NEXT: return $pop[[R]]{{$}} 404declare <4 x i32> @llvm.wasm.extmul.low.signed.v4i32(<8 x i16>, <8 x i16>) 405define <4 x i32> @extmul_low_s_v4i32(<8 x i16> %x, <8 x i16> %y) { 406 %a = call <4 x i32> @llvm.wasm.extmul.low.signed.v4i32( 407 <8 x i16> %x, <8 x i16> %y 408 ) 409 ret <4 x i32> %a 410} 411 412; CHECK-LABEL: extmul_high_s_v4i32: 413; CHECK-NEXT: .functype extmul_high_s_v4i32 (v128, v128) -> (v128){{$}} 414; CHECK-NEXT: i32x4.extmul_high_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 415; CHECK-NEXT: return $pop[[R]]{{$}} 416declare <4 x i32> @llvm.wasm.extmul.high.signed.v4i32(<8 x i16>, <8 x i16>) 417define <4 x i32> @extmul_high_s_v4i32(<8 x i16> %x, <8 x i16> %y) { 418 %a = call <4 x i32> @llvm.wasm.extmul.high.signed.v4i32( 419 <8 x i16> %x, <8 x i16> %y 420 ) 421 ret <4 x i32> %a 422} 423 424; CHECK-LABEL: extmul_low_u_v4i32: 425; CHECK-NEXT: .functype extmul_low_u_v4i32 (v128, v128) -> (v128){{$}} 426; CHECK-NEXT: i32x4.extmul_low_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 427; CHECK-NEXT: return $pop[[R]]{{$}} 428declare <4 x i32> @llvm.wasm.extmul.low.unsigned.v4i32(<8 x i16>, <8 x i16>) 429define <4 x i32> @extmul_low_u_v4i32(<8 x i16> %x, <8 x i16> %y) { 430 %a = call <4 x i32> @llvm.wasm.extmul.low.unsigned.v4i32( 431 <8 x i16> %x, <8 x i16> %y 432 ) 433 ret <4 x i32> %a 434} 435 436; CHECK-LABEL: extmul_high_u_v4i32: 437; CHECK-NEXT: .functype extmul_high_u_v4i32 (v128, v128) -> (v128){{$}} 438; CHECK-NEXT: i32x4.extmul_high_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 439; CHECK-NEXT: return $pop[[R]]{{$}} 440declare <4 x i32> @llvm.wasm.extmul.high.unsigned.v4i32(<8 x i16>, <8 x i16>) 441define <4 x i32> @extmul_high_u_v4i32(<8 x i16> %x, <8 x i16> %y) { 442 %a = call <4 x i32> @llvm.wasm.extmul.high.unsigned.v4i32( 443 <8 x i16> %x, <8 x i16> %y 444 ) 445 ret <4 x i32> %a 446} 447 448; CHECK-LABEL: extadd_pairwise_s_v4i32: 449; CHECK-NEXT: .functype extadd_pairwise_s_v4i32 (v128) -> (v128){{$}} 450; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_s $push[[R:[0-9]+]]=, $0{{$}} 451; CHECK-NEXT: return $pop[[R]]{{$}} 452declare <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16>) 453define <4 x i32> @extadd_pairwise_s_v4i32(<8 x i16> %x) { 454 %a = call <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16> %x) 455 ret <4 x i32> %a 456} 457 458; CHECK-LABEL: extadd_pairwise_u_v4i32: 459; CHECK-NEXT: .functype extadd_pairwise_u_v4i32 (v128) -> (v128){{$}} 460; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_u $push[[R:[0-9]+]]=, $0{{$}} 461; CHECK-NEXT: return $pop[[R]]{{$}} 462declare <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16>) 463define <4 x i32> @extadd_pairwise_u_v4i32(<8 x i16> %x) { 464 %a = call <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16> %x) 465 ret <4 x i32> %a 466} 467 468 469; CHECK-LABEL: any_v4i32: 470; CHECK-NEXT: .functype any_v4i32 (v128) -> (i32){{$}} 471; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 472; CHECK-NEXT: return $pop[[R]]{{$}} 473declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>) 474define i32 @any_v4i32(<4 x i32> %x) { 475 %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x) 476 ret i32 %a 477} 478 479; CHECK-LABEL: all_v4i32: 480; CHECK-NEXT: .functype all_v4i32 (v128) -> (i32){{$}} 481; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}} 482; CHECK-NEXT: return $pop[[R]]{{$}} 483declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>) 484define i32 @all_v4i32(<4 x i32> %x) { 485 %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x) 486 ret i32 %a 487} 488 489; CHECK-LABEL: bitmask_v4i32: 490; CHECK-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}} 491; CHECK-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}} 492; CHECK-NEXT: return $pop[[R]]{{$}} 493declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>) 494define i32 @bitmask_v4i32(<4 x i32> %x) { 495 %a = call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x) 496 ret i32 %a 497} 498 499; CHECK-LABEL: bitselect_v4i32: 500; CHECK-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}} 501; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 502; CHECK-NEXT: return $pop[[R]]{{$}} 503declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 504define <4 x i32> @bitselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) { 505 %a = call <4 x i32> @llvm.wasm.bitselect.v4i32( 506 <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c 507 ) 508 ret <4 x i32> %a 509} 510 511; CHECK-LABEL: trunc_sat_s_v4i32: 512; NO-CHECK-NOT: f32x4 513; CHECK-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}} 514; CHECK-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0 515; CHECK-NEXT: return $pop[[R]] 516declare <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float>) 517define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) { 518 %a = call <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float> %x) 519 ret <4 x i32> %a 520} 521 522; CHECK-LABEL: trunc_sat_u_v4i32: 523; NO-CHECK-NOT: f32x4 524; CHECK-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}} 525; CHECK-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0 526; CHECK-NEXT: return $pop[[R]] 527declare <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float>) 528define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) { 529 %a = call <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float> %x) 530 ret <4 x i32> %a 531} 532 533; CHECK-LABEL: trunc_sat_zero_signed_v4i32: 534; CHECK-NEXT: .functype trunc_sat_zero_signed_v4i32 (v128) -> (v128){{$}} 535; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}} 536; CHECK-NEXT: return $pop[[R]]{{$}} 537declare <4 x i32> @llvm.wasm.trunc.sat.zero.signed(<2 x double>) 538define <4 x i32> @trunc_sat_zero_signed_v4i32(<2 x double> %a) { 539 %v = call <4 x i32> @llvm.wasm.trunc.sat.zero.signed(<2 x double> %a) 540 ret <4 x i32> %v 541} 542 543; CHECK-LABEL: trunc_sat_zero_unsigned_v4i32: 544; CHECK-NEXT: .functype trunc_sat_zero_unsigned_v4i32 (v128) -> (v128){{$}} 545; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}} 546; CHECK-NEXT: return $pop[[R]]{{$}} 547declare <4 x i32> @llvm.wasm.trunc.sat.zero.unsigned(<2 x double>) 548define <4 x i32> @trunc_sat_zero_unsigned_v4i32(<2 x double> %a) { 549 %v = call <4 x i32> @llvm.wasm.trunc.sat.zero.unsigned(<2 x double> %a) 550 ret <4 x i32> %v 551} 552 553; ============================================================================== 554; 2 x i64 555; ============================================================================== 556; CHECK-LABEL: extmul_low_s_v2i64: 557; CHECK-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}} 558; CHECK-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 559; CHECK-NEXT: return $pop[[R]]{{$}} 560declare <2 x i64> @llvm.wasm.extmul.low.signed.v2i64(<4 x i32>, <4 x i32>) 561define <2 x i64> @extmul_low_s_v2i64(<4 x i32> %x, <4 x i32> %y) { 562 %a = call <2 x i64> @llvm.wasm.extmul.low.signed.v2i64( 563 <4 x i32> %x, <4 x i32> %y 564 ) 565 ret <2 x i64> %a 566} 567 568; CHECK-LABEL: extmul_high_s_v2i64: 569; CHECK-NEXT: .functype extmul_high_s_v2i64 (v128, v128) -> (v128){{$}} 570; CHECK-NEXT: i64x2.extmul_high_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 571; CHECK-NEXT: return $pop[[R]]{{$}} 572declare <2 x i64> @llvm.wasm.extmul.high.signed.v2i64(<4 x i32>, <4 x i32>) 573define <2 x i64> @extmul_high_s_v2i64(<4 x i32> %x, <4 x i32> %y) { 574 %a = call <2 x i64> @llvm.wasm.extmul.high.signed.v2i64( 575 <4 x i32> %x, <4 x i32> %y 576 ) 577 ret <2 x i64> %a 578} 579 580; CHECK-LABEL: extmul_low_u_v2i64: 581; CHECK-NEXT: .functype extmul_low_u_v2i64 (v128, v128) -> (v128){{$}} 582; CHECK-NEXT: i64x2.extmul_low_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 583; CHECK-NEXT: return $pop[[R]]{{$}} 584declare <2 x i64> @llvm.wasm.extmul.low.unsigned.v2i64(<4 x i32>, <4 x i32>) 585define <2 x i64> @extmul_low_u_v2i64(<4 x i32> %x, <4 x i32> %y) { 586 %a = call <2 x i64> @llvm.wasm.extmul.low.unsigned.v2i64( 587 <4 x i32> %x, <4 x i32> %y 588 ) 589 ret <2 x i64> %a 590} 591 592; CHECK-LABEL: extmul_high_u_v2i64: 593; CHECK-NEXT: .functype extmul_high_u_v2i64 (v128, v128) -> (v128){{$}} 594; CHECK-NEXT: i64x2.extmul_high_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 595; CHECK-NEXT: return $pop[[R]]{{$}} 596declare <2 x i64> @llvm.wasm.extmul.high.unsigned.v2i64(<4 x i32>, <4 x i32>) 597define <2 x i64> @extmul_high_u_v2i64(<4 x i32> %x, <4 x i32> %y) { 598 %a = call <2 x i64> @llvm.wasm.extmul.high.unsigned.v2i64( 599 <4 x i32> %x, <4 x i32> %y 600 ) 601 ret <2 x i64> %a 602} 603 604; CHECK-LABEL: any_v2i64: 605; CHECK-NEXT: .functype any_v2i64 (v128) -> (i32){{$}} 606; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 607; CHECK-NEXT: return $pop[[R]]{{$}} 608declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>) 609define i32 @any_v2i64(<2 x i64> %x) { 610 %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x) 611 ret i32 %a 612} 613 614; CHECK-LABEL: all_v2i64: 615; CHECK-NEXT: .functype all_v2i64 (v128) -> (i32){{$}} 616; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}} 617; CHECK-NEXT: return $pop[[R]]{{$}} 618declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>) 619define i32 @all_v2i64(<2 x i64> %x) { 620 %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x) 621 ret i32 %a 622} 623 624; CHECK-LABEL: bitmask_v2i64: 625; CHECK-NEXT: .functype bitmask_v2i64 (v128) -> (i32){{$}} 626; CHECK-NEXT: i64x2.bitmask $push[[R:[0-9]+]]=, $0{{$}} 627; CHECK-NEXT: return $pop[[R]]{{$}} 628declare i32 @llvm.wasm.bitmask.v2i64(<2 x i64>) 629define i32 @bitmask_v2i64(<2 x i64> %x) { 630 %a = call i32 @llvm.wasm.bitmask.v2i64(<2 x i64> %x) 631 ret i32 %a 632} 633 634; CHECK-LABEL: bitselect_v2i64: 635; CHECK-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}} 636; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 637; CHECK-NEXT: return $pop[[R]]{{$}} 638declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 639define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) { 640 %a = call <2 x i64> @llvm.wasm.bitselect.v2i64( 641 <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c 642 ) 643 ret <2 x i64> %a 644} 645 646; ============================================================================== 647; 4 x f32 648; ============================================================================== 649; CHECK-LABEL: bitselect_v4f32: 650; CHECK-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}} 651; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 652; CHECK-NEXT: return $pop[[R]]{{$}} 653declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>) 654define <4 x float> @bitselect_v4f32(<4 x float> %v1, <4 x float> %v2, <4 x float> %c) { 655 %a = call <4 x float> @llvm.wasm.bitselect.v4f32( 656 <4 x float> %v1, <4 x float> %v2, <4 x float> %c 657 ) 658 ret <4 x float> %a 659} 660 661; CHECK-LABEL: pmin_v4f32: 662; CHECK-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}} 663; CHECK-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 664; CHECK-NEXT: return $pop[[R]]{{$}} 665declare <4 x float> @llvm.wasm.pmin.v4f32(<4 x float>, <4 x float>) 666define <4 x float> @pmin_v4f32(<4 x float> %a, <4 x float> %b) { 667 %v = call <4 x float> @llvm.wasm.pmin.v4f32(<4 x float> %a, <4 x float> %b) 668 ret <4 x float> %v 669} 670 671; CHECK-LABEL: pmax_v4f32: 672; CHECK-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}} 673; CHECK-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 674; CHECK-NEXT: return $pop[[R]]{{$}} 675declare <4 x float> @llvm.wasm.pmax.v4f32(<4 x float>, <4 x float>) 676define <4 x float> @pmax_v4f32(<4 x float> %a, <4 x float> %b) { 677 %v = call <4 x float> @llvm.wasm.pmax.v4f32(<4 x float> %a, <4 x float> %b) 678 ret <4 x float> %v 679} 680 681; CHECK-LABEL: ceil_v4f32: 682; CHECK-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}} 683; CHECK-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}} 684; CHECK-NEXT: return $pop[[R]]{{$}} 685declare <4 x float> @llvm.ceil.v4f32(<4 x float>) 686define <4 x float> @ceil_v4f32(<4 x float> %a) { 687 %v = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a) 688 ret <4 x float> %v 689} 690 691; CHECK-LABEL: floor_v4f32: 692; CHECK-NEXT: .functype floor_v4f32 (v128) -> (v128){{$}} 693; CHECK-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}} 694; CHECK-NEXT: return $pop[[R]]{{$}} 695declare <4 x float> @llvm.floor.v4f32(<4 x float>) 696define <4 x float> @floor_v4f32(<4 x float> %a) { 697 %v = call <4 x float> @llvm.floor.v4f32(<4 x float> %a) 698 ret <4 x float> %v 699} 700 701; CHECK-LABEL: trunc_v4f32: 702; CHECK-NEXT: .functype trunc_v4f32 (v128) -> (v128){{$}} 703; CHECK-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}} 704; CHECK-NEXT: return $pop[[R]]{{$}} 705declare <4 x float> @llvm.trunc.v4f32(<4 x float>) 706define <4 x float> @trunc_v4f32(<4 x float> %a) { 707 %v = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a) 708 ret <4 x float> %v 709} 710 711; CHECK-LABEL: nearest_v4f32: 712; CHECK-NEXT: .functype nearest_v4f32 (v128) -> (v128){{$}} 713; CHECK-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}} 714; CHECK-NEXT: return $pop[[R]]{{$}} 715declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) 716define <4 x float> @nearest_v4f32(<4 x float> %a) { 717 %v = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a) 718 ret <4 x float> %v 719} 720 721; CHECK-LABEL: demote_zero_v4f32: 722; CHECK-NEXT: .functype demote_zero_v4f32 (v128) -> (v128){{$}} 723; CHECK-NEXT: f32x4.demote_zero_f64x2 $push[[R:[0-9]+]]=, $0{{$}} 724; CHECK-NEXT: return $pop[[R]]{{$}} 725declare <4 x float> @llvm.wasm.demote.zero(<2 x double>) 726define <4 x float> @demote_zero_v4f32(<2 x double> %a) { 727 %v = call <4 x float> @llvm.wasm.demote.zero(<2 x double> %a) 728 ret <4 x float> %v 729} 730 731; ============================================================================== 732; 2 x f64 733; ============================================================================== 734; CHECK-LABEL: bitselect_v2f64: 735; CHECK-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}} 736; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 737; CHECK-NEXT: return $pop[[R]]{{$}} 738declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>) 739define <2 x double> @bitselect_v2f64(<2 x double> %v1, <2 x double> %v2, <2 x double> %c) { 740 %a = call <2 x double> @llvm.wasm.bitselect.v2f64( 741 <2 x double> %v1, <2 x double> %v2, <2 x double> %c 742 ) 743 ret <2 x double> %a 744} 745 746; CHECK-LABEL: pmin_v2f64: 747; CHECK-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}} 748; CHECK-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 749; CHECK-NEXT: return $pop[[R]]{{$}} 750declare <2 x double> @llvm.wasm.pmin.v2f64(<2 x double>, <2 x double>) 751define <2 x double> @pmin_v2f64(<2 x double> %a, <2 x double> %b) { 752 %v = call <2 x double> @llvm.wasm.pmin.v2f64(<2 x double> %a, <2 x double> %b) 753 ret <2 x double> %v 754} 755 756; CHECK-LABEL: pmax_v2f64: 757; CHECK-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}} 758; CHECK-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 759; CHECK-NEXT: return $pop[[R]]{{$}} 760declare <2 x double> @llvm.wasm.pmax.v2f64(<2 x double>, <2 x double>) 761define <2 x double> @pmax_v2f64(<2 x double> %a, <2 x double> %b) { 762 %v = call <2 x double> @llvm.wasm.pmax.v2f64(<2 x double> %a, <2 x double> %b) 763 ret <2 x double> %v 764} 765 766; CHECK-LABEL: ceil_v2f64: 767; CHECK-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}} 768; CHECK-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}} 769; CHECK-NEXT: return $pop[[R]]{{$}} 770declare <2 x double> @llvm.ceil.v2f64(<2 x double>) 771define <2 x double> @ceil_v2f64(<2 x double> %a) { 772 %v = call <2 x double> @llvm.ceil.v2f64(<2 x double> %a) 773 ret <2 x double> %v 774} 775 776; CHECK-LABEL: floor_v2f64: 777; CHECK-NEXT: .functype floor_v2f64 (v128) -> (v128){{$}} 778; CHECK-NEXT: f64x2.floor $push[[R:[0-9]+]]=, $0{{$}} 779; CHECK-NEXT: return $pop[[R]]{{$}} 780declare <2 x double> @llvm.floor.v2f64(<2 x double>) 781define <2 x double> @floor_v2f64(<2 x double> %a) { 782 %v = call <2 x double> @llvm.floor.v2f64(<2 x double> %a) 783 ret <2 x double> %v 784} 785 786; CHECK-LABEL: trunc_v2f64: 787; CHECK-NEXT: .functype trunc_v2f64 (v128) -> (v128){{$}} 788; CHECK-NEXT: f64x2.trunc $push[[R:[0-9]+]]=, $0{{$}} 789; CHECK-NEXT: return $pop[[R]]{{$}} 790declare <2 x double> @llvm.trunc.v2f64(<2 x double>) 791define <2 x double> @trunc_v2f64(<2 x double> %a) { 792 %v = call <2 x double> @llvm.trunc.v2f64(<2 x double> %a) 793 ret <2 x double> %v 794} 795 796; CHECK-LABEL: nearest_v2f64: 797; CHECK-NEXT: .functype nearest_v2f64 (v128) -> (v128){{$}} 798; CHECK-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}} 799; CHECK-NEXT: return $pop[[R]]{{$}} 800declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) 801define <2 x double> @nearest_v2f64(<2 x double> %a) { 802 %v = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %a) 803 ret <2 x double> %v 804} 805 806; CHECK-LABEL: promote_low_v2f64: 807; CHECK-NEXT: .functype promote_low_v2f64 (v128) -> (v128){{$}} 808; CHECK-NEXT: f64x2.promote_low_f32x4 $push[[R:[0-9]+]]=, $0{{$}} 809; CHECK-NEXT: return $pop[[R]]{{$}} 810declare <2 x double> @llvm.wasm.promote.low(<4 x float>) 811define <2 x double> @promote_low_v2f64(<4 x float> %a) { 812 %v = call <2 x double> @llvm.wasm.promote.low(<4 x float> %a) 813 ret <2 x double> %v 814} 815