1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd | FileCheck %s --check-prefixes=CHECK,SLOW 2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd -fast-isel | FileCheck %s 3 4; Test that SIMD128 intrinsics lower as expected. These intrinsics are 5; only expected to lower successfully if the simd128 attribute is 6; enabled and legal types are used. 7 8target triple = "wasm32-unknown-unknown" 9 10; ============================================================================== 11; 16 x i8 12; ============================================================================== 13; CHECK-LABEL: swizzle_v16i8: 14; CHECK-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}} 15; CHECK-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}} 16; CHECK-NEXT: return $pop[[R]]{{$}} 17declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>) 18define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) { 19 %a = call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y) 20 ret <16 x i8> %a 21} 22 23; CHECK-LABEL: add_sat_s_v16i8: 24; CHECK-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}} 25; CHECK-NEXT: i8x16.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 26; CHECK-NEXT: return $pop[[R]]{{$}} 27declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>) 28define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 29 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 30 ret <16 x i8> %a 31} 32 33; CHECK-LABEL: add_sat_u_v16i8: 34; CHECK-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}} 35; CHECK-NEXT: i8x16.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 36; CHECK-NEXT: return $pop[[R]]{{$}} 37declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) 38define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 39 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 40 ret <16 x i8> %a 41} 42 43; CHECK-LABEL: sub_sat_s_v16i8: 44; CHECK-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}} 45; CHECK-NEXT: i8x16.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 46; CHECK-NEXT: return $pop[[R]]{{$}} 47declare <16 x i8> @llvm.wasm.sub.sat.signed.v16i8(<16 x i8>, <16 x i8>) 48define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 49 %a = call <16 x i8> @llvm.wasm.sub.sat.signed.v16i8( 50 <16 x i8> %x, <16 x i8> %y 51 ) 52 ret <16 x i8> %a 53} 54 55; CHECK-LABEL: sub_sat_u_v16i8: 56; CHECK-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}} 57; CHECK-NEXT: i8x16.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 58; CHECK-NEXT: return $pop[[R]]{{$}} 59declare <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8(<16 x i8>, <16 x i8>) 60define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 61 %a = call <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8( 62 <16 x i8> %x, <16 x i8> %y 63 ) 64 ret <16 x i8> %a 65} 66 67; CHECK-LABEL: avgr_u_v16i8: 68; CHECK-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}} 69; CHECK-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 70; CHECK-NEXT: return $pop[[R]]{{$}} 71declare <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8>, <16 x i8>) 72define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 73 %a = call <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y) 74 ret <16 x i8> %a 75} 76 77; CHECK-LABEL: popcnt_v16i8: 78; CHECK-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}} 79; CHECK-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}} 80; CHECK-NEXT: return $pop[[R]]{{$}} 81declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) 82define <16 x i8> @popcnt_v16i8(<16 x i8> %x) { 83 %a = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %x) 84 ret <16 x i8> %a 85} 86 87; CHECK-LABEL: any_v16i8: 88; CHECK-NEXT: .functype any_v16i8 (v128) -> (i32){{$}} 89; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 90; CHECK-NEXT: return $pop[[R]]{{$}} 91declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>) 92define i32 @any_v16i8(<16 x i8> %x) { 93 %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x) 94 ret i32 %a 95} 96 97; CHECK-LABEL: all_v16i8: 98; CHECK-NEXT: .functype all_v16i8 (v128) -> (i32){{$}} 99; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}} 100; CHECK-NEXT: return $pop[[R]]{{$}} 101declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>) 102define i32 @all_v16i8(<16 x i8> %x) { 103 %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x) 104 ret i32 %a 105} 106 107; CHECK-LABEL: bitmask_v16i8: 108; CHECK-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}} 109; CHECK-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}} 110; CHECK-NEXT: return $pop[[R]]{{$}} 111declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>) 112define i32 @bitmask_v16i8(<16 x i8> %x) { 113 %a = call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x) 114 ret i32 %a 115} 116 117; CHECK-LABEL: bitselect_v16i8: 118; CHECK-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}} 119; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 120; CHECK-NEXT: return $pop[[R]]{{$}} 121declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 122define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) { 123 %a = call <16 x i8> @llvm.wasm.bitselect.v16i8( 124 <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c 125 ) 126 ret <16 x i8> %a 127} 128 129; CHECK-LABEL: narrow_signed_v16i8: 130; CHECK-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}} 131; CHECK-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 132; CHECK-NEXT: return $pop[[R]]{{$}} 133declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>) 134define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) { 135 %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16( 136 <8 x i16> %low, <8 x i16> %high 137 ) 138 ret <16 x i8> %a 139} 140 141; CHECK-LABEL: narrow_unsigned_v16i8: 142; CHECK-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}} 143; CHECK-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 144; CHECK-NEXT: return $pop[[R]]{{$}} 145declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>) 146define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) { 147 %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16( 148 <8 x i16> %low, <8 x i16> %high 149 ) 150 ret <16 x i8> %a 151} 152 153; CHECK-LABEL: shuffle_v16i8: 154; NO-CHECK-NOT: i8x16 155; CHECK-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}} 156; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 157; CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}} 158; CHECK-NEXT: return $pop[[R]]{{$}} 159declare <16 x i8> @llvm.wasm.shuffle( 160 <16 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, 161 i32, i32, i32, i32, i32) 162define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) { 163 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 164 i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, 165 i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 35) 166 ret <16 x i8> %res 167} 168 169; CHECK-LABEL: shuffle_undef_v16i8: 170; NO-CHECK-NOT: i8x16 171; CHECK-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}} 172; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 173; CHECK-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}} 174; CHECK-NEXT: return $pop[[R]]{{$}} 175define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) { 176 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 177 i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 178 i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 179 i32 undef, i32 undef, i32 undef, i32 2) 180 ret <16 x i8> %res 181} 182 183; ============================================================================== 184; 8 x i16 185; ============================================================================== 186; CHECK-LABEL: add_sat_s_v8i16: 187; CHECK-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}} 188; CHECK-NEXT: i16x8.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 189; CHECK-NEXT: return $pop[[R]]{{$}} 190declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) 191define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 192 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 193 ret <8 x i16> %a 194} 195 196; CHECK-LABEL: add_sat_u_v8i16: 197; CHECK-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}} 198; CHECK-NEXT: i16x8.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 199; CHECK-NEXT: return $pop[[R]]{{$}} 200declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>) 201define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 202 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 203 ret <8 x i16> %a 204} 205 206; CHECK-LABEL: sub_sat_s_v8i16: 207; CHECK-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}} 208; CHECK-NEXT: i16x8.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 209; CHECK-NEXT: return $pop[[R]]{{$}} 210declare <8 x i16> @llvm.wasm.sub.sat.signed.v8i16(<8 x i16>, <8 x i16>) 211define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 212 %a = call <8 x i16> @llvm.wasm.sub.sat.signed.v8i16( 213 <8 x i16> %x, <8 x i16> %y 214 ) 215 ret <8 x i16> %a 216} 217 218; CHECK-LABEL: sub_sat_u_v8i16: 219; CHECK-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}} 220; CHECK-NEXT: i16x8.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}} 221; CHECK-NEXT: return $pop[[R]]{{$}} 222declare <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16(<8 x i16>, <8 x i16>) 223define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 224 %a = call <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16( 225 <8 x i16> %x, <8 x i16> %y 226 ) 227 ret <8 x i16> %a 228} 229 230; CHECK-LABEL: avgr_u_v8i16: 231; CHECK-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}} 232; CHECK-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 233; CHECK-NEXT: return $pop[[R]]{{$}} 234declare <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16>, <8 x i16>) 235define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 236 %a = call <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y) 237 ret <8 x i16> %a 238} 239 240; CHECK-LABEL: q15mulr_sat_s_v8i16: 241; CHECK-NEXT: .functype q15mulr_sat_s_v8i16 (v128, v128) -> (v128){{$}} 242; CHECK-NEXT: i16x8.q15mulr_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}} 243; CHECK-NEXT: return $pop[[R]]{{$}} 244declare <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16>, <8 x i16>) 245define <8 x i16> @q15mulr_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 246 %a = call <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16> %x, 247 <8 x i16> %y) 248 ret <8 x i16> %a 249} 250 251; CHECK-LABEL: extadd_pairwise_s_v8i16: 252; CHECK-NEXT: .functype extadd_pairwise_s_v8i16 (v128) -> (v128){{$}} 253; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_s $push[[R:[0-9]+]]=, $0{{$}} 254; CHECK-NEXT: return $pop[[R]]{{$}} 255declare <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8>) 256define <8 x i16> @extadd_pairwise_s_v8i16(<16 x i8> %x) { 257 %a = call <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8> %x) 258 ret <8 x i16> %a 259} 260 261; CHECK-LABEL: extadd_pairwise_u_v8i16: 262; CHECK-NEXT: .functype extadd_pairwise_u_v8i16 (v128) -> (v128){{$}} 263; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_u $push[[R:[0-9]+]]=, $0{{$}} 264; CHECK-NEXT: return $pop[[R]]{{$}} 265declare <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8>) 266define <8 x i16> @extadd_pairwise_u_v8i16(<16 x i8> %x) { 267 %a = call <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8> %x) 268 ret <8 x i16> %a 269} 270 271; CHECK-LABEL: any_v8i16: 272; CHECK-NEXT: .functype any_v8i16 (v128) -> (i32){{$}} 273; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 274; CHECK-NEXT: return $pop[[R]]{{$}} 275declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>) 276define i32 @any_v8i16(<8 x i16> %x) { 277 %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x) 278 ret i32 %a 279} 280 281; CHECK-LABEL: all_v8i16: 282; CHECK-NEXT: .functype all_v8i16 (v128) -> (i32){{$}} 283; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}} 284; CHECK-NEXT: return $pop[[R]]{{$}} 285declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>) 286define i32 @all_v8i16(<8 x i16> %x) { 287 %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x) 288 ret i32 %a 289} 290 291; CHECK-LABEL: bitmask_v8i16: 292; CHECK-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}} 293; CHECK-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}} 294; CHECK-NEXT: return $pop[[R]]{{$}} 295declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>) 296define i32 @bitmask_v8i16(<8 x i16> %x) { 297 %a = call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x) 298 ret i32 %a 299} 300 301; CHECK-LABEL: bitselect_v8i16: 302; CHECK-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}} 303; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 304; CHECK-NEXT: return $pop[[R]]{{$}} 305declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 306define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) { 307 %a = call <8 x i16> @llvm.wasm.bitselect.v8i16( 308 <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c 309 ) 310 ret <8 x i16> %a 311} 312 313; CHECK-LABEL: narrow_signed_v8i16: 314; CHECK-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}} 315; CHECK-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 316; CHECK-NEXT: return $pop[[R]]{{$}} 317declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>) 318define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) { 319 %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32( 320 <4 x i32> %low, <4 x i32> %high 321 ) 322 ret <8 x i16> %a 323} 324 325; CHECK-LABEL: narrow_unsigned_v8i16: 326; CHECK-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}} 327; CHECK-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 328; CHECK-NEXT: return $pop[[R]]{{$}} 329declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>) 330define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) { 331 %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32( 332 <4 x i32> %low, <4 x i32> %high 333 ) 334 ret <8 x i16> %a 335} 336 337; ============================================================================== 338; 4 x i32 339; ============================================================================== 340; CHECK-LABEL: dot: 341; CHECK-NEXT: .functype dot (v128, v128) -> (v128){{$}} 342; CHECK-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 343; CHECK-NEXT: return $pop[[R]]{{$}} 344declare <4 x i32> @llvm.wasm.dot(<8 x i16>, <8 x i16>) 345define <4 x i32> @dot(<8 x i16> %x, <8 x i16> %y) { 346 %a = call <4 x i32> @llvm.wasm.dot(<8 x i16> %x, <8 x i16> %y) 347 ret <4 x i32> %a 348} 349 350; CHECK-LABEL: extadd_pairwise_s_v4i32: 351; CHECK-NEXT: .functype extadd_pairwise_s_v4i32 (v128) -> (v128){{$}} 352; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_s $push[[R:[0-9]+]]=, $0{{$}} 353; CHECK-NEXT: return $pop[[R]]{{$}} 354declare <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16>) 355define <4 x i32> @extadd_pairwise_s_v4i32(<8 x i16> %x) { 356 %a = call <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16> %x) 357 ret <4 x i32> %a 358} 359 360; CHECK-LABEL: extadd_pairwise_u_v4i32: 361; CHECK-NEXT: .functype extadd_pairwise_u_v4i32 (v128) -> (v128){{$}} 362; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_u $push[[R:[0-9]+]]=, $0{{$}} 363; CHECK-NEXT: return $pop[[R]]{{$}} 364declare <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16>) 365define <4 x i32> @extadd_pairwise_u_v4i32(<8 x i16> %x) { 366 %a = call <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16> %x) 367 ret <4 x i32> %a 368} 369 370 371; CHECK-LABEL: any_v4i32: 372; CHECK-NEXT: .functype any_v4i32 (v128) -> (i32){{$}} 373; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 374; CHECK-NEXT: return $pop[[R]]{{$}} 375declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>) 376define i32 @any_v4i32(<4 x i32> %x) { 377 %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x) 378 ret i32 %a 379} 380 381; CHECK-LABEL: all_v4i32: 382; CHECK-NEXT: .functype all_v4i32 (v128) -> (i32){{$}} 383; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}} 384; CHECK-NEXT: return $pop[[R]]{{$}} 385declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>) 386define i32 @all_v4i32(<4 x i32> %x) { 387 %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x) 388 ret i32 %a 389} 390 391; CHECK-LABEL: bitmask_v4i32: 392; CHECK-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}} 393; CHECK-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}} 394; CHECK-NEXT: return $pop[[R]]{{$}} 395declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>) 396define i32 @bitmask_v4i32(<4 x i32> %x) { 397 %a = call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x) 398 ret i32 %a 399} 400 401; CHECK-LABEL: bitselect_v4i32: 402; CHECK-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}} 403; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 404; CHECK-NEXT: return $pop[[R]]{{$}} 405declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 406define <4 x i32> @bitselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) { 407 %a = call <4 x i32> @llvm.wasm.bitselect.v4i32( 408 <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c 409 ) 410 ret <4 x i32> %a 411} 412 413; CHECK-LABEL: trunc_sat_s_v4i32: 414; NO-CHECK-NOT: f32x4 415; CHECK-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}} 416; CHECK-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0 417; CHECK-NEXT: return $pop[[R]] 418declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float>) 419define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) { 420 %a = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %x) 421 ret <4 x i32> %a 422} 423 424; CHECK-LABEL: trunc_sat_u_v4i32: 425; NO-CHECK-NOT: f32x4 426; CHECK-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}} 427; CHECK-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0 428; CHECK-NEXT: return $pop[[R]] 429declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float>) 430define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) { 431 %a = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %x) 432 ret <4 x i32> %a 433} 434 435; CHECK-LABEL: trunc_sat_zero_s_v4i32: 436; CHECK-NEXT: .functype trunc_sat_zero_s_v4i32 (v128) -> (v128){{$}} 437; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}} 438; CHECK-NEXT: return $pop[[R]]{{$}} 439declare <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double>) 440define <4 x i32> @trunc_sat_zero_s_v4i32(<2 x double> %x) { 441 %v = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %x) 442 %a = shufflevector <2 x i32> %v, <2 x i32> <i32 0, i32 0>, 443 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 444 ret <4 x i32> %a 445} 446 447; CHECK-LABEL: trunc_sat_zero_s_v4i32_2: 448; CHECK-NEXT: .functype trunc_sat_zero_s_v4i32_2 (v128) -> (v128){{$}} 449; SLOW-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}} 450; SLOW-NEXT: return $pop[[R]]{{$}} 451declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double>) 452define <4 x i32> @trunc_sat_zero_s_v4i32_2(<2 x double> %x) { 453 %v = shufflevector <2 x double> %x, <2 x double> zeroinitializer, 454 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 455 %a = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double> %v) 456 ret <4 x i32> %a 457} 458 459; CHECK-LABEL: trunc_sat_zero_u_v4i32: 460; CHECK-NEXT: .functype trunc_sat_zero_u_v4i32 (v128) -> (v128){{$}} 461; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}} 462; CHECK-NEXT: return $pop[[R]]{{$}} 463declare <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double>) 464define <4 x i32> @trunc_sat_zero_u_v4i32(<2 x double> %x) { 465 %v = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %x) 466 %a = shufflevector <2 x i32> %v, <2 x i32> <i32 0, i32 0>, 467 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 468 ret <4 x i32> %a 469} 470 471; CHECK-LABEL: trunc_sat_zero_u_v4i32_2: 472; CHECK-NEXT: .functype trunc_sat_zero_u_v4i32_2 (v128) -> (v128){{$}} 473; SLOW-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}} 474; SLOW-NEXT: return $pop[[R]]{{$}} 475declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double>) 476define <4 x i32> @trunc_sat_zero_u_v4i32_2(<2 x double> %x) { 477 %v = shufflevector <2 x double> %x, <2 x double> zeroinitializer, 478 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 479 %a = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double> %v) 480 ret <4 x i32> %a 481} 482 483; ============================================================================== 484; 2 x i64 485; ============================================================================== 486; CHECK-LABEL: any_v2i64: 487; CHECK-NEXT: .functype any_v2i64 (v128) -> (i32){{$}} 488; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}} 489; CHECK-NEXT: return $pop[[R]]{{$}} 490declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>) 491define i32 @any_v2i64(<2 x i64> %x) { 492 %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x) 493 ret i32 %a 494} 495 496; CHECK-LABEL: all_v2i64: 497; CHECK-NEXT: .functype all_v2i64 (v128) -> (i32){{$}} 498; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}} 499; CHECK-NEXT: return $pop[[R]]{{$}} 500declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>) 501define i32 @all_v2i64(<2 x i64> %x) { 502 %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x) 503 ret i32 %a 504} 505 506; CHECK-LABEL: bitmask_v2i64: 507; CHECK-NEXT: .functype bitmask_v2i64 (v128) -> (i32){{$}} 508; CHECK-NEXT: i64x2.bitmask $push[[R:[0-9]+]]=, $0{{$}} 509; CHECK-NEXT: return $pop[[R]]{{$}} 510declare i32 @llvm.wasm.bitmask.v2i64(<2 x i64>) 511define i32 @bitmask_v2i64(<2 x i64> %x) { 512 %a = call i32 @llvm.wasm.bitmask.v2i64(<2 x i64> %x) 513 ret i32 %a 514} 515 516; CHECK-LABEL: bitselect_v2i64: 517; CHECK-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}} 518; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 519; CHECK-NEXT: return $pop[[R]]{{$}} 520declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 521define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) { 522 %a = call <2 x i64> @llvm.wasm.bitselect.v2i64( 523 <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c 524 ) 525 ret <2 x i64> %a 526} 527 528; ============================================================================== 529; 4 x f32 530; ============================================================================== 531; CHECK-LABEL: bitselect_v4f32: 532; CHECK-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}} 533; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 534; CHECK-NEXT: return $pop[[R]]{{$}} 535declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>) 536define <4 x float> @bitselect_v4f32(<4 x float> %v1, <4 x float> %v2, <4 x float> %c) { 537 %a = call <4 x float> @llvm.wasm.bitselect.v4f32( 538 <4 x float> %v1, <4 x float> %v2, <4 x float> %c 539 ) 540 ret <4 x float> %a 541} 542 543; CHECK-LABEL: pmin_v4f32: 544; CHECK-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}} 545; CHECK-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 546; CHECK-NEXT: return $pop[[R]]{{$}} 547declare <4 x float> @llvm.wasm.pmin.v4f32(<4 x float>, <4 x float>) 548define <4 x float> @pmin_v4f32(<4 x float> %a, <4 x float> %b) { 549 %v = call <4 x float> @llvm.wasm.pmin.v4f32(<4 x float> %a, <4 x float> %b) 550 ret <4 x float> %v 551} 552 553; CHECK-LABEL: pmax_v4f32: 554; CHECK-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}} 555; CHECK-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 556; CHECK-NEXT: return $pop[[R]]{{$}} 557declare <4 x float> @llvm.wasm.pmax.v4f32(<4 x float>, <4 x float>) 558define <4 x float> @pmax_v4f32(<4 x float> %a, <4 x float> %b) { 559 %v = call <4 x float> @llvm.wasm.pmax.v4f32(<4 x float> %a, <4 x float> %b) 560 ret <4 x float> %v 561} 562 563; CHECK-LABEL: ceil_v4f32: 564; CHECK-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}} 565; CHECK-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}} 566; CHECK-NEXT: return $pop[[R]]{{$}} 567declare <4 x float> @llvm.ceil.v4f32(<4 x float>) 568define <4 x float> @ceil_v4f32(<4 x float> %a) { 569 %v = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a) 570 ret <4 x float> %v 571} 572 573; CHECK-LABEL: floor_v4f32: 574; CHECK-NEXT: .functype floor_v4f32 (v128) -> (v128){{$}} 575; CHECK-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}} 576; CHECK-NEXT: return $pop[[R]]{{$}} 577declare <4 x float> @llvm.floor.v4f32(<4 x float>) 578define <4 x float> @floor_v4f32(<4 x float> %a) { 579 %v = call <4 x float> @llvm.floor.v4f32(<4 x float> %a) 580 ret <4 x float> %v 581} 582 583; CHECK-LABEL: trunc_v4f32: 584; CHECK-NEXT: .functype trunc_v4f32 (v128) -> (v128){{$}} 585; CHECK-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}} 586; CHECK-NEXT: return $pop[[R]]{{$}} 587declare <4 x float> @llvm.trunc.v4f32(<4 x float>) 588define <4 x float> @trunc_v4f32(<4 x float> %a) { 589 %v = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a) 590 ret <4 x float> %v 591} 592 593; CHECK-LABEL: nearest_v4f32: 594; CHECK-NEXT: .functype nearest_v4f32 (v128) -> (v128){{$}} 595; CHECK-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}} 596; CHECK-NEXT: return $pop[[R]]{{$}} 597declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) 598define <4 x float> @nearest_v4f32(<4 x float> %a) { 599 %v = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a) 600 ret <4 x float> %v 601} 602 603; CHECK-LABEL: fma_v4f32: 604; CHECK-NEXT: .functype fma_v4f32 (v128, v128, v128) -> (v128){{$}} 605; CHECK-NEXT: f32x4.fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 606; CHECK-NEXT: return $pop[[R]]{{$}} 607declare <4 x float> @llvm.wasm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) 608define <4 x float> @fma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 609 %v = call <4 x float> @llvm.wasm.fma.v4f32( 610 <4 x float> %a, <4 x float> %b, <4 x float> %c 611 ) 612 ret <4 x float> %v 613} 614 615; CHECK-LABEL: fms_v4f32: 616; CHECK-NEXT: .functype fms_v4f32 (v128, v128, v128) -> (v128){{$}} 617; CHECK-NEXT: f32x4.fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 618; CHECK-NEXT: return $pop[[R]]{{$}} 619declare <4 x float> @llvm.wasm.fms.v4f32(<4 x float>, <4 x float>, <4 x float>) 620define <4 x float> @fms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 621 %v = call <4 x float> @llvm.wasm.fms.v4f32( 622 <4 x float> %a, <4 x float> %b, <4 x float> %c 623 ) 624 ret <4 x float> %v 625} 626 627; ============================================================================== 628; 2 x f64 629; ============================================================================== 630; CHECK-LABEL: bitselect_v2f64: 631; CHECK-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}} 632; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 633; CHECK-NEXT: return $pop[[R]]{{$}} 634declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>) 635define <2 x double> @bitselect_v2f64(<2 x double> %v1, <2 x double> %v2, <2 x double> %c) { 636 %a = call <2 x double> @llvm.wasm.bitselect.v2f64( 637 <2 x double> %v1, <2 x double> %v2, <2 x double> %c 638 ) 639 ret <2 x double> %a 640} 641 642; CHECK-LABEL: pmin_v2f64: 643; CHECK-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}} 644; CHECK-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 645; CHECK-NEXT: return $pop[[R]]{{$}} 646declare <2 x double> @llvm.wasm.pmin.v2f64(<2 x double>, <2 x double>) 647define <2 x double> @pmin_v2f64(<2 x double> %a, <2 x double> %b) { 648 %v = call <2 x double> @llvm.wasm.pmin.v2f64(<2 x double> %a, <2 x double> %b) 649 ret <2 x double> %v 650} 651 652; CHECK-LABEL: pmax_v2f64: 653; CHECK-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}} 654; CHECK-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 655; CHECK-NEXT: return $pop[[R]]{{$}} 656declare <2 x double> @llvm.wasm.pmax.v2f64(<2 x double>, <2 x double>) 657define <2 x double> @pmax_v2f64(<2 x double> %a, <2 x double> %b) { 658 %v = call <2 x double> @llvm.wasm.pmax.v2f64(<2 x double> %a, <2 x double> %b) 659 ret <2 x double> %v 660} 661 662; CHECK-LABEL: ceil_v2f64: 663; CHECK-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}} 664; CHECK-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}} 665; CHECK-NEXT: return $pop[[R]]{{$}} 666declare <2 x double> @llvm.ceil.v2f64(<2 x double>) 667define <2 x double> @ceil_v2f64(<2 x double> %a) { 668 %v = call <2 x double> @llvm.ceil.v2f64(<2 x double> %a) 669 ret <2 x double> %v 670} 671 672; CHECK-LABEL: floor_v2f64: 673; CHECK-NEXT: .functype floor_v2f64 (v128) -> (v128){{$}} 674; CHECK-NEXT: f64x2.floor $push[[R:[0-9]+]]=, $0{{$}} 675; CHECK-NEXT: return $pop[[R]]{{$}} 676declare <2 x double> @llvm.floor.v2f64(<2 x double>) 677define <2 x double> @floor_v2f64(<2 x double> %a) { 678 %v = call <2 x double> @llvm.floor.v2f64(<2 x double> %a) 679 ret <2 x double> %v 680} 681 682; CHECK-LABEL: trunc_v2f64: 683; CHECK-NEXT: .functype trunc_v2f64 (v128) -> (v128){{$}} 684; CHECK-NEXT: f64x2.trunc $push[[R:[0-9]+]]=, $0{{$}} 685; CHECK-NEXT: return $pop[[R]]{{$}} 686declare <2 x double> @llvm.trunc.v2f64(<2 x double>) 687define <2 x double> @trunc_v2f64(<2 x double> %a) { 688 %v = call <2 x double> @llvm.trunc.v2f64(<2 x double> %a) 689 ret <2 x double> %v 690} 691 692; CHECK-LABEL: nearest_v2f64: 693; CHECK-NEXT: .functype nearest_v2f64 (v128) -> (v128){{$}} 694; CHECK-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}} 695; CHECK-NEXT: return $pop[[R]]{{$}} 696declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) 697define <2 x double> @nearest_v2f64(<2 x double> %a) { 698 %v = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %a) 699 ret <2 x double> %v 700} 701 702; CHECK-LABEL: fma_v2f64: 703; CHECK-NEXT: .functype fma_v2f64 (v128, v128, v128) -> (v128){{$}} 704; CHECK-NEXT: f64x2.fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 705; CHECK-NEXT: return $pop[[R]]{{$}} 706declare <2 x double> @llvm.wasm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) 707define <2 x double> @fma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 708 %v = call <2 x double> @llvm.wasm.fma.v2f64( 709 <2 x double> %a, <2 x double> %b, <2 x double> %c 710 ) 711 ret <2 x double> %v 712} 713 714; CHECK-LABEL: fms_v2f64: 715; CHECK-NEXT: .functype fms_v2f64 (v128, v128, v128) -> (v128){{$}} 716; CHECK-NEXT: f64x2.fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 717; CHECK-NEXT: return $pop[[R]]{{$}} 718declare <2 x double> @llvm.wasm.fms.v2f64(<2 x double>, <2 x double>, <2 x double>) 719define <2 x double> @fms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 720 %v = call <2 x double> @llvm.wasm.fms.v2f64( 721 <2 x double> %a, <2 x double> %b, <2 x double> %c 722 ) 723 ret <2 x double> %v 724} 725