1; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
2; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
3; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
4; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
5
6; Test that basic SIMD128 arithmetic operations assemble as expected.
7
8target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
9target triple = "wasm32-unknown-unknown"
10
11; ==============================================================================
12; 16 x i8
13; ==============================================================================
14; CHECK-LABEL: add_v16i8
15; NO-SIMD128-NOT: i8x16
16; SIMD128: .param v128, v128{{$}}
17; SIMD128: .result v128{{$}}
18; SIMD128: i8x16.add $push0=, $0, $1{{$}}
19; SIMD128: return $pop0{{$}}
20define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) {
21  %a = add <16 x i8> %x, %y
22  ret <16 x i8> %a
23}
24
25; CHECK-LABEL: sub_v16i8
26; NO-SIMD128-NOT: i8x16
27; SIMD128: .param v128, v128{{$}}
28; SIMD128: .result v128{{$}}
29; SIMD128: i8x16.sub $push0=, $0, $1{{$}}
30; SIMD128: return $pop0{{$}}
31define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) {
32  %a = sub <16 x i8> %x, %y
33  ret <16 x i8> %a
34}
35
36; CHECK-LABEL: mul_v16i8
37; NO-SIMD128-NOT: i8x16
38; SIMD128: .param v128, v128{{$}}
39; SIMD128: .result v128{{$}}
40; SIMD128: i8x16.mul $push0=, $0, $1{{$}}
41; SIMD128: return $pop0{{$}}
42define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
43  %a = mul <16 x i8> %x, %y
44  ret <16 x i8> %a
45}
46
47; ==============================================================================
48; 8 x i16
49; ==============================================================================
50; CHECK-LABEL: add_v8i16
51; NO-SIMD128-NOT: i16x8
52; SIMD128: .param v128, v128{{$}}
53; SIMD128: .result v128{{$}}
54; SIMD128: i16x8.add $push0=, $0, $1{{$}}
55; SIMD128: return $pop0{{$}}
56define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) {
57  %a = add <8 x i16> %x, %y
58  ret <8 x i16> %a
59}
60
61; CHECK-LABEL: sub_v8i16
62; NO-SIMD128-NOT: i16x8
63; SIMD128: .param v128, v128{{$}}
64; SIMD128: .result v128{{$}}
65; SIMD128: i16x8.sub $push0=, $0, $1{{$}}
66; SIMD128: return $pop0{{$}}
67define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) {
68  %a = sub <8 x i16> %x, %y
69  ret <8 x i16> %a
70}
71
72; CHECK-LABEL: mul_v8i16
73; NO-SIMD128-NOT: i16x8
74; SIMD128: .param v128, v128{{$}}
75; SIMD128: .result v128{{$}}
76; SIMD128: i16x8.mul $push0=, $0, $1{{$}}
77; SIMD128: return $pop0{{$}}
78define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) {
79  %a = mul <8 x i16> %x, %y
80  ret <8 x i16> %a
81}
82
83; ==============================================================================
84; 4 x i32
85; ==============================================================================
86; CHECK-LABEL: add_v4i32
87; NO-SIMD128-NOT: i32x4
88; SIMD128: .param v128, v128{{$}}
89; SIMD128: .result v128{{$}}
90; SIMD128: i32x4.add $push0=, $0, $1{{$}}
91; SIMD128: return $pop0{{$}}
92define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) {
93  %a = add <4 x i32> %x, %y
94  ret <4 x i32> %a
95}
96
97; CHECK-LABEL: sub_v4i32
98; NO-SIMD128-NOT: i32x4
99; SIMD128: .param v128, v128{{$}}
100; SIMD128: .result v128{{$}}
101; SIMD128: i32x4.sub $push0=, $0, $1{{$}}
102; SIMD128: return $pop0{{$}}
103define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) {
104  %a = sub <4 x i32> %x, %y
105  ret <4 x i32> %a
106}
107
108; CHECK-LABEL: mul_v4i32
109; NO-SIMD128-NOT: i32x4
110; SIMD128: .param v128, v128{{$}}
111; SIMD128: .result v128{{$}}
112; SIMD128: i32x4.mul $push0=, $0, $1{{$}}
113; SIMD128: return $pop0{{$}}
114define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
115  %a = mul <4 x i32> %x, %y
116  ret <4 x i32> %a
117}
118
119; ==============================================================================
120; 2 x i64
121; ==============================================================================
122; CHECK-LABEL: add_v2i64
123; NO-SIMD128-NOT: i64x2
124; SIMD128: .param v128, v128{{$}}
125; SIMD128: .result v128{{$}}
126; SIMD128: i64x2.add $push0=, $0, $1{{$}}
127; SIMD128: return $pop0{{$}}
128define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) {
129  %a = add <2 x i64> %x, %y
130  ret <2 x i64> %a
131}
132
133; CHECK-LABEL: sub_v2i64
134; NO-SIMD128-NOT: i64x2
135; SIMD128: .param v128, v128{{$}}
136; SIMD128: .result v128{{$}}
137; SIMD128: i64x2.sub $push0=, $0, $1{{$}}
138; SIMD128: return $pop0{{$}}
139define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
140  %a = sub <2 x i64> %x, %y
141  ret <2 x i64> %a
142}
143
144; CHECK-LABEL: mul_v2i64
145; NO-SIMD128-NOT: i64x2
146; SIMD128: .param v128, v128{{$}}
147; SIMD128: .result v128{{$}}
148; SIMD128: i64x2.mul $push0=, $0, $1{{$}}
149; SIMD128: return $pop0{{$}}
150define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
151  %a = mul <2 x i64> %x, %y
152  ret <2 x i64> %a
153}
154
155; ==============================================================================
156; 4 x float
157; ==============================================================================
158; CHECK-LABEL: add_v4f32
159; NO-SIMD128-NOT: f32x4
160; SIMD128: .param v128, v128{{$}}
161; SIMD128: .result v128{{$}}
162; SIMD128: f32x4.add $push0=, $0, $1{{$}}
163; SIMD128: return $pop0{{$}}
164define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
165  %a = fadd <4 x float> %x, %y
166  ret <4 x float> %a
167}
168
169; CHECK-LABEL: sub_v4f32
170; NO-SIMD128-NOT: f32x4
171; SIMD128: .param v128, v128{{$}}
172; SIMD128: .result v128{{$}}
173; SIMD128: f32x4.sub $push0=, $0, $1{{$}}
174; SIMD128: return $pop0{{$}}
175define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) {
176  %a = fsub <4 x float> %x, %y
177  ret <4 x float> %a
178}
179
180; CHECK-LABEL: div_v4f32
181; NO-SIMD128-NOT: f32x4
182; SIMD128: .param v128, v128{{$}}
183; SIMD128: .result v128{{$}}
184; SIMD128: f32x4.div $push0=, $0, $1{{$}}
185; SIMD128: return $pop0{{$}}
186define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) {
187  %a = fdiv <4 x float> %x, %y
188  ret <4 x float> %a
189}
190
191; CHECK-LABEL: mul_v4f32
192; NO-SIMD128-NOT: f32x4
193; SIMD128: .param v128, v128{{$}}
194; SIMD128: .result v128{{$}}
195; SIMD128: f32x4.mul $push0=, $0, $1{{$}}
196; SIMD128: return $pop0{{$}}
197define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
198  %a = fmul <4 x float> %x, %y
199  ret <4 x float> %a
200}
201
202; ==============================================================================
203; 2 x double
204; ==============================================================================
205; CHECK-LABEL: add_v2f64
206; NO-SIMD128-NOT: f64x2
207; SIMD128: .param v128, v128{{$}}
208; SIMD128: .result v128{{$}}
209; SIMD128: f64x2.add $push0=, $0, $1{{$}}
210; SIMD128: return $pop0{{$}}
211define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
212  %a = fadd <2 x double> %x, %y
213  ret <2 x double> %a
214}
215
216; CHECK-LABEL: sub_v2f64
217; NO-SIMD128-NOT: f64x2
218; SIMD128: .param v128, v128{{$}}
219; SIMD128: .result v128{{$}}
220; SIMD128: f64x2.sub $push0=, $0, $1{{$}}
221; SIMD128: return $pop0{{$}}
222define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) {
223  %a = fsub <2 x double> %x, %y
224  ret <2 x double> %a
225}
226
227; CHECK-LABEL: div_v2f64
228; NO-SIMD128-NOT: f64x2
229; SIMD128: .param v128, v128{{$}}
230; SIMD128: .result v128{{$}}
231; SIMD128: f64x2.div $push0=, $0, $1{{$}}
232; SIMD128: return $pop0{{$}}
233define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) {
234  %a = fdiv <2 x double> %x, %y
235  ret <2 x double> %a
236}
237
238; CHECK-LABEL: mul_v2f64
239; NO-SIMD128-NOT: f64x2
240; SIMD128: .param v128, v128{{$}}
241; SIMD128: .result v128{{$}}
242; SIMD128: f64x2.mul $push0=, $0, $1{{$}}
243; SIMD128: return $pop0{{$}}
244define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) {
245  %a = fmul <2 x double> %x, %y
246  ret <2 x double> %a
247}
248