1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW 2 3; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST 4 5; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128 6 7; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128 8 9; check that a non-test run (including explicit locals pass) at least finishes 10; RUN: llc < %s -O0 -mattr=+simd128 11; RUN: llc < %s -O2 -mattr=+simd128 12 13; Test that basic SIMD128 arithmetic operations assemble as expected. 14 15target triple = "wasm32-unknown-unknown" 16 17; ============================================================================== 18; 16 x i8 19; ============================================================================== 20; CHECK-LABEL: add_v16i8: 21; NO-SIMD128-NOT: i8x16 22; SIMD128-NEXT: .functype add_v16i8 (v128, v128) -> (v128){{$}} 23; SIMD128-NEXT: i8x16.add $push[[R:[0-9]+]]=, $0, $1{{$}} 24; SIMD128-NEXT: return $pop[[R]]{{$}} 25define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) { 26 %a = add <16 x i8> %x, %y 27 ret <16 x i8> %a 28} 29 30; CHECK-LABEL: sub_v16i8: 31; NO-SIMD128-NOT: i8x16 32; SIMD128-NEXT: .functype sub_v16i8 (v128, v128) -> (v128){{$}} 33; SIMD128-NEXT: i8x16.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 34; SIMD128-NEXT: return $pop[[R]]{{$}} 35define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) { 36 %a = sub <16 x i8> %x, %y 37 ret <16 x i8> %a 38} 39 40; i8x16.mul is not in spec 41; CHECK-LABEL: mul_v16i8: 42; NO-SIMD128-NOT: i8x16 43; SIMD128-NOT: i8x16.mul 44; SIMD128: i8x16.extract_lane_u 45; SIMD128: i32.mul 46define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) { 47 %a = mul <16 x i8> %x, %y 48 ret <16 x i8> %a 49} 50 51; CHECK-LABEL: min_s_v16i8: 52; NO-SIMD128-NOT: i8x16 53; SIMD128-NEXT: .functype min_s_v16i8 (v128, v128) -> (v128){{$}} 54; SIMD128-NEXT: i8x16.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 55; SIMD128-NEXT: return $pop[[R]]{{$}} 56define <16 x i8> @min_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 57 %c = icmp slt <16 x i8> %x, %y 58 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 59 ret <16 x i8> %a 60} 61 62; CHECK-LABEL: min_u_v16i8: 63; NO-SIMD128-NOT: i8x16 64; SIMD128-NEXT: .functype min_u_v16i8 (v128, v128) -> (v128){{$}} 65; SIMD128-NEXT: i8x16.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 66; SIMD128-NEXT: return $pop[[R]]{{$}} 67define <16 x i8> @min_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 68 %c = icmp ult <16 x i8> %x, %y 69 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 70 ret <16 x i8> %a 71} 72 73; CHECK-LABEL: max_s_v16i8: 74; NO-SIMD128-NOT: i8x16 75; SIMD128-NEXT: .functype max_s_v16i8 (v128, v128) -> (v128){{$}} 76; SIMD128-NEXT: i8x16.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 77; SIMD128-NEXT: return $pop[[R]]{{$}} 78define <16 x i8> @max_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 79 %c = icmp sgt <16 x i8> %x, %y 80 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 81 ret <16 x i8> %a 82} 83 84; CHECK-LABEL: max_u_v16i8: 85; NO-SIMD128-NOT: i8x16 86; SIMD128-NEXT: .functype max_u_v16i8 (v128, v128) -> (v128){{$}} 87; SIMD128-NEXT: i8x16.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 88; SIMD128-NEXT: return $pop[[R]]{{$}} 89define <16 x i8> @max_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 90 %c = icmp ugt <16 x i8> %x, %y 91 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 92 ret <16 x i8> %a 93} 94 95; CHECK-LABEL: avgr_u_v16i8: 96; NO-SIMD128-NOT: i8x16 97; SIMD128-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}} 98; SIMD128-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 99; SIMD128-NEXT: return $pop[[R]]{{$}} 100define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 101 %a = add nuw <16 x i8> %x, %y 102 %b = add nuw <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, 103 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 104 %c = udiv <16 x i8> %b, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, 105 i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 106 ret <16 x i8> %c 107} 108 109; CHECK-LABEL: avgr_u_v16i8_wrap: 110; NO-SIMD128-NOT: i8x16 111; SIMD128-NEXT: .functype avgr_u_v16i8_wrap (v128, v128) -> (v128){{$}} 112; SIMD128-NOT: i8x16.avgr_u 113define <16 x i8> @avgr_u_v16i8_wrap(<16 x i8> %x, <16 x i8> %y) { 114 %a = add <16 x i8> %x, %y 115 %b = add <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, 116 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 117 %c = udiv <16 x i8> %b, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, 118 i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 119 ret <16 x i8> %c 120} 121 122; CHECK-LABEL: abs_v16i8: 123; NO-SIMD128-NOT: i8x16 124; SIMD128-NEXT: .functype abs_v16i8 (v128) -> (v128){{$}} 125; SIMD128-NEXT: i8x16.abs $push[[R:[0-9]+]]=, $0{{$}} 126; SIMD128-NEXT: return $pop[[R]]{{$}} 127define <16 x i8> @abs_v16i8(<16 x i8> %x) { 128 %a = sub <16 x i8> zeroinitializer, %x 129 %b = icmp slt <16 x i8> %x, zeroinitializer 130 %c = select <16 x i1> %b, <16 x i8> %a, <16 x i8> %x 131 ret <16 x i8> %c 132} 133 134; CHECK-LABEL: neg_v16i8: 135; NO-SIMD128-NOT: i8x16 136; SIMD128-NEXT: .functype neg_v16i8 (v128) -> (v128){{$}} 137; SIMD128-NEXT: i8x16.neg $push[[R:[0-9]+]]=, $0{{$}} 138; SIMD128-NEXT: return $pop[[R]]{{$}} 139define <16 x i8> @neg_v16i8(<16 x i8> %x) { 140 %a = sub <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, 141 i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, 142 %x 143 ret <16 x i8> %a 144} 145 146; CHECK-LABEL: shl_v16i8: 147; NO-SIMD128-NOT: i8x16 148; SIMD128-NEXT: .functype shl_v16i8 (v128, i32) -> (v128){{$}} 149; SIMD128-NEXT: i8x16.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 150; SIMD128-NEXT: return $pop[[R]]{{$}} 151define <16 x i8> @shl_v16i8(<16 x i8> %v, i8 %x) { 152 %t = insertelement <16 x i8> undef, i8 %x, i32 0 153 %s = shufflevector <16 x i8> %t, <16 x i8> undef, 154 <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, 155 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 156 %a = shl <16 x i8> %v, %s 157 ret <16 x i8> %a 158} 159 160; CHECK-LABEL: shl_const_v16i8: 161; NO-SIMD128-NOT: i8x16 162; SIMD128-NEXT: .functype shl_const_v16i8 (v128) -> (v128){{$}} 163; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5 164; SIMD128-NEXT: i8x16.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 165; SIMD128-NEXT: return $pop[[R]]{{$}} 166define <16 x i8> @shl_const_v16i8(<16 x i8> %v) { 167 %a = shl <16 x i8> %v, 168 <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, 169 i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> 170 ret <16 x i8> %a 171} 172 173; CHECK-LABEL: shl_vec_v16i8: 174; NO-SIMD128-NOT: i8x16 175; SIMD128-NEXT: .functype shl_vec_v16i8 (v128, v128) -> (v128){{$}} 176; SIMD128-NEXT: i8x16.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}} 177; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}} 178; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}} 179; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 180; SIMD128-NEXT: i32.shl $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]] 181; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]] 182; Skip 14 lanes 183; SIMD128: i8x16.extract_lane_u $push[[L4:[0-9]+]]=, $0, 15{{$}} 184; SIMD128-NEXT: i8x16.extract_lane_u $push[[L5:[0-9]+]]=, $1, 15{{$}} 185; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}} 186; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 187; SIMD128-NEXT: i32.shl $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 188; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}} 189; SIMD128-NEXT: return $pop[[R]]{{$}} 190define <16 x i8> @shl_vec_v16i8(<16 x i8> %v, <16 x i8> %x) { 191 %a = shl <16 x i8> %v, %x 192 ret <16 x i8> %a 193} 194 195; CHECK-LABEL: shr_s_v16i8: 196; NO-SIMD128-NOT: i8x16 197; SIMD128-NEXT: .functype shr_s_v16i8 (v128, i32) -> (v128){{$}} 198; SIMD128-NEXT: i8x16.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 199; SIMD128-NEXT: return $pop[[R]]{{$}} 200define <16 x i8> @shr_s_v16i8(<16 x i8> %v, i8 %x) { 201 %t = insertelement <16 x i8> undef, i8 %x, i32 0 202 %s = shufflevector <16 x i8> %t, <16 x i8> undef, 203 <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, 204 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 205 %a = ashr <16 x i8> %v, %s 206 ret <16 x i8> %a 207} 208 209; CHECK-LABEL: shr_s_vec_v16i8: 210; NO-SIMD128-NOT: i8x16 211; SIMD128-NEXT: .functype shr_s_vec_v16i8 (v128, v128) -> (v128){{$}} 212; SIMD128-NEXT: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}} 213; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}} 214; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}} 215; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 216; SIMD128-NEXT: i32.shr_s $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]] 217; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]] 218; Skip 14 lanes 219; SIMD128: i8x16.extract_lane_s $push[[L4:[0-9]+]]=, $0, 15{{$}} 220; SIMD128-NEXT: i8x16.extract_lane_u $push[[L5:[0-9]+]]=, $1, 15{{$}} 221; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}} 222; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 223; SIMD128-NEXT: i32.shr_s $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 224; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}} 225; SIMD128-NEXT: return $pop[[R]]{{$}} 226define <16 x i8> @shr_s_vec_v16i8(<16 x i8> %v, <16 x i8> %x) { 227 %a = ashr <16 x i8> %v, %x 228 ret <16 x i8> %a 229} 230 231; CHECK-LABEL: shr_u_v16i8: 232; NO-SIMD128-NOT: i8x16 233; SIMD128-NEXT: .functype shr_u_v16i8 (v128, i32) -> (v128){{$}} 234; SIMD128-NEXT: i8x16.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 235; SIMD128-NEXT: return $pop[[R]]{{$}} 236define <16 x i8> @shr_u_v16i8(<16 x i8> %v, i8 %x) { 237 %t = insertelement <16 x i8> undef, i8 %x, i32 0 238 %s = shufflevector <16 x i8> %t, <16 x i8> undef, 239 <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, 240 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 241 %a = lshr <16 x i8> %v, %s 242 ret <16 x i8> %a 243} 244 245; CHECK-LABEL: shr_u_vec_v16i8: 246; NO-SIMD128-NOT: i8x16 247; SIMD128-NEXT: .functype shr_u_vec_v16i8 (v128, v128) -> (v128){{$}} 248; SIMD128-NEXT: i8x16.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}} 249; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}} 250; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}} 251; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 252; SIMD128-NEXT: i32.shr_u $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]] 253; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]] 254; Skip 14 lanes 255; SIMD128: i8x16.extract_lane_u $push[[L4:[0-9]+]]=, $0, 15{{$}} 256; SIMD128-NEXT: i8x16.extract_lane_u $push[[L5:[0-9]+]]=, $1, 15{{$}} 257; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}} 258; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 259; SIMD128-NEXT: i32.shr_u $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 260; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}} 261; SIMD128-NEXT: return $pop[[R]]{{$}} 262define <16 x i8> @shr_u_vec_v16i8(<16 x i8> %v, <16 x i8> %x) { 263 %a = lshr <16 x i8> %v, %x 264 ret <16 x i8> %a 265} 266 267; CHECK-LABEL: and_v16i8: 268; NO-SIMD128-NOT: v128 269; SIMD128-NEXT: .functype and_v16i8 (v128, v128) -> (v128){{$}} 270; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 271; SIMD128-NEXT: return $pop[[R]]{{$}} 272define <16 x i8> @and_v16i8(<16 x i8> %x, <16 x i8> %y) { 273 %a = and <16 x i8> %x, %y 274 ret <16 x i8> %a 275} 276 277; CHECK-LABEL: or_v16i8: 278; NO-SIMD128-NOT: v128 279; SIMD128-NEXT: .functype or_v16i8 (v128, v128) -> (v128){{$}} 280; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 281; SIMD128-NEXT: return $pop[[R]]{{$}} 282define <16 x i8> @or_v16i8(<16 x i8> %x, <16 x i8> %y) { 283 %a = or <16 x i8> %x, %y 284 ret <16 x i8> %a 285} 286 287; CHECK-LABEL: xor_v16i8: 288; NO-SIMD128-NOT: v128 289; SIMD128-NEXT: .functype xor_v16i8 (v128, v128) -> (v128){{$}} 290; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 291; SIMD128-NEXT: return $pop[[R]]{{$}} 292define <16 x i8> @xor_v16i8(<16 x i8> %x, <16 x i8> %y) { 293 %a = xor <16 x i8> %x, %y 294 ret <16 x i8> %a 295} 296 297; CHECK-LABEL: not_v16i8: 298; NO-SIMD128-NOT: v128 299; SIMD128-NEXT: .functype not_v16i8 (v128) -> (v128){{$}} 300; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 301; SIMD128-NEXT: return $pop[[R]]{{$}} 302define <16 x i8> @not_v16i8(<16 x i8> %x) { 303 %a = xor <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, 304 i8 -1, i8 -1, i8 -1, i8 -1, 305 i8 -1, i8 -1, i8 -1, i8 -1, 306 i8 -1, i8 -1, i8 -1, i8 -1> 307 ret <16 x i8> %a 308} 309 310; CHECK-LABEL: andnot_v16i8: 311; NO-SIMD128-NOT: v128 312; SIMD128-NEXT: .functype andnot_v16i8 (v128, v128) -> (v128){{$}} 313; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 314; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 315; SIMD128-FAST-NEXT: v128.not 316; SIMD128-FAST-NEXT: v128.and 317; SIMD128-FAST-NEXT: return 318define <16 x i8> @andnot_v16i8(<16 x i8> %x, <16 x i8> %y) { 319 %inv_y = xor <16 x i8> %y, 320 <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 321 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 322 %a = and <16 x i8> %x, %inv_y 323 ret <16 x i8> %a 324} 325 326; CHECK-LABEL: bitselect_v16i8: 327; NO-SIMD128-NOT: v128 328; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}} 329; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 330; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 331; SIMD128-FAST-NEXT: v128.and 332; SIMD128-FAST-NEXT: v128.not 333; SIMD128-FAST-NEXT: v128.and 334; SIMD128-FAST-NEXT: v128.or 335; SIMD128-FAST-NEXT: return 336define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) { 337 %masked_v1 = and <16 x i8> %c, %v1 338 %inv_mask = xor <16 x i8> %c, 339 <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 340 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 341 %masked_v2 = and <16 x i8> %inv_mask, %v2 342 %a = or <16 x i8> %masked_v1, %masked_v2 343 ret <16 x i8> %a 344} 345 346; ============================================================================== 347; 8 x i16 348; ============================================================================== 349; CHECK-LABEL: add_v8i16: 350; NO-SIMD128-NOT: i16x8 351; SIMD128-NEXT: .functype add_v8i16 (v128, v128) -> (v128){{$}} 352; SIMD128-NEXT: i16x8.add $push[[R:[0-9]+]]=, $0, $1{{$}} 353; SIMD128-NEXT: return $pop[[R]]{{$}} 354define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) { 355 %a = add <8 x i16> %x, %y 356 ret <8 x i16> %a 357} 358 359; CHECK-LABEL: sub_v8i16: 360; NO-SIMD128-NOT: i16x8 361; SIMD128-NEXT: .functype sub_v8i16 (v128, v128) -> (v128){{$}} 362; SIMD128-NEXT: i16x8.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 363; SIMD128-NEXT: return $pop[[R]]{{$}} 364define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) { 365 %a = sub <8 x i16> %x, %y 366 ret <8 x i16> %a 367} 368 369; CHECK-LABEL: mul_v8i16: 370; NO-SIMD128-NOT: i16x8 371; SIMD128-NEXT: .functype mul_v8i16 (v128, v128) -> (v128){{$}} 372; SIMD128-NEXT: i16x8.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 373; SIMD128-NEXT: return $pop[[R]]{{$}} 374define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) { 375 %a = mul <8 x i16> %x, %y 376 ret <8 x i16> %a 377} 378 379; CHECK-LABEL: min_s_v8i16: 380; NO-SIMD128-NOT: i16x8 381; SIMD128-NEXT: .functype min_s_v8i16 (v128, v128) -> (v128){{$}} 382; SIMD128-NEXT: i16x8.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 383; SIMD128-NEXT: return $pop[[R]]{{$}} 384define <8 x i16> @min_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 385 %c = icmp slt <8 x i16> %x, %y 386 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 387 ret <8 x i16> %a 388} 389 390; CHECK-LABEL: min_u_v8i16: 391; NO-SIMD128-NOT: i16x8 392; SIMD128-NEXT: .functype min_u_v8i16 (v128, v128) -> (v128){{$}} 393; SIMD128-NEXT: i16x8.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 394; SIMD128-NEXT: return $pop[[R]]{{$}} 395define <8 x i16> @min_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 396 %c = icmp ult <8 x i16> %x, %y 397 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 398 ret <8 x i16> %a 399} 400 401; CHECK-LABEL: max_s_v8i16: 402; NO-SIMD128-NOT: i16x8 403; SIMD128-NEXT: .functype max_s_v8i16 (v128, v128) -> (v128){{$}} 404; SIMD128-NEXT: i16x8.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 405; SIMD128-NEXT: return $pop[[R]]{{$}} 406define <8 x i16> @max_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 407 %c = icmp sgt <8 x i16> %x, %y 408 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 409 ret <8 x i16> %a 410} 411 412; CHECK-LABEL: max_u_v8i16: 413; NO-SIMD128-NOT: i16x8 414; SIMD128-NEXT: .functype max_u_v8i16 (v128, v128) -> (v128){{$}} 415; SIMD128-NEXT: i16x8.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 416; SIMD128-NEXT: return $pop[[R]]{{$}} 417define <8 x i16> @max_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 418 %c = icmp ugt <8 x i16> %x, %y 419 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 420 ret <8 x i16> %a 421} 422 423; CHECK-LABEL: avgr_u_v8i16: 424; NO-SIMD128-NOT: i16x8 425; SIMD128-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}} 426; SIMD128-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 427; SIMD128-NEXT: return $pop[[R]]{{$}} 428define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 429 %a = add nuw <8 x i16> %x, %y 430 %b = add nuw <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 431 %c = udiv <8 x i16> %b, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> 432 ret <8 x i16> %c 433} 434 435; CHECK-LABEL: avgr_u_v8i16_wrap: 436; NO-SIMD128-NOT: i16x8 437; SIMD128-NEXT: .functype avgr_u_v8i16_wrap (v128, v128) -> (v128){{$}} 438; SIMD128-NOT: i16x8.avgr_u 439define <8 x i16> @avgr_u_v8i16_wrap(<8 x i16> %x, <8 x i16> %y) { 440 %a = add <8 x i16> %x, %y 441 %b = add <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 442 %c = udiv <8 x i16> %b, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> 443 ret <8 x i16> %c 444} 445 446; CHECK-LABEL: abs_v8i16: 447; NO-SIMD128-NOT: i16x8 448; SIMD128-NEXT: .functype abs_v8i16 (v128) -> (v128){{$}} 449; SIMD128-NEXT: i16x8.abs $push[[R:[0-9]+]]=, $0{{$}} 450; SIMD128-NEXT: return $pop[[R]]{{$}} 451define <8 x i16> @abs_v8i16(<8 x i16> %x) { 452 %a = sub <8 x i16> zeroinitializer, %x 453 %b = icmp slt <8 x i16> %x, zeroinitializer 454 %c = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %x 455 ret <8 x i16> %c 456} 457 458; CHECK-LABEL: neg_v8i16: 459; NO-SIMD128-NOT: i16x8 460; SIMD128-NEXT: .functype neg_v8i16 (v128) -> (v128){{$}} 461; SIMD128-NEXT: i16x8.neg $push[[R:[0-9]+]]=, $0{{$}} 462; SIMD128-NEXT: return $pop[[R]]{{$}} 463define <8 x i16> @neg_v8i16(<8 x i16> %x) { 464 %a = sub <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, 465 %x 466 ret <8 x i16> %a 467} 468 469; CHECK-LABEL: shl_v8i16: 470; NO-SIMD128-NOT: i16x8 471; SIMD128-NEXT: .functype shl_v8i16 (v128, i32) -> (v128){{$}} 472; SIMD128-NEXT: i16x8.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 473; SIMD128-NEXT: return $pop[[R]]{{$}} 474define <8 x i16> @shl_v8i16(<8 x i16> %v, i16 %x) { 475 %t = insertelement <8 x i16> undef, i16 %x, i32 0 476 %s = shufflevector <8 x i16> %t, <8 x i16> undef, 477 <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 478 %a = shl <8 x i16> %v, %s 479 ret <8 x i16> %a 480} 481 482; CHECK-LABEL: shl_const_v8i16: 483; NO-SIMD128-NOT: i16x8 484; SIMD128-NEXT: .functype shl_const_v8i16 (v128) -> (v128){{$}} 485; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5 486; SIMD128-NEXT: i16x8.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 487; SIMD128-NEXT: return $pop[[R]]{{$}} 488define <8 x i16> @shl_const_v8i16(<8 x i16> %v) { 489 %a = shl <8 x i16> %v, 490 <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> 491 ret <8 x i16> %a 492} 493 494; CHECK-LABEL: shl_vec_v8i16: 495; NO-SIMD128-NOT: i16x8 496; SIMD128-NEXT: .functype shl_vec_v8i16 (v128, v128) -> (v128){{$}} 497; SIMD128-NEXT: i16x8.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}} 498; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}} 499; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}} 500; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 501; SIMD128-NEXT: i32.shl $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}} 502; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}} 503; Skip 6 lanes 504; SIMD128: i16x8.extract_lane_u $push[[L4:[0-9]+]]=, $0, 7{{$}} 505; SIMD128-NEXT: i16x8.extract_lane_u $push[[L5:[0-9]+]]=, $1, 7{{$}} 506; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}} 507; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 508; SIMD128-NEXT: i32.shl $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 509; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}} 510; SIMD128-NEXT: return $pop[[R]]{{$}} 511define <8 x i16> @shl_vec_v8i16(<8 x i16> %v, <8 x i16> %x) { 512 %a = shl <8 x i16> %v, %x 513 ret <8 x i16> %a 514} 515 516; CHECK-LABEL: shr_s_v8i16: 517; NO-SIMD128-NOT: i16x8 518; SIMD128-NEXT: .functype shr_s_v8i16 (v128, i32) -> (v128){{$}} 519; SIMD128-NEXT: i16x8.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 520; SIMD128-NEXT: return $pop[[R]]{{$}} 521define <8 x i16> @shr_s_v8i16(<8 x i16> %v, i16 %x) { 522 %t = insertelement <8 x i16> undef, i16 %x, i32 0 523 %s = shufflevector <8 x i16> %t, <8 x i16> undef, 524 <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 525 %a = ashr <8 x i16> %v, %s 526 ret <8 x i16> %a 527} 528 529; CHECK-LABEL: shr_s_vec_v8i16: 530; NO-SIMD128-NOT: i16x8 531; SIMD128-NEXT: .functype shr_s_vec_v8i16 (v128, v128) -> (v128){{$}} 532; SIMD128-NEXT: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}} 533; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}} 534; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}} 535; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 536; SIMD128-NEXT: i32.shr_s $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}} 537; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}} 538; Skip 6 lanes 539; SIMD128: i16x8.extract_lane_s $push[[L4:[0-9]+]]=, $0, 7{{$}} 540; SIMD128-NEXT: i16x8.extract_lane_u $push[[L5:[0-9]+]]=, $1, 7{{$}} 541; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}} 542; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 543; SIMD128-NEXT: i32.shr_s $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 544; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}} 545; SIMD128-NEXT: return $pop[[R]]{{$}} 546define <8 x i16> @shr_s_vec_v8i16(<8 x i16> %v, <8 x i16> %x) { 547 %a = ashr <8 x i16> %v, %x 548 ret <8 x i16> %a 549} 550 551; CHECK-LABEL: shr_u_v8i16: 552; NO-SIMD128-NOT: i16x8 553; SIMD128-NEXT: .functype shr_u_v8i16 (v128, i32) -> (v128){{$}} 554; SIMD128-NEXT: i16x8.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 555; SIMD128-NEXT: return $pop[[R]]{{$}} 556define <8 x i16> @shr_u_v8i16(<8 x i16> %v, i16 %x) { 557 %t = insertelement <8 x i16> undef, i16 %x, i32 0 558 %s = shufflevector <8 x i16> %t, <8 x i16> undef, 559 <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 560 %a = lshr <8 x i16> %v, %s 561 ret <8 x i16> %a 562} 563 564; CHECK-LABEL: shr_u_vec_v8i16: 565; NO-SIMD128-NOT: i16x8 566; SIMD128-NEXT: .functype shr_u_vec_v8i16 (v128, v128) -> (v128){{$}} 567; SIMD128-NEXT: i16x8.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}} 568; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}} 569; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}} 570; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 571; SIMD128-NEXT: i32.shr_u $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}} 572; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}} 573; Skip 6 lanes 574; SIMD128: i16x8.extract_lane_u $push[[L4:[0-9]+]]=, $0, 7{{$}} 575; SIMD128-NEXT: i16x8.extract_lane_u $push[[L5:[0-9]+]]=, $1, 7{{$}} 576; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}} 577; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 578; SIMD128-NEXT: i32.shr_u $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 579; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}} 580; SIMD128-NEXT: return $pop[[R]]{{$}} 581define <8 x i16> @shr_u_vec_v8i16(<8 x i16> %v, <8 x i16> %x) { 582 %a = lshr <8 x i16> %v, %x 583 ret <8 x i16> %a 584} 585 586; CHECK-LABEL: and_v8i16: 587; NO-SIMD128-NOT: v128 588; SIMD128-NEXT: .functype and_v8i16 (v128, v128) -> (v128){{$}} 589; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 590; SIMD128-NEXT: return $pop[[R]]{{$}} 591define <8 x i16> @and_v8i16(<8 x i16> %x, <8 x i16> %y) { 592 %a = and <8 x i16> %x, %y 593 ret <8 x i16> %a 594} 595 596; CHECK-LABEL: or_v8i16: 597; NO-SIMD128-NOT: v128 598; SIMD128-NEXT: .functype or_v8i16 (v128, v128) -> (v128){{$}} 599; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 600; SIMD128-NEXT: return $pop[[R]]{{$}} 601define <8 x i16> @or_v8i16(<8 x i16> %x, <8 x i16> %y) { 602 %a = or <8 x i16> %x, %y 603 ret <8 x i16> %a 604} 605 606; CHECK-LABEL: xor_v8i16: 607; NO-SIMD128-NOT: v128 608; SIMD128-NEXT: .functype xor_v8i16 (v128, v128) -> (v128){{$}} 609; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 610; SIMD128-NEXT: return $pop[[R]]{{$}} 611define <8 x i16> @xor_v8i16(<8 x i16> %x, <8 x i16> %y) { 612 %a = xor <8 x i16> %x, %y 613 ret <8 x i16> %a 614} 615 616; CHECK-LABEL: not_v8i16: 617; NO-SIMD128-NOT: v128 618; SIMD128-NEXT: .functype not_v8i16 (v128) -> (v128){{$}} 619; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 620; SIMD128-NEXT: return $pop[[R]]{{$}} 621define <8 x i16> @not_v8i16(<8 x i16> %x) { 622 %a = xor <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, 623 i16 -1, i16 -1, i16 -1, i16 -1> 624 ret <8 x i16> %a 625} 626 627; CHECK-LABEL: andnot_v8i16: 628; NO-SIMD128-NOT: v128 629; SIMD128-NEXT: .functype andnot_v8i16 (v128, v128) -> (v128){{$}} 630; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 631; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 632; SIMD128-FAST-NEXT: v128.not 633; SIMD128-FAST-NEXT: v128.and 634; SIMD128-FAST-NEXT: return 635define <8 x i16> @andnot_v8i16(<8 x i16> %x, <8 x i16> %y) { 636 %inv_y = xor <8 x i16> %y, 637 <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 638 %a = and <8 x i16> %x, %inv_y 639 ret <8 x i16> %a 640} 641 642; CHECK-LABEL: bitselect_v8i16: 643; NO-SIMD128-NOT: v128 644; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}} 645; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 646; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 647; SIMD128-FAST-NEXT: v128.and 648; SIMD128-FAST-NEXT: v128.not 649; SIMD128-FAST-NEXT: v128.and 650; SIMD128-FAST-NEXT: v128.or 651; SIMD128-FAST-NEXT: return 652define <8 x i16> @bitselect_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) { 653 %masked_v1 = and <8 x i16> %v1, %c 654 %inv_mask = xor <8 x i16> 655 <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, 656 %c 657 %masked_v2 = and <8 x i16> %v2, %inv_mask 658 %a = or <8 x i16> %masked_v1, %masked_v2 659 ret <8 x i16> %a 660} 661 662; CHECK-LABEL: extmul_low_s_v8i16: 663; NO-SIMD128-NOT: i16x8 664; SIMD128-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}} 665; SIMD128-SLOW-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}} 666; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 667define <8 x i16> @extmul_low_s_v8i16(<16 x i8> %v1, <16 x i8> %v2) { 668 %low1 = shufflevector <16 x i8> %v1, <16 x i8> undef, 669 <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 670 %low2 = shufflevector <16 x i8> %v2, <16 x i8> undef, 671 <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 672 %extended1 = sext <8 x i8> %low1 to <8 x i16> 673 %extended2 = sext <8 x i8> %low2 to <8 x i16> 674 %a = mul <8 x i16> %extended1, %extended2 675 ret <8 x i16> %a 676} 677 678; CHECK-LABEL: extmul_high_s_v8i16: 679; NO-SIMD128-NOT: i16x8 680; SIMD128-NEXT: .functype extmul_high_s_v8i16 (v128, v128) -> (v128){{$}} 681; SIMD128-SLOW-NEXT: i16x8.extmul_high_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}} 682; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 683define <8 x i16> @extmul_high_s_v8i16(<16 x i8> %v1, <16 x i8> %v2) { 684 %high1 = shufflevector <16 x i8> %v1, <16 x i8> undef, 685 <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 686 %high2 = shufflevector <16 x i8> %v2, <16 x i8> undef, 687 <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 688 %extended1 = sext <8 x i8> %high1 to <8 x i16> 689 %extended2 = sext <8 x i8> %high2 to <8 x i16> 690 %a = mul <8 x i16> %extended1, %extended2 691 ret <8 x i16> %a 692} 693 694; CHECK-LABEL: extmul_low_u_v8i16: 695; NO-SIMD128-NOT: i16x8 696; SIMD128-NEXT: .functype extmul_low_u_v8i16 (v128, v128) -> (v128){{$}} 697; SIMD128-SLOW-NEXT: i16x8.extmul_low_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}} 698; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 699define <8 x i16> @extmul_low_u_v8i16(<16 x i8> %v1, <16 x i8> %v2) { 700 %low1 = shufflevector <16 x i8> %v1, <16 x i8> undef, 701 <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 702 %low2 = shufflevector <16 x i8> %v2, <16 x i8> undef, 703 <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 704 %extended1 = zext <8 x i8> %low1 to <8 x i16> 705 %extended2 = zext <8 x i8> %low2 to <8 x i16> 706 %a = mul <8 x i16> %extended1, %extended2 707 ret <8 x i16> %a 708} 709 710; CHECK-LABEL: extmul_high_u_v8i16: 711; NO-SIMD128-NOT: i16x8 712; SIMD128-NEXT: .functype extmul_high_u_v8i16 (v128, v128) -> (v128){{$}} 713; SIMD128-SLOW-NEXT: i16x8.extmul_high_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}} 714; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 715define <8 x i16> @extmul_high_u_v8i16(<16 x i8> %v1, <16 x i8> %v2) { 716 %high1 = shufflevector <16 x i8> %v1, <16 x i8> undef, 717 <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 718 %high2 = shufflevector <16 x i8> %v2, <16 x i8> undef, 719 <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 720 %extended1 = zext <8 x i8> %high1 to <8 x i16> 721 %extended2 = zext <8 x i8> %high2 to <8 x i16> 722 %a = mul <8 x i16> %extended1, %extended2 723 ret <8 x i16> %a 724} 725 726; ============================================================================== 727; 4 x i32 728; ============================================================================== 729; CHECK-LABEL: add_v4i32: 730; NO-SIMD128-NOT: i32x4 731; SIMD128-NEXT: .functype add_v4i32 (v128, v128) -> (v128){{$}} 732; SIMD128-NEXT: i32x4.add $push[[R:[0-9]+]]=, $0, $1{{$}} 733; SIMD128-NEXT: return $pop[[R]]{{$}} 734define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) { 735 %a = add <4 x i32> %x, %y 736 ret <4 x i32> %a 737} 738 739; CHECK-LABEL: sub_v4i32: 740; NO-SIMD128-NOT: i32x4 741; SIMD128-NEXT: .functype sub_v4i32 (v128, v128) -> (v128){{$}} 742; SIMD128-NEXT: i32x4.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 743; SIMD128-NEXT: return $pop[[R]]{{$}} 744define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) { 745 %a = sub <4 x i32> %x, %y 746 ret <4 x i32> %a 747} 748 749; CHECK-LABEL: mul_v4i32: 750; NO-SIMD128-NOT: i32x4 751; SIMD128-NEXT: .functype mul_v4i32 (v128, v128) -> (v128){{$}} 752; SIMD128-NEXT: i32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 753; SIMD128-NEXT: return $pop[[R]]{{$}} 754define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) { 755 %a = mul <4 x i32> %x, %y 756 ret <4 x i32> %a 757} 758 759; CHECK-LABEL: min_s_v4i32: 760; NO-SIMD128-NOT: i32x4 761; SIMD128-NEXT: .functype min_s_v4i32 (v128, v128) -> (v128){{$}} 762; SIMD128-NEXT: i32x4.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 763; SIMD128-NEXT: return $pop[[R]]{{$}} 764define <4 x i32> @min_s_v4i32(<4 x i32> %x, <4 x i32> %y) { 765 %c = icmp slt <4 x i32> %x, %y 766 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 767 ret <4 x i32> %a 768} 769 770; CHECK-LABEL: min_u_v4i32: 771; NO-SIMD128-NOT: i32x4 772; SIMD128-NEXT: .functype min_u_v4i32 (v128, v128) -> (v128){{$}} 773; SIMD128-NEXT: i32x4.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 774; SIMD128-NEXT: return $pop[[R]]{{$}} 775define <4 x i32> @min_u_v4i32(<4 x i32> %x, <4 x i32> %y) { 776 %c = icmp ult <4 x i32> %x, %y 777 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 778 ret <4 x i32> %a 779} 780 781; CHECK-LABEL: max_s_v4i32: 782; NO-SIMD128-NOT: i32x4 783; SIMD128-NEXT: .functype max_s_v4i32 (v128, v128) -> (v128){{$}} 784; SIMD128-NEXT: i32x4.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 785; SIMD128-NEXT: return $pop[[R]]{{$}} 786define <4 x i32> @max_s_v4i32(<4 x i32> %x, <4 x i32> %y) { 787 %c = icmp sgt <4 x i32> %x, %y 788 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 789 ret <4 x i32> %a 790} 791 792; CHECK-LABEL: max_u_v4i32: 793; NO-SIMD128-NOT: i32x4 794; SIMD128-NEXT: .functype max_u_v4i32 (v128, v128) -> (v128){{$}} 795; SIMD128-NEXT: i32x4.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 796; SIMD128-NEXT: return $pop[[R]]{{$}} 797define <4 x i32> @max_u_v4i32(<4 x i32> %x, <4 x i32> %y) { 798 %c = icmp ugt <4 x i32> %x, %y 799 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 800 ret <4 x i32> %a 801} 802 803; CHECK-LABEL: abs_v4i32: 804; NO-SIMD128-NOT: i32x4 805; SIMD128-NEXT: .functype abs_v4i32 (v128) -> (v128){{$}} 806; SIMD128-NEXT: i32x4.abs $push[[R:[0-9]+]]=, $0{{$}} 807; SIMD128-NEXT: return $pop[[R]]{{$}} 808define <4 x i32> @abs_v4i32(<4 x i32> %x) { 809 %a = sub <4 x i32> zeroinitializer, %x 810 %b = icmp slt <4 x i32> %x, zeroinitializer 811 %c = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %x 812 ret <4 x i32> %c 813} 814 815; CHECK-LABEL: neg_v4i32: 816; NO-SIMD128-NOT: i32x4 817; SIMD128-NEXT: .functype neg_v4i32 (v128) -> (v128){{$}} 818; SIMD128-NEXT: i32x4.neg $push[[R:[0-9]+]]=, $0{{$}} 819; SIMD128-NEXT: return $pop[[R]]{{$}} 820define <4 x i32> @neg_v4i32(<4 x i32> %x) { 821 %a = sub <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %x 822 ret <4 x i32> %a 823} 824 825; CHECK-LABEL: shl_v4i32: 826; NO-SIMD128-NOT: i32x4 827; SIMD128-NEXT: .functype shl_v4i32 (v128, i32) -> (v128){{$}} 828; SIMD128-NEXT: i32x4.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 829; SIMD128-NEXT: return $pop[[R]]{{$}} 830define <4 x i32> @shl_v4i32(<4 x i32> %v, i32 %x) { 831 %t = insertelement <4 x i32> undef, i32 %x, i32 0 832 %s = shufflevector <4 x i32> %t, <4 x i32> undef, 833 <4 x i32> <i32 0, i32 0, i32 0, i32 0> 834 %a = shl <4 x i32> %v, %s 835 ret <4 x i32> %a 836} 837 838; CHECK-LABEL: shl_const_v4i32: 839; NO-SIMD128-NOT: i32x4 840; SIMD128-NEXT: .functype shl_const_v4i32 (v128) -> (v128){{$}} 841; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5 842; SIMD128-NEXT: i32x4.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 843; SIMD128-NEXT: return $pop[[R]]{{$}} 844define <4 x i32> @shl_const_v4i32(<4 x i32> %v) { 845 %a = shl <4 x i32> %v, <i32 5, i32 5, i32 5, i32 5> 846 ret <4 x i32> %a 847} 848 849; CHECK-LABEL: shl_vec_v4i32: 850; NO-SIMD128-NOT: i32x4 851; SIMD128-NEXT: .functype shl_vec_v4i32 (v128, v128) -> (v128){{$}} 852; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 853; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 854; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 855; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 856; Skip 2 lanes 857; SIMD128: i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}} 858; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}} 859; SIMD128-NEXT: i32.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 860; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}} 861; SIMD128-NEXT: return $pop[[R]]{{$}} 862define <4 x i32> @shl_vec_v4i32(<4 x i32> %v, <4 x i32> %x) { 863 %a = shl <4 x i32> %v, %x 864 ret <4 x i32> %a 865} 866 867; CHECK-LABEL: shr_s_v4i32: 868; NO-SIMD128-NOT: i32x4 869; SIMD128-NEXT: .functype shr_s_v4i32 (v128, i32) -> (v128){{$}} 870; SIMD128-NEXT: i32x4.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 871; SIMD128-NEXT: return $pop[[R]]{{$}} 872define <4 x i32> @shr_s_v4i32(<4 x i32> %v, i32 %x) { 873 %t = insertelement <4 x i32> undef, i32 %x, i32 0 874 %s = shufflevector <4 x i32> %t, <4 x i32> undef, 875 <4 x i32> <i32 0, i32 0, i32 0, i32 0> 876 %a = ashr <4 x i32> %v, %s 877 ret <4 x i32> %a 878} 879 880; CHECK-LABEL: shr_s_vec_v4i32: 881; NO-SIMD128-NOT: i32x4 882; SIMD128-NEXT: .functype shr_s_vec_v4i32 (v128, v128) -> (v128){{$}} 883; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 884; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 885; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 886; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 887; Skip 2 lanes 888; SIMD128: i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}} 889; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}} 890; SIMD128-NEXT: i32.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 891; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}} 892; SIMD128-NEXT: return $pop[[R]]{{$}} 893define <4 x i32> @shr_s_vec_v4i32(<4 x i32> %v, <4 x i32> %x) { 894 %a = ashr <4 x i32> %v, %x 895 ret <4 x i32> %a 896} 897 898; CHECK-LABEL: shr_u_v4i32: 899; NO-SIMD128-NOT: i32x4 900; SIMD128-NEXT: .functype shr_u_v4i32 (v128, i32) -> (v128){{$}} 901; SIMD128-NEXT: i32x4.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 902; SIMD128-NEXT: return $pop[[R]]{{$}} 903define <4 x i32> @shr_u_v4i32(<4 x i32> %v, i32 %x) { 904 %t = insertelement <4 x i32> undef, i32 %x, i32 0 905 %s = shufflevector <4 x i32> %t, <4 x i32> undef, 906 <4 x i32> <i32 0, i32 0, i32 0, i32 0> 907 %a = lshr <4 x i32> %v, %s 908 ret <4 x i32> %a 909} 910 911; CHECK-LABEL: shr_u_vec_v4i32: 912; NO-SIMD128-NOT: i32x4 913; SIMD128-NEXT: .functype shr_u_vec_v4i32 (v128, v128) -> (v128){{$}} 914; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 915; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 916; SIMD128-NEXT: i32.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 917; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 918; Skip 2 lanes 919; SIMD128: i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}} 920; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}} 921; SIMD128-NEXT: i32.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 922; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}} 923; SIMD128-NEXT: return $pop[[R]]{{$}} 924define <4 x i32> @shr_u_vec_v4i32(<4 x i32> %v, <4 x i32> %x) { 925 %a = lshr <4 x i32> %v, %x 926 ret <4 x i32> %a 927} 928 929; CHECK-LABEL: and_v4i32: 930; NO-SIMD128-NOT: v128 931; SIMD128-NEXT: .functype and_v4i32 (v128, v128) -> (v128){{$}} 932; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 933; SIMD128-NEXT: return $pop[[R]]{{$}} 934define <4 x i32> @and_v4i32(<4 x i32> %x, <4 x i32> %y) { 935 %a = and <4 x i32> %x, %y 936 ret <4 x i32> %a 937} 938 939; CHECK-LABEL: or_v4i32: 940; NO-SIMD128-NOT: v128 941; SIMD128-NEXT: .functype or_v4i32 (v128, v128) -> (v128){{$}} 942; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 943; SIMD128-NEXT: return $pop[[R]]{{$}} 944define <4 x i32> @or_v4i32(<4 x i32> %x, <4 x i32> %y) { 945 %a = or <4 x i32> %x, %y 946 ret <4 x i32> %a 947} 948 949; CHECK-LABEL: xor_v4i32: 950; NO-SIMD128-NOT: v128 951; SIMD128-NEXT: .functype xor_v4i32 (v128, v128) -> (v128){{$}} 952; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 953; SIMD128-NEXT: return $pop[[R]]{{$}} 954define <4 x i32> @xor_v4i32(<4 x i32> %x, <4 x i32> %y) { 955 %a = xor <4 x i32> %x, %y 956 ret <4 x i32> %a 957} 958 959; CHECK-LABEL: not_v4i32: 960; NO-SIMD128-NOT: v128 961; SIMD128-NEXT: .functype not_v4i32 (v128) -> (v128){{$}} 962; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 963; SIMD128-NEXT: return $pop[[R]]{{$}} 964define <4 x i32> @not_v4i32(<4 x i32> %x) { 965 %a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 966 ret <4 x i32> %a 967} 968 969; CHECK-LABEL: andnot_v4i32: 970; NO-SIMD128-NOT: v128 971; SIMD128-NEXT: .functype andnot_v4i32 (v128, v128) -> (v128){{$}} 972; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 973; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 974; SIMD128-FAST-NEXT: v128.not 975; SIMD128-FAST-NEXT: v128.and 976; SIMD128-FAST-NEXT: return 977define <4 x i32> @andnot_v4i32(<4 x i32> %x, <4 x i32> %y) { 978 %inv_y = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1> 979 %a = and <4 x i32> %x, %inv_y 980 ret <4 x i32> %a 981} 982 983; CHECK-LABEL: bitselect_v4i32: 984; NO-SIMD128-NOT: v128 985; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}} 986; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 987; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 988; SIMD128-FAST-NEXT: v128.not 989; SIMD128-FAST-NEXT: v128.and 990; SIMD128-FAST-NEXT: v128.and 991; SIMD128-FAST-NEXT: v128.or 992; SIMD128-FAST-NEXT: return 993define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) { 994 %masked_v1 = and <4 x i32> %c, %v1 995 %inv_mask = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %c 996 %masked_v2 = and <4 x i32> %inv_mask, %v2 997 %a = or <4 x i32> %masked_v2, %masked_v1 998 ret <4 x i32> %a 999} 1000 1001; CHECK-LABEL: extmul_low_s_v4i32: 1002; NO-SIMD128-NOT: i32x4 1003; SIMD128-NEXT: .functype extmul_low_s_v4i32 (v128, v128) -> (v128){{$}} 1004; SIMD128-SLOW-NEXT: i32x4.extmul_low_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 1005; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1006define <4 x i32> @extmul_low_s_v4i32(<8 x i16> %v1, <8 x i16> %v2) { 1007 %low1 = shufflevector <8 x i16> %v1, <8 x i16> undef, 1008 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1009 %low2 = shufflevector <8 x i16> %v2, <8 x i16> undef, 1010 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1011 %extended1 = sext <4 x i16> %low1 to <4 x i32> 1012 %extended2 = sext <4 x i16> %low2 to <4 x i32> 1013 %a = mul <4 x i32> %extended1, %extended2 1014 ret <4 x i32> %a 1015} 1016 1017; CHECK-LABEL: extmul_high_s_v4i32: 1018; NO-SIMD128-NOT: i32x4 1019; SIMD128-NEXT: .functype extmul_high_s_v4i32 (v128, v128) -> (v128){{$}} 1020; SIMD128-SLOW-NEXT: i32x4.extmul_high_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 1021; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1022define <4 x i32> @extmul_high_s_v4i32(<8 x i16> %v1, <8 x i16> %v2) { 1023 %high1 = shufflevector <8 x i16> %v1, <8 x i16> undef, 1024 <4 x i32> <i32 4, i32 5, i32 6, i32 7> 1025 %high2 = shufflevector <8 x i16> %v2, <8 x i16> undef, 1026 <4 x i32> <i32 4, i32 5, i32 6, i32 7> 1027 %extended1 = sext <4 x i16> %high1 to <4 x i32> 1028 %extended2 = sext <4 x i16> %high2 to <4 x i32> 1029 %a = mul <4 x i32> %extended1, %extended2 1030 ret <4 x i32> %a 1031} 1032 1033; CHECK-LABEL: extmul_low_u_v4i32: 1034; NO-SIMD128-NOT: i32x4 1035; SIMD128-NEXT: .functype extmul_low_u_v4i32 (v128, v128) -> (v128){{$}} 1036; SIMD128-SLOW-NEXT: i32x4.extmul_low_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 1037; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1038define <4 x i32> @extmul_low_u_v4i32(<8 x i16> %v1, <8 x i16> %v2) { 1039 %low1 = shufflevector <8 x i16> %v1, <8 x i16> undef, 1040 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1041 %low2 = shufflevector <8 x i16> %v2, <8 x i16> undef, 1042 <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1043 %extended1 = zext <4 x i16> %low1 to <4 x i32> 1044 %extended2 = zext <4 x i16> %low2 to <4 x i32> 1045 %a = mul <4 x i32> %extended1, %extended2 1046 ret <4 x i32> %a 1047} 1048 1049; CHECK-LABEL: extmul_high_u_v4i32: 1050; NO-SIMD128-NOT: i32x4 1051; SIMD128-NEXT: .functype extmul_high_u_v4i32 (v128, v128) -> (v128){{$}} 1052; SIMD128-SLOW-NEXT: i32x4.extmul_high_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 1053; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1054define <4 x i32> @extmul_high_u_v4i32(<8 x i16> %v1, <8 x i16> %v2) { 1055 %high1 = shufflevector <8 x i16> %v1, <8 x i16> undef, 1056 <4 x i32> <i32 4, i32 5, i32 6, i32 7> 1057 %high2 = shufflevector <8 x i16> %v2, <8 x i16> undef, 1058 <4 x i32> <i32 4, i32 5, i32 6, i32 7> 1059 %extended1 = zext <4 x i16> %high1 to <4 x i32> 1060 %extended2 = zext <4 x i16> %high2 to <4 x i32> 1061 %a = mul <4 x i32> %extended1, %extended2 1062 ret <4 x i32> %a 1063} 1064 1065; ============================================================================== 1066; 2 x i64 1067; ============================================================================== 1068; CHECK-LABEL: add_v2i64: 1069; NO-SIMD128-NOT: i64x2 1070; SIMD128-NEXT: .functype add_v2i64 (v128, v128) -> (v128){{$}} 1071; SIMD128-NEXT: i64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}} 1072; SIMD128-NEXT: return $pop[[R]]{{$}} 1073define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) { 1074 %a = add <2 x i64> %x, %y 1075 ret <2 x i64> %a 1076} 1077 1078; CHECK-LABEL: sub_v2i64: 1079; NO-SIMD128-NOT: i64x2 1080; SIMD128-NEXT: .functype sub_v2i64 (v128, v128) -> (v128){{$}} 1081; SIMD128-NEXT: i64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 1082; SIMD128-NEXT: return $pop[[R]]{{$}} 1083define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) { 1084 %a = sub <2 x i64> %x, %y 1085 ret <2 x i64> %a 1086} 1087 1088; CHECK-LABEL: mul_v2i64: 1089; NO-SIMD128-NOT: i64x2 1090; SIMD128-NEXT: .functype mul_v2i64 (v128, v128) -> (v128){{$}} 1091; SIMD128: i64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 1092; SIMD128-NEXT: return $pop[[R]]{{$}} 1093define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) { 1094 %a = mul <2 x i64> %x, %y 1095 ret <2 x i64> %a 1096} 1097 1098; CHECK-LABEL: abs_v2i64: 1099; NO-SIMD128-NOT: i64x2: 1100; SIMD128-NEXT: .functype abs_v2i64 (v128) -> (v128){{$}} 1101; SIMD128-NEXT: i64x2.abs $push[[R:[0-9]+]]=, $0{{$}} 1102; SIMD128-NEXT: return $pop[[R]]{{$}} 1103define <2 x i64> @abs_v2i64(<2 x i64> %x) { 1104 %a = sub <2 x i64> zeroinitializer, %x 1105 %b = icmp slt <2 x i64> %x, zeroinitializer 1106 %c = select <2 x i1> %b, <2 x i64> %a, <2 x i64> %x 1107 ret <2 x i64> %c 1108} 1109 1110; CHECK-LABEL: neg_v2i64: 1111; NO-SIMD128-NOT: i64x2 1112; SIMD128-NEXT: .functype neg_v2i64 (v128) -> (v128){{$}} 1113; SIMD128-NEXT: i64x2.neg $push[[R:[0-9]+]]=, $0{{$}} 1114; SIMD128-NEXT: return $pop[[R]]{{$}} 1115define <2 x i64> @neg_v2i64(<2 x i64> %x) { 1116 %a = sub <2 x i64> <i64 0, i64 0>, %x 1117 ret <2 x i64> %a 1118} 1119 1120; CHECK-LABEL: shl_v2i64: 1121; NO-SIMD128-NOT: i64x2 1122; SIMD128-NEXT: .functype shl_v2i64 (v128, i32) -> (v128){{$}} 1123; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 1124; SIMD128-NEXT: return $pop[[R]]{{$}} 1125define <2 x i64> @shl_v2i64(<2 x i64> %v, i32 %x) { 1126 %x2 = zext i32 %x to i64 1127 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1128 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1129 %a = shl <2 x i64> %v, %s 1130 ret <2 x i64> %a 1131} 1132 1133; CHECK-LABEL: shl_sext_v2i64: 1134; NO-SIMD128-NOT: i64x2 1135; SIMD128-NEXT: .functype shl_sext_v2i64 (v128, i32) -> (v128){{$}} 1136; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 1137; SIMD128-NEXT: return $pop[[R]]{{$}} 1138define <2 x i64> @shl_sext_v2i64(<2 x i64> %v, i32 %x) { 1139 %x2 = sext i32 %x to i64 1140 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1141 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1142 %a = shl <2 x i64> %v, %s 1143 ret <2 x i64> %a 1144} 1145 1146; CHECK-LABEL: shl_noext_v2i64: 1147; NO-SIMD128-NOT: i64x2 1148; SIMD128-NEXT: .functype shl_noext_v2i64 (v128, i64) -> (v128){{$}} 1149; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}} 1150; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1151; SIMD128-NEXT: return $pop[[R]]{{$}} 1152define <2 x i64> @shl_noext_v2i64(<2 x i64> %v, i64 %x) { 1153 %t = insertelement <2 x i64> undef, i64 %x, i32 0 1154 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1155 %a = shl <2 x i64> %v, %s 1156 ret <2 x i64> %a 1157} 1158 1159; CHECK-LABEL: shl_const_v2i64: 1160; NO-SIMD128-NOT: i64x2 1161; SIMD128-NEXT: .functype shl_const_v2i64 (v128) -> (v128){{$}} 1162; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}} 1163; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1164; SIMD128-NEXT: return $pop[[R]]{{$}} 1165define <2 x i64> @shl_const_v2i64(<2 x i64> %v) { 1166 %a = shl <2 x i64> %v, <i64 5, i64 5> 1167 ret <2 x i64> %a 1168} 1169 1170; CHECK-LABEL: shl_vec_v2i64: 1171; NO-SIMD128-NOT: i64x2 1172; SIMD128-NEXT: .functype shl_vec_v2i64 (v128, v128) -> (v128){{$}} 1173; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 1174; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 1175; SIMD128-NEXT: i64.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 1176; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 1177; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}} 1178; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}} 1179; SIMD128-NEXT: i64.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 1180; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}} 1181; SIMD128-NEXT: return $pop[[R]]{{$}} 1182define <2 x i64> @shl_vec_v2i64(<2 x i64> %v, <2 x i64> %x) { 1183 %a = shl <2 x i64> %v, %x 1184 ret <2 x i64> %a 1185} 1186 1187; CHECK-LABEL: shr_s_v2i64: 1188; NO-SIMD128-NOT: i64x2 1189; SIMD128-NEXT: .functype shr_s_v2i64 (v128, i32) -> (v128){{$}} 1190; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 1191; SIMD128-NEXT: return $pop[[R]]{{$}} 1192define <2 x i64> @shr_s_v2i64(<2 x i64> %v, i32 %x) { 1193 %x2 = zext i32 %x to i64 1194 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1195 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1196 %a = ashr <2 x i64> %v, %s 1197 ret <2 x i64> %a 1198} 1199 1200; CHECK-LABEL: shr_s_sext_v2i64: 1201; NO-SIMD128-NOT: i64x2 1202; SIMD128-NEXT: .functype shr_s_sext_v2i64 (v128, i32) -> (v128){{$}} 1203; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 1204; SIMD128-NEXT: return $pop[[R]]{{$}} 1205define <2 x i64> @shr_s_sext_v2i64(<2 x i64> %v, i32 %x) { 1206 %x2 = sext i32 %x to i64 1207 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1208 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1209 %a = ashr <2 x i64> %v, %s 1210 ret <2 x i64> %a 1211} 1212 1213; CHECK-LABEL: shr_s_noext_v2i64: 1214; NO-SIMD128-NOT: i64x2 1215; SIMD128-NEXT: .functype shr_s_noext_v2i64 (v128, i64) -> (v128){{$}} 1216; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}} 1217; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1218; SIMD128-NEXT: return $pop[[R]]{{$}} 1219define <2 x i64> @shr_s_noext_v2i64(<2 x i64> %v, i64 %x) { 1220 %t = insertelement <2 x i64> undef, i64 %x, i32 0 1221 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1222 %a = ashr <2 x i64> %v, %s 1223 ret <2 x i64> %a 1224} 1225 1226; CHECK-LABEL: shr_s_const_v2i64: 1227; NO-SIMD128-NOT: i64x2 1228; SIMD128-NEXT: .functype shr_s_const_v2i64 (v128) -> (v128){{$}} 1229; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}} 1230; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1231; SIMD128-NEXT: return $pop[[R]]{{$}} 1232define <2 x i64> @shr_s_const_v2i64(<2 x i64> %v) { 1233 %a = ashr <2 x i64> %v, <i64 5, i64 5> 1234 ret <2 x i64> %a 1235} 1236 1237; CHECK-LABEL: shr_s_vec_v2i64: 1238; NO-SIMD128-NOT: i64x2 1239; SIMD128-NEXT: .functype shr_s_vec_v2i64 (v128, v128) -> (v128){{$}} 1240; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 1241; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 1242; SIMD128-NEXT: i64.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 1243; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 1244; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}} 1245; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}} 1246; SIMD128-NEXT: i64.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 1247; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}} 1248; SIMD128-NEXT: return $pop[[R]]{{$}} 1249define <2 x i64> @shr_s_vec_v2i64(<2 x i64> %v, <2 x i64> %x) { 1250 %a = ashr <2 x i64> %v, %x 1251 ret <2 x i64> %a 1252} 1253 1254; CHECK-LABEL: shr_u_v2i64: 1255; NO-SIMD128-NOT: i64x2 1256; SIMD128-NEXT: .functype shr_u_v2i64 (v128, i32) -> (v128){{$}} 1257; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 1258; SIMD128-NEXT: return $pop[[R]]{{$}} 1259define <2 x i64> @shr_u_v2i64(<2 x i64> %v, i32 %x) { 1260 %x2 = zext i32 %x to i64 1261 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1262 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1263 %a = lshr <2 x i64> %v, %s 1264 ret <2 x i64> %a 1265} 1266 1267; CHECK-LABEL: shr_u_sext_v2i64: 1268; NO-SIMD128-NOT: i64x2 1269; SIMD128-NEXT: .functype shr_u_sext_v2i64 (v128, i32) -> (v128){{$}} 1270; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 1271; SIMD128-NEXT: return $pop[[R]]{{$}} 1272define <2 x i64> @shr_u_sext_v2i64(<2 x i64> %v, i32 %x) { 1273 %x2 = sext i32 %x to i64 1274 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1275 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1276 %a = lshr <2 x i64> %v, %s 1277 ret <2 x i64> %a 1278} 1279 1280; CHECK-LABEL: shr_u_noext_v2i64: 1281; NO-SIMD128-NOT: i64x2 1282; SIMD128-NEXT: .functype shr_u_noext_v2i64 (v128, i64) -> (v128){{$}} 1283; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}} 1284; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1285; SIMD128-NEXT: return $pop[[R]]{{$}} 1286define <2 x i64> @shr_u_noext_v2i64(<2 x i64> %v, i64 %x) { 1287 %t = insertelement <2 x i64> undef, i64 %x, i32 0 1288 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1289 %a = lshr <2 x i64> %v, %s 1290 ret <2 x i64> %a 1291} 1292 1293; CHECK-LABEL: shr_u_const_v2i64: 1294; NO-SIMD128-NOT: i64x2 1295; SIMD128-NEXT: .functype shr_u_const_v2i64 (v128) -> (v128){{$}} 1296; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}} 1297; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1298; SIMD128-NEXT: return $pop[[R]]{{$}} 1299define <2 x i64> @shr_u_const_v2i64(<2 x i64> %v) { 1300 %a = lshr <2 x i64> %v, <i64 5, i64 5> 1301 ret <2 x i64> %a 1302} 1303 1304; CHECK-LABEL: shr_u_vec_v2i64: 1305; NO-SIMD128-NOT: i64x2 1306; SIMD128-NEXT: .functype shr_u_vec_v2i64 (v128, v128) -> (v128){{$}} 1307; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 1308; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 1309; SIMD128-NEXT: i64.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 1310; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 1311; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}} 1312; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}} 1313; SIMD128-NEXT: i64.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 1314; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}} 1315; SIMD128-NEXT: return $pop[[R]]{{$}} 1316define <2 x i64> @shr_u_vec_v2i64(<2 x i64> %v, <2 x i64> %x) { 1317 %a = lshr <2 x i64> %v, %x 1318 ret <2 x i64> %a 1319} 1320 1321; CHECK-LABEL: and_v2i64: 1322; NO-SIMD128-NOT: v128 1323; SIMD128-NEXT: .functype and_v2i64 (v128, v128) -> (v128){{$}} 1324; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 1325; SIMD128-NEXT: return $pop[[R]]{{$}} 1326define <2 x i64> @and_v2i64(<2 x i64> %x, <2 x i64> %y) { 1327 %a = and <2 x i64> %x, %y 1328 ret <2 x i64> %a 1329} 1330 1331; CHECK-LABEL: or_v2i64: 1332; NO-SIMD128-NOT: v128 1333; SIMD128-NEXT: .functype or_v2i64 (v128, v128) -> (v128){{$}} 1334; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 1335; SIMD128-NEXT: return $pop[[R]]{{$}} 1336define <2 x i64> @or_v2i64(<2 x i64> %x, <2 x i64> %y) { 1337 %a = or <2 x i64> %x, %y 1338 ret <2 x i64> %a 1339} 1340 1341; CHECK-LABEL: xor_v2i64: 1342; NO-SIMD128-NOT: v128 1343; SIMD128-NEXT: .functype xor_v2i64 (v128, v128) -> (v128){{$}} 1344; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 1345; SIMD128-NEXT: return $pop[[R]]{{$}} 1346define <2 x i64> @xor_v2i64(<2 x i64> %x, <2 x i64> %y) { 1347 %a = xor <2 x i64> %x, %y 1348 ret <2 x i64> %a 1349} 1350 1351; CHECK-LABEL: not_v2i64: 1352; NO-SIMD128-NOT: v128 1353; SIMD128-NEXT: .functype not_v2i64 (v128) -> (v128){{$}} 1354; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 1355; SIMD128-NEXT: return $pop[[R]]{{$}} 1356define <2 x i64> @not_v2i64(<2 x i64> %x) { 1357 %a = xor <2 x i64> %x, <i64 -1, i64 -1> 1358 ret <2 x i64> %a 1359} 1360 1361; CHECK-LABEL: andnot_v2i64: 1362; NO-SIMD128-NOT: v128 1363; SIMD128-NEXT: .functype andnot_v2i64 (v128, v128) -> (v128){{$}} 1364; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 1365; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1366; SIMD128-FAST-NEXT: v128.not 1367; SIMD128-FAST-NEXT: v128.and 1368; SIMD128-FAST-NEXT: return 1369define <2 x i64> @andnot_v2i64(<2 x i64> %x, <2 x i64> %y) { 1370 %inv_y = xor <2 x i64> %y, <i64 -1, i64 -1> 1371 %a = and <2 x i64> %x, %inv_y 1372 ret <2 x i64> %a 1373} 1374 1375; CHECK-LABEL: bitselect_v2i64: 1376; NO-SIMD128-NOT: v128 1377; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}} 1378; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 1379; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1380; SIMD128-FAST-NEXT: v128.not 1381; SIMD128-FAST-NEXT: v128.and 1382; SIMD128-FAST-NEXT: v128.and 1383; SIMD128-FAST-NEXT: v128.or 1384; SIMD128-FAST-NEXT: return 1385define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) { 1386 %masked_v1 = and <2 x i64> %v1, %c 1387 %inv_mask = xor <2 x i64> <i64 -1, i64 -1>, %c 1388 %masked_v2 = and <2 x i64> %v2, %inv_mask 1389 %a = or <2 x i64> %masked_v2, %masked_v1 1390 ret <2 x i64> %a 1391} 1392 1393; CHECK-LABEL: extmul_low_s_v2i64: 1394; NO-SIMD128-NOT: i64x2 1395; SIMD128-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}} 1396; SIMD128-SLOW-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 1397; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1398define <2 x i64> @extmul_low_s_v2i64(<4 x i32> %v1, <4 x i32> %v2) { 1399 %low1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 0, i32 1> 1400 %low2 = shufflevector <4 x i32> %v2, <4 x i32> undef, <2 x i32> <i32 0, i32 1> 1401 %extended1 = sext <2 x i32> %low1 to <2 x i64> 1402 %extended2 = sext <2 x i32> %low2 to <2 x i64> 1403 %a = mul <2 x i64> %extended1, %extended2 1404 ret <2 x i64> %a 1405} 1406 1407; CHECK-LABEL: extmul_high_s_v2i64: 1408; NO-SIMD128-NOT: i64x2 1409; SIMD128-NEXT: .functype extmul_high_s_v2i64 (v128, v128) -> (v128){{$}} 1410; SIMD128-SLOW-NEXT: i64x2.extmul_high_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 1411; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1412define <2 x i64> @extmul_high_s_v2i64(<4 x i32> %v1, <4 x i32> %v2) { 1413 %high1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> 1414 %high2 = shufflevector <4 x i32> %v2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> 1415 %extended1 = sext <2 x i32> %high1 to <2 x i64> 1416 %extended2 = sext <2 x i32> %high2 to <2 x i64> 1417 %a = mul <2 x i64> %extended1, %extended2 1418 ret <2 x i64> %a 1419} 1420 1421; CHECK-LABEL: extmul_low_u_v2i64: 1422; NO-SIMD128-NOT: i64x2 1423; SIMD128-NEXT: .functype extmul_low_u_v2i64 (v128, v128) -> (v128){{$}} 1424; SIMD128-SLOW-NEXT: i64x2.extmul_low_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 1425; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1426define <2 x i64> @extmul_low_u_v2i64(<4 x i32> %v1, <4 x i32> %v2) { 1427 %low1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 0, i32 1> 1428 %low2 = shufflevector <4 x i32> %v2, <4 x i32> undef, <2 x i32> <i32 0, i32 1> 1429 %extended1 = zext <2 x i32> %low1 to <2 x i64> 1430 %extended2 = zext <2 x i32> %low2 to <2 x i64> 1431 %a = mul <2 x i64> %extended1, %extended2 1432 ret <2 x i64> %a 1433} 1434 1435; CHECK-LABEL: extmul_high_u_v2i64: 1436; NO-SIMD128-NOT: i64x2 1437; SIMD128-NEXT: .functype extmul_high_u_v2i64 (v128, v128) -> (v128){{$}} 1438; SIMD128-SLOW-NEXT: i64x2.extmul_high_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 1439; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1440define <2 x i64> @extmul_high_u_v2i64(<4 x i32> %v1, <4 x i32> %v2) { 1441 %high1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> 1442 %high2 = shufflevector <4 x i32> %v2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> 1443 %extended1 = zext <2 x i32> %high1 to <2 x i64> 1444 %extended2 = zext <2 x i32> %high2 to <2 x i64> 1445 %a = mul <2 x i64> %extended1, %extended2 1446 ret <2 x i64> %a 1447} 1448 1449; ============================================================================== 1450; 4 x float 1451; ============================================================================== 1452; CHECK-LABEL: neg_v4f32: 1453; NO-SIMD128-NOT: f32x4 1454; SIMD128-NEXT: .functype neg_v4f32 (v128) -> (v128){{$}} 1455; SIMD128-NEXT: f32x4.neg $push[[R:[0-9]+]]=, $0{{$}} 1456; SIMD128-NEXT: return $pop[[R]]{{$}} 1457define <4 x float> @neg_v4f32(<4 x float> %x) { 1458 ; nsz makes this semantically equivalent to flipping sign bit 1459 %a = fsub nsz <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, %x 1460 ret <4 x float> %a 1461} 1462 1463; CHECK-LABEL: abs_v4f32: 1464; NO-SIMD128-NOT: f32x4 1465; SIMD128-NEXT: .functype abs_v4f32 (v128) -> (v128){{$}} 1466; SIMD128-NEXT: f32x4.abs $push[[R:[0-9]+]]=, $0{{$}} 1467; SIMD128-NEXT: return $pop[[R]]{{$}} 1468declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone 1469define <4 x float> @abs_v4f32(<4 x float> %x) { 1470 %a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x) 1471 ret <4 x float> %a 1472} 1473 1474; CHECK-LABEL: min_unordered_v4f32: 1475; NO-SIMD128-NOT: f32x4 1476; SIMD128-NEXT: .functype min_unordered_v4f32 (v128) -> (v128){{$}} 1477; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2{{$}} 1478; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1479; SIMD128-NEXT: return $pop[[R]]{{$}} 1480define <4 x float> @min_unordered_v4f32(<4 x float> %x) { 1481 %cmps = fcmp ule <4 x float> %x, <float 5., float 5., float 5., float 5.> 1482 %a = select <4 x i1> %cmps, <4 x float> %x, 1483 <4 x float> <float 5., float 5., float 5., float 5.> 1484 ret <4 x float> %a 1485} 1486 1487; CHECK-LABEL: max_unordered_v4f32: 1488; NO-SIMD128-NOT: f32x4 1489; SIMD128-NEXT: .functype max_unordered_v4f32 (v128) -> (v128){{$}} 1490; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2 1491; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1492; SIMD128-NEXT: return $pop[[R]]{{$}} 1493define <4 x float> @max_unordered_v4f32(<4 x float> %x) { 1494 %cmps = fcmp uge <4 x float> %x, <float 5., float 5., float 5., float 5.> 1495 %a = select <4 x i1> %cmps, <4 x float> %x, 1496 <4 x float> <float 5., float 5., float 5., float 5.> 1497 ret <4 x float> %a 1498} 1499 1500; CHECK-LABEL: min_ordered_v4f32: 1501; NO-SIMD128-NOT: f32x4 1502; SIMD128-NEXT: .functype min_ordered_v4f32 (v128) -> (v128){{$}} 1503; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2{{$}} 1504; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1505; SIMD128-NEXT: return $pop[[R]]{{$}} 1506define <4 x float> @min_ordered_v4f32(<4 x float> %x) { 1507 %cmps = fcmp ole <4 x float> <float 5., float 5., float 5., float 5.>, %x 1508 %a = select <4 x i1> %cmps, 1509 <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x 1510 ret <4 x float> %a 1511} 1512 1513; CHECK-LABEL: max_ordered_v4f32: 1514; NO-SIMD128-NOT: f32x4 1515; SIMD128-NEXT: .functype max_ordered_v4f32 (v128) -> (v128){{$}} 1516; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2{{$}} 1517; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1518; SIMD128-NEXT: return $pop[[R]]{{$}} 1519define <4 x float> @max_ordered_v4f32(<4 x float> %x) { 1520 %cmps = fcmp oge <4 x float> <float 5., float 5., float 5., float 5.>, %x 1521 %a = select <4 x i1> %cmps, 1522 <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x 1523 ret <4 x float> %a 1524} 1525 1526; CHECK-LABEL: min_intrinsic_v4f32: 1527; NO-SIMD128-NOT: f32x4 1528; SIMD128-NEXT: .functype min_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1529; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $1{{$}} 1530; SIMD128-NEXT: return $pop[[R]]{{$}} 1531declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>) 1532define <4 x float> @min_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1533 %a = call <4 x float> @llvm.minimum.v4f32(<4 x float> %x, <4 x float> %y) 1534 ret <4 x float> %a 1535} 1536 1537; CHECK-LABEL: minnum_intrinsic_v4f32: 1538; NO-SIMD128-NOT: f32x4 1539; SIMD128-NEXT: .functype minnum_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1540; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $1{{$}} 1541; SIMD128-NEXT: return $pop[[R]]{{$}} 1542declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) 1543define <4 x float> @minnum_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1544 %a = call nnan <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float> %y) 1545 ret <4 x float> %a 1546} 1547 1548; CHECK-LABEL: max_intrinsic_v4f32: 1549; NO-SIMD128-NOT: f32x4 1550; SIMD128-NEXT: .functype max_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1551; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $1{{$}} 1552; SIMD128-NEXT: return $pop[[R]]{{$}} 1553declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>) 1554define <4 x float> @max_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1555 %a = call <4 x float> @llvm.maximum.v4f32(<4 x float> %x, <4 x float> %y) 1556 ret <4 x float> %a 1557} 1558 1559; CHECK-LABEL: maxnum_intrinsic_v4f32: 1560; NO-SIMD128-NOT: f32x4 1561; SIMD128-NEXT: .functype maxnum_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1562; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $1{{$}} 1563; SIMD128-NEXT: return $pop[[R]]{{$}} 1564declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) 1565define <4 x float> @maxnum_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1566 %a = call nnan <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float> %y) 1567 ret <4 x float> %a 1568} 1569 1570; CHECK-LABEL: min_const_intrinsic_v4f32: 1571; NO-SIMD128-NOT: f32x4 1572; SIMD128-NEXT: .functype min_const_intrinsic_v4f32 () -> (v128){{$}} 1573; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2{{$}} 1574; SIMD128-NEXT: return $pop[[R]]{{$}} 1575define <4 x float> @min_const_intrinsic_v4f32() { 1576 %a = call <4 x float> @llvm.minimum.v4f32( 1577 <4 x float> <float 42., float 42., float 42., float 42.>, 1578 <4 x float> <float 5., float 5., float 5., float 5.> 1579 ) 1580 ret <4 x float> %a 1581} 1582 1583; CHECK-LABEL: max_const_intrinsic_v4f32: 1584; NO-SIMD128-NOT: f32x4 1585; SIMD128-NEXT: .functype max_const_intrinsic_v4f32 () -> (v128){{$}} 1586; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.5p5, 0x1.5p5, 0x1.5p5, 0x1.5p5{{$}} 1587; SIMD128-NEXT: return $pop[[R]]{{$}} 1588define <4 x float> @max_const_intrinsic_v4f32() { 1589 %a = call <4 x float> @llvm.maximum.v4f32( 1590 <4 x float> <float 42., float 42., float 42., float 42.>, 1591 <4 x float> <float 5., float 5., float 5., float 5.> 1592 ) 1593 ret <4 x float> %a 1594} 1595 1596; CHECK-LABEL: pmin_v4f32: 1597; NO-SIMD128-NOT: f32x4 1598; SIMD128-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}} 1599; SIMD128-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 1600; SIMD128-NEXT: return $pop[[R]]{{$}} 1601define <4 x float> @pmin_v4f32(<4 x float> %x, <4 x float> %y) { 1602 %c = fcmp olt <4 x float> %y, %x 1603 %a = select <4 x i1> %c, <4 x float> %y, <4 x float> %x 1604 ret <4 x float> %a 1605} 1606 1607; CHECK-LABEL: pmin_int_v4f32: 1608; NO-SIMD128-NOT: f32x4 1609; SIMD128-NEXT: .functype pmin_int_v4f32 (v128, v128) -> (v128){{$}} 1610; SIMD128-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 1611; SIMD128-NEXT: return $pop[[R]]{{$}} 1612define <4 x i32> @pmin_int_v4f32(<4 x i32> %x, <4 x i32> %y) { 1613 %fx = bitcast <4 x i32> %x to <4 x float> 1614 %fy = bitcast <4 x i32> %y to <4 x float> 1615 %c = fcmp olt <4 x float> %fy, %fx 1616 %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> %x 1617 ret <4 x i32> %a 1618} 1619 1620; CHECK-LABEL: pmax_v4f32: 1621; NO-SIMD128-NOT: f32x4 1622; SIMD128-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}} 1623; SIMD128-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 1624; SIMD128-NEXT: return $pop[[R]]{{$}} 1625define <4 x float> @pmax_v4f32(<4 x float> %x, <4 x float> %y) { 1626 %c = fcmp olt <4 x float> %x, %y 1627 %a = select <4 x i1> %c, <4 x float> %y, <4 x float> %x 1628 ret <4 x float> %a 1629} 1630 1631; CHECK-LABEL: pmax_int_v4f32: 1632; NO-SIMD128-NOT: f32x4 1633; SIMD128-NEXT: .functype pmax_int_v4f32 (v128, v128) -> (v128){{$}} 1634; SIMD128-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 1635; SIMD128-NEXT: return $pop[[R]]{{$}} 1636define <4 x i32> @pmax_int_v4f32(<4 x i32> %x, <4 x i32> %y) { 1637 %fx = bitcast <4 x i32> %x to <4 x float> 1638 %fy = bitcast <4 x i32> %y to <4 x float> 1639 %c = fcmp olt <4 x float> %fx, %fy 1640 %a = select <4 x i1> %c, <4 x i32> %y, <4 x i32> %x 1641 ret <4 x i32> %a 1642} 1643 1644; CHECK-LABEL: add_v4f32: 1645; NO-SIMD128-NOT: f32x4 1646; SIMD128-NEXT: .functype add_v4f32 (v128, v128) -> (v128){{$}} 1647; SIMD128-NEXT: f32x4.add $push[[R:[0-9]+]]=, $0, $1{{$}} 1648; SIMD128-NEXT: return $pop[[R]]{{$}} 1649define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) { 1650 %a = fadd <4 x float> %x, %y 1651 ret <4 x float> %a 1652} 1653 1654; CHECK-LABEL: sub_v4f32: 1655; NO-SIMD128-NOT: f32x4 1656; SIMD128-NEXT: .functype sub_v4f32 (v128, v128) -> (v128){{$}} 1657; SIMD128-NEXT: f32x4.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 1658; SIMD128-NEXT: return $pop[[R]]{{$}} 1659define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) { 1660 %a = fsub <4 x float> %x, %y 1661 ret <4 x float> %a 1662} 1663 1664; CHECK-LABEL: div_v4f32: 1665; NO-SIMD128-NOT: f32x4 1666; SIMD128-NEXT: .functype div_v4f32 (v128, v128) -> (v128){{$}} 1667; SIMD128-NEXT: f32x4.div $push[[R:[0-9]+]]=, $0, $1{{$}} 1668; SIMD128-NEXT: return $pop[[R]]{{$}} 1669define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) { 1670 %a = fdiv <4 x float> %x, %y 1671 ret <4 x float> %a 1672} 1673 1674; CHECK-LABEL: mul_v4f32: 1675; NO-SIMD128-NOT: f32x4 1676; SIMD128-NEXT: .functype mul_v4f32 (v128, v128) -> (v128){{$}} 1677; SIMD128-NEXT: f32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 1678; SIMD128-NEXT: return $pop[[R]]{{$}} 1679define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) { 1680 %a = fmul <4 x float> %x, %y 1681 ret <4 x float> %a 1682} 1683 1684; CHECK-LABEL: sqrt_v4f32: 1685; NO-SIMD128-NOT: f32x4 1686; SIMD128-NEXT: .functype sqrt_v4f32 (v128) -> (v128){{$}} 1687; SIMD128-NEXT: f32x4.sqrt $push[[R:[0-9]+]]=, $0{{$}} 1688; SIMD128-NEXT: return $pop[[R]]{{$}} 1689declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) 1690define <4 x float> @sqrt_v4f32(<4 x float> %x) { 1691 %a = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) 1692 ret <4 x float> %a 1693} 1694 1695; ============================================================================== 1696; 2 x double 1697; ============================================================================== 1698; CHECK-LABEL: neg_v2f64: 1699; NO-SIMD128-NOT: f64x2 1700; SIMD128-NEXT: .functype neg_v2f64 (v128) -> (v128){{$}} 1701; SIMD128-NEXT: f64x2.neg $push[[R:[0-9]+]]=, $0{{$}} 1702; SIMD128-NEXT: return $pop[[R]]{{$}} 1703define <2 x double> @neg_v2f64(<2 x double> %x) { 1704 ; nsz makes this semantically equivalent to flipping sign bit 1705 %a = fsub nsz <2 x double> <double 0., double 0.>, %x 1706 ret <2 x double> %a 1707} 1708 1709; CHECK-LABEL: abs_v2f64: 1710; NO-SIMD128-NOT: f64x2 1711; SIMD128-NEXT: .functype abs_v2f64 (v128) -> (v128){{$}} 1712; SIMD128-NEXT: f64x2.abs $push[[R:[0-9]+]]=, $0{{$}} 1713; SIMD128-NEXT: return $pop[[R]]{{$}} 1714declare <2 x double> @llvm.fabs.v2f64(<2 x double>) nounwind readnone 1715define <2 x double> @abs_v2f64(<2 x double> %x) { 1716 %a = call <2 x double> @llvm.fabs.v2f64(<2 x double> %x) 1717 ret <2 x double> %a 1718} 1719 1720; CHECK-LABEL: min_unordered_v2f64: 1721; NO-SIMD128-NOT: f64x2 1722; SIMD128-NEXT: .functype min_unordered_v2f64 (v128) -> (v128){{$}} 1723; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2{{$}} 1724; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1725; SIMD128-NEXT: return $pop[[R]]{{$}} 1726define <2 x double> @min_unordered_v2f64(<2 x double> %x) { 1727 %cmps = fcmp ule <2 x double> %x, <double 5., double 5.> 1728 %a = select <2 x i1> %cmps, <2 x double> %x, 1729 <2 x double> <double 5., double 5.> 1730 ret <2 x double> %a 1731} 1732 1733; CHECK-LABEL: max_unordered_v2f64: 1734; NO-SIMD128-NOT: f64x2 1735; SIMD128-NEXT: .functype max_unordered_v2f64 (v128) -> (v128){{$}} 1736; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2{{$}} 1737; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1738; SIMD128-NEXT: return $pop[[R]]{{$}} 1739define <2 x double> @max_unordered_v2f64(<2 x double> %x) { 1740 %cmps = fcmp uge <2 x double> %x, <double 5., double 5.> 1741 %a = select <2 x i1> %cmps, <2 x double> %x, 1742 <2 x double> <double 5., double 5.> 1743 ret <2 x double> %a 1744} 1745 1746; CHECK-LABEL: min_ordered_v2f64: 1747; NO-SIMD128-NOT: f64x2 1748; SIMD128-NEXT: .functype min_ordered_v2f64 (v128) -> (v128){{$}} 1749; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2{{$}} 1750; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1751; SIMD128-NEXT: return $pop[[R]]{{$}} 1752define <2 x double> @min_ordered_v2f64(<2 x double> %x) { 1753 %cmps = fcmp ole <2 x double> <double 5., double 5.>, %x 1754 %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>, 1755 <2 x double> %x 1756 ret <2 x double> %a 1757} 1758 1759; CHECK-LABEL: max_ordered_v2f64: 1760; NO-SIMD128-NOT: f64x2 1761; SIMD128-NEXT: .functype max_ordered_v2f64 (v128) -> (v128){{$}} 1762; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2{{$}} 1763; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1764; SIMD128-NEXT: return $pop[[R]]{{$}} 1765define <2 x double> @max_ordered_v2f64(<2 x double> %x) { 1766 %cmps = fcmp oge <2 x double> <double 5., double 5.>, %x 1767 %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>, 1768 <2 x double> %x 1769 ret <2 x double> %a 1770} 1771 1772; CHECK-LABEL: min_intrinsic_v2f64: 1773; NO-SIMD128-NOT: f64x2 1774; SIMD128-NEXT: .functype min_intrinsic_v2f64 (v128, v128) -> (v128){{$}} 1775; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $1{{$}} 1776; SIMD128-NEXT: return $pop[[R]]{{$}} 1777declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>) 1778define <2 x double> @min_intrinsic_v2f64(<2 x double> %x, <2 x double> %y) { 1779 %a = call <2 x double> @llvm.minimum.v2f64(<2 x double> %x, <2 x double> %y) 1780 ret <2 x double> %a 1781} 1782 1783; CHECK-LABEL: max_intrinsic_v2f64: 1784; NO-SIMD128-NOT: f64x2 1785; SIMD128-NEXT: .functype max_intrinsic_v2f64 (v128, v128) -> (v128){{$}} 1786; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $1{{$}} 1787; SIMD128-NEXT: return $pop[[R]]{{$}} 1788declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>) 1789define <2 x double> @max_intrinsic_v2f64(<2 x double> %x, <2 x double> %y) { 1790 %a = call <2 x double> @llvm.maximum.v2f64(<2 x double> %x, <2 x double> %y) 1791 ret <2 x double> %a 1792} 1793 1794; CHECK-LABEL: min_const_intrinsic_v2f64: 1795; NO-SIMD128-NOT: f64x2 1796; SIMD128-NEXT: .functype min_const_intrinsic_v2f64 () -> (v128){{$}} 1797; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.4p2, 0x1.4p2{{$}} 1798; SIMD128-NEXT: return $pop[[R]]{{$}} 1799define <2 x double> @min_const_intrinsic_v2f64() { 1800 %a = call <2 x double> @llvm.minimum.v2f64( 1801 <2 x double> <double 42., double 42.>, 1802 <2 x double> <double 5., double 5.> 1803 ) 1804 ret <2 x double> %a 1805} 1806 1807; CHECK-LABEL: max_const_intrinsic_v2f64: 1808; NO-SIMD128-NOT: f64x2 1809; SIMD128-NEXT: .functype max_const_intrinsic_v2f64 () -> (v128){{$}} 1810; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.5p5, 0x1.5p5{{$}} 1811; SIMD128-NEXT: return $pop[[R]]{{$}} 1812define <2 x double> @max_const_intrinsic_v2f64() { 1813 %a = call <2 x double> @llvm.maximum.v2f64( 1814 <2 x double> <double 42., double 42.>, 1815 <2 x double> <double 5., double 5.> 1816 ) 1817 ret <2 x double> %a 1818} 1819 1820; CHECK-LABEL: pmin_v2f64: 1821; NO-SIMD128-NOT: f64x2 1822; SIMD128-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}} 1823; SIMD128-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 1824; SIMD128-NEXT: return $pop[[R]]{{$}} 1825define <2 x double> @pmin_v2f64(<2 x double> %x, <2 x double> %y) { 1826 %c = fcmp olt <2 x double> %y, %x 1827 %a = select <2 x i1> %c, <2 x double> %y, <2 x double> %x 1828 ret <2 x double> %a 1829} 1830 1831; CHECK-LABEL: pmin_int_v2f64: 1832; NO-SIMD128-NOT: f64x2 1833; SIMD128-NEXT: .functype pmin_int_v2f64 (v128, v128) -> (v128){{$}} 1834; SIMD128-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 1835; SIMD128-NEXT: return $pop[[R]]{{$}} 1836define <2 x i64> @pmin_int_v2f64(<2 x i64> %x, <2 x i64> %y) { 1837 %fx = bitcast <2 x i64> %x to <2 x double> 1838 %fy = bitcast <2 x i64> %y to <2 x double> 1839 %c = fcmp olt <2 x double> %fy, %fx 1840 %a = select <2 x i1> %c, <2 x i64> %y, <2 x i64> %x 1841 ret <2 x i64> %a 1842} 1843 1844; CHECK-LABEL: pmax_v2f64: 1845; NO-SIMD128-NOT: f64x2 1846; SIMD128-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}} 1847; SIMD128-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 1848; SIMD128-NEXT: return $pop[[R]]{{$}} 1849define <2 x double> @pmax_v2f64(<2 x double> %x, <2 x double> %y) { 1850 %c = fcmp olt <2 x double> %x, %y 1851 %a = select <2 x i1> %c, <2 x double> %y, <2 x double> %x 1852 ret <2 x double> %a 1853} 1854 1855; CHECK-LABEL: pmax_int_v2f64: 1856; NO-SIMD128-NOT: f64x2 1857; SIMD128-NEXT: .functype pmax_int_v2f64 (v128, v128) -> (v128){{$}} 1858; SIMD128-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 1859; SIMD128-NEXT: return $pop[[R]]{{$}} 1860define <2 x i64> @pmax_int_v2f64(<2 x i64> %x, <2 x i64> %y) { 1861 %fx = bitcast <2 x i64> %x to <2 x double> 1862 %fy = bitcast <2 x i64> %y to <2 x double> 1863 %c = fcmp olt <2 x double> %fx, %fy 1864 %a = select <2 x i1> %c, <2 x i64> %y, <2 x i64> %x 1865 ret <2 x i64> %a 1866} 1867 1868; CHECK-LABEL: add_v2f64: 1869; NO-SIMD128-NOT: f64x2 1870; SIMD128-NEXT: .functype add_v2f64 (v128, v128) -> (v128){{$}} 1871; SIMD128-NEXT: f64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}} 1872; SIMD128-NEXT: return $pop[[R]]{{$}} 1873define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) { 1874 %a = fadd <2 x double> %x, %y 1875 ret <2 x double> %a 1876} 1877 1878; CHECK-LABEL: sub_v2f64: 1879; NO-SIMD128-NOT: f64x2 1880; SIMD128-NEXT: .functype sub_v2f64 (v128, v128) -> (v128){{$}} 1881; SIMD128-NEXT: f64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 1882; SIMD128-NEXT: return $pop[[R]]{{$}} 1883define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) { 1884 %a = fsub <2 x double> %x, %y 1885 ret <2 x double> %a 1886} 1887 1888; CHECK-LABEL: div_v2f64: 1889; NO-SIMD128-NOT: f64x2 1890; SIMD128-NEXT: .functype div_v2f64 (v128, v128) -> (v128){{$}} 1891; SIMD128-NEXT: f64x2.div $push[[R:[0-9]+]]=, $0, $1{{$}} 1892; SIMD128-NEXT: return $pop[[R]]{{$}} 1893define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) { 1894 %a = fdiv <2 x double> %x, %y 1895 ret <2 x double> %a 1896} 1897 1898; CHECK-LABEL: mul_v2f64: 1899; NO-SIMD128-NOT: f64x2 1900; SIMD128-NEXT: .functype mul_v2f64 (v128, v128) -> (v128){{$}} 1901; SIMD128-NEXT: f64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 1902; SIMD128-NEXT: return $pop[[R]]{{$}} 1903define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) { 1904 %a = fmul <2 x double> %x, %y 1905 ret <2 x double> %a 1906} 1907 1908; CHECK-LABEL: sqrt_v2f64: 1909; NO-SIMD128-NOT: f64x2 1910; SIMD128-NEXT: .functype sqrt_v2f64 (v128) -> (v128){{$}} 1911; SIMD128-NEXT: f64x2.sqrt $push[[R:[0-9]+]]=, $0{{$}} 1912; SIMD128-NEXT: return $pop[[R]]{{$}} 1913declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %x) 1914define <2 x double> @sqrt_v2f64(<2 x double> %x) { 1915 %a = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %x) 1916 ret <2 x double> %a 1917} 1918