1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW 2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST 3; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM 4; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM 5; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128 6; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128 7 8; check that a non-test run (including explicit locals pass) at least finishes 9; RUN: llc < %s -O0 -mattr=+unimplemented-simd128 10; RUN: llc < %s -O2 -mattr=+unimplemented-simd128 11 12; Test that basic SIMD128 arithmetic operations assemble as expected. 13 14target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" 15target triple = "wasm32-unknown-unknown" 16 17; ============================================================================== 18; 16 x i8 19; ============================================================================== 20; CHECK-LABEL: add_v16i8: 21; NO-SIMD128-NOT: i8x16 22; SIMD128-NEXT: .functype add_v16i8 (v128, v128) -> (v128){{$}} 23; SIMD128-NEXT: i8x16.add $push[[R:[0-9]+]]=, $0, $1{{$}} 24; SIMD128-NEXT: return $pop[[R]]{{$}} 25define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) { 26 %a = add <16 x i8> %x, %y 27 ret <16 x i8> %a 28} 29 30; CHECK-LABEL: sub_v16i8: 31; NO-SIMD128-NOT: i8x16 32; SIMD128-NEXT: .functype sub_v16i8 (v128, v128) -> (v128){{$}} 33; SIMD128-NEXT: i8x16.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 34; SIMD128-NEXT: return $pop[[R]]{{$}} 35define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) { 36 %a = sub <16 x i8> %x, %y 37 ret <16 x i8> %a 38} 39 40; CHECK-LABEL: mul_v16i8: 41; NO-SIMD128-NOT: i8x16 42; SIMD128-NEXT: .functype mul_v16i8 (v128, v128) -> (v128){{$}} 43; SIMD128-NEXT: i8x16.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 44; SIMD128-NEXT: return $pop[[R]]{{$}} 45define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) { 46 %a = mul <16 x i8> %x, %y 47 ret <16 x i8> %a 48} 49 50; CHECK-LABEL: min_s_v16i8: 51; NO-SIMD128-NOT: i8x16 52; SIMD128-NEXT: .functype min_s_v16i8 (v128, v128) -> (v128){{$}} 53; SIMD128-NEXT: i8x16.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 54; SIMD128-NEXT: return $pop[[R]]{{$}} 55define <16 x i8> @min_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 56 %c = icmp slt <16 x i8> %x, %y 57 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 58 ret <16 x i8> %a 59} 60 61; CHECK-LABEL: min_u_v16i8: 62; NO-SIMD128-NOT: i8x16 63; SIMD128-NEXT: .functype min_u_v16i8 (v128, v128) -> (v128){{$}} 64; SIMD128-NEXT: i8x16.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 65; SIMD128-NEXT: return $pop[[R]]{{$}} 66define <16 x i8> @min_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 67 %c = icmp ult <16 x i8> %x, %y 68 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 69 ret <16 x i8> %a 70} 71 72; CHECK-LABEL: max_s_v16i8: 73; NO-SIMD128-NOT: i8x16 74; SIMD128-NEXT: .functype max_s_v16i8 (v128, v128) -> (v128){{$}} 75; SIMD128-NEXT: i8x16.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 76; SIMD128-NEXT: return $pop[[R]]{{$}} 77define <16 x i8> @max_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 78 %c = icmp sgt <16 x i8> %x, %y 79 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 80 ret <16 x i8> %a 81} 82 83; CHECK-LABEL: max_u_v16i8: 84; NO-SIMD128-NOT: i8x16 85; SIMD128-NEXT: .functype max_u_v16i8 (v128, v128) -> (v128){{$}} 86; SIMD128-NEXT: i8x16.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 87; SIMD128-NEXT: return $pop[[R]]{{$}} 88define <16 x i8> @max_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 89 %c = icmp ugt <16 x i8> %x, %y 90 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 91 ret <16 x i8> %a 92} 93 94; CHECK-LABEL: avgr_u_v16i8: 95; NO-SIMD128-NOT: i8x16 96; SIMD128-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}} 97; SIMD128-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 98; SIMD128-NEXT: return $pop[[R]]{{$}} 99define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 100 %a = add nuw <16 x i8> %x, %y 101 %b = add nuw <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, 102 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 103 %c = udiv <16 x i8> %b, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, 104 i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 105 ret <16 x i8> %c 106} 107 108; CHECK-LABEL: avgr_u_v16i8_wrap: 109; NO-SIMD128-NOT: i8x16 110; SIMD128-NEXT: .functype avgr_u_v16i8_wrap (v128, v128) -> (v128){{$}} 111; SIMD128-NOT: i8x16.avgr_u 112define <16 x i8> @avgr_u_v16i8_wrap(<16 x i8> %x, <16 x i8> %y) { 113 %a = add <16 x i8> %x, %y 114 %b = add <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, 115 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 116 %c = udiv <16 x i8> %b, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, 117 i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 118 ret <16 x i8> %c 119} 120 121; CHECK-LABEL: neg_v16i8: 122; NO-SIMD128-NOT: i8x16 123; SIMD128-NEXT: .functype neg_v16i8 (v128) -> (v128){{$}} 124; SIMD128-NEXT: i8x16.neg $push[[R:[0-9]+]]=, $0{{$}} 125; SIMD128-NEXT: return $pop[[R]]{{$}} 126define <16 x i8> @neg_v16i8(<16 x i8> %x) { 127 %a = sub <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, 128 i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, 129 %x 130 ret <16 x i8> %a 131} 132 133; CHECK-LABEL: shl_v16i8: 134; NO-SIMD128-NOT: i8x16 135; SIMD128-NEXT: .functype shl_v16i8 (v128, i32) -> (v128){{$}} 136; SIMD128-NEXT: i8x16.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 137; SIMD128-NEXT: return $pop[[R]]{{$}} 138define <16 x i8> @shl_v16i8(<16 x i8> %v, i8 %x) { 139 %t = insertelement <16 x i8> undef, i8 %x, i32 0 140 %s = shufflevector <16 x i8> %t, <16 x i8> undef, 141 <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, 142 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 143 %a = shl <16 x i8> %v, %s 144 ret <16 x i8> %a 145} 146 147; CHECK-LABEL: shl_const_v16i8: 148; NO-SIMD128-NOT: i8x16 149; SIMD128-NEXT: .functype shl_const_v16i8 (v128) -> (v128){{$}} 150; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5 151; SIMD128-NEXT: i8x16.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 152; SIMD128-NEXT: return $pop[[R]]{{$}} 153define <16 x i8> @shl_const_v16i8(<16 x i8> %v) { 154 %a = shl <16 x i8> %v, 155 <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, 156 i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> 157 ret <16 x i8> %a 158} 159 160; CHECK-LABEL: shl_vec_v16i8: 161; NO-SIMD128-NOT: i8x16 162; SIMD128-NEXT: .functype shl_vec_v16i8 (v128, v128) -> (v128){{$}} 163; SIMD128-NEXT: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}} 164; SIMD128-NEXT: i8x16.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 165; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}} 166; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 167; SIMD128-NEXT: i32.shl $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]] 168; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]] 169; Skip 14 lanes 170; SIMD128: i8x16.extract_lane_s $push[[L4:[0-9]+]]=, $0, 15{{$}} 171; SIMD128-NEXT: i8x16.extract_lane_s $push[[L5:[0-9]+]]=, $1, 15{{$}} 172; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}} 173; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 174; SIMD128-NEXT: i32.shl $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 175; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}} 176; SIMD128-NEXT: return $pop[[R]]{{$}} 177define <16 x i8> @shl_vec_v16i8(<16 x i8> %v, <16 x i8> %x) { 178 %a = shl <16 x i8> %v, %x 179 ret <16 x i8> %a 180} 181 182; CHECK-LABEL: shr_s_v16i8: 183; NO-SIMD128-NOT: i8x16 184; SIMD128-NEXT: .functype shr_s_v16i8 (v128, i32) -> (v128){{$}} 185; SIMD128-NEXT: i8x16.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 186; SIMD128-NEXT: return $pop[[R]]{{$}} 187define <16 x i8> @shr_s_v16i8(<16 x i8> %v, i8 %x) { 188 %t = insertelement <16 x i8> undef, i8 %x, i32 0 189 %s = shufflevector <16 x i8> %t, <16 x i8> undef, 190 <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, 191 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 192 %a = ashr <16 x i8> %v, %s 193 ret <16 x i8> %a 194} 195 196; CHECK-LABEL: shr_s_vec_v16i8: 197; NO-SIMD128-NOT: i8x16 198; SIMD128-NEXT: .functype shr_s_vec_v16i8 (v128, v128) -> (v128){{$}} 199; SIMD128-NEXT: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}} 200; SIMD128-NEXT: i8x16.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 201; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}} 202; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 203; SIMD128-NEXT: i32.shr_s $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]] 204; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]] 205; Skip 14 lanes 206; SIMD128: i8x16.extract_lane_s $push[[L4:[0-9]+]]=, $0, 15{{$}} 207; SIMD128-NEXT: i8x16.extract_lane_s $push[[L5:[0-9]+]]=, $1, 15{{$}} 208; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}} 209; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 210; SIMD128-NEXT: i32.shr_s $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 211; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}} 212; SIMD128-NEXT: return $pop[[R]]{{$}} 213define <16 x i8> @shr_s_vec_v16i8(<16 x i8> %v, <16 x i8> %x) { 214 %a = ashr <16 x i8> %v, %x 215 ret <16 x i8> %a 216} 217 218; CHECK-LABEL: shr_u_v16i8: 219; NO-SIMD128-NOT: i8x16 220; SIMD128-NEXT: .functype shr_u_v16i8 (v128, i32) -> (v128){{$}} 221; SIMD128-NEXT: i8x16.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 222; SIMD128-NEXT: return $pop[[R]]{{$}} 223define <16 x i8> @shr_u_v16i8(<16 x i8> %v, i8 %x) { 224 %t = insertelement <16 x i8> undef, i8 %x, i32 0 225 %s = shufflevector <16 x i8> %t, <16 x i8> undef, 226 <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, 227 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 228 %a = lshr <16 x i8> %v, %s 229 ret <16 x i8> %a 230} 231 232; CHECK-LABEL: shr_u_vec_v16i8: 233; NO-SIMD128-NOT: i8x16 234; SIMD128-NEXT: .functype shr_u_vec_v16i8 (v128, v128) -> (v128){{$}} 235; SIMD128-NEXT: i8x16.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}} 236; SIMD128-NEXT: i8x16.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 237; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}} 238; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 239; SIMD128-NEXT: i32.shr_u $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]] 240; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]] 241; Skip 14 lanes 242; SIMD128: i8x16.extract_lane_u $push[[L4:[0-9]+]]=, $0, 15{{$}} 243; SIMD128-NEXT: i8x16.extract_lane_s $push[[L5:[0-9]+]]=, $1, 15{{$}} 244; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}} 245; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 246; SIMD128-NEXT: i32.shr_u $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 247; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}} 248; SIMD128-NEXT: return $pop[[R]]{{$}} 249define <16 x i8> @shr_u_vec_v16i8(<16 x i8> %v, <16 x i8> %x) { 250 %a = lshr <16 x i8> %v, %x 251 ret <16 x i8> %a 252} 253 254; CHECK-LABEL: and_v16i8: 255; NO-SIMD128-NOT: v128 256; SIMD128-NEXT: .functype and_v16i8 (v128, v128) -> (v128){{$}} 257; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 258; SIMD128-NEXT: return $pop[[R]]{{$}} 259define <16 x i8> @and_v16i8(<16 x i8> %x, <16 x i8> %y) { 260 %a = and <16 x i8> %x, %y 261 ret <16 x i8> %a 262} 263 264; CHECK-LABEL: or_v16i8: 265; NO-SIMD128-NOT: v128 266; SIMD128-NEXT: .functype or_v16i8 (v128, v128) -> (v128){{$}} 267; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 268; SIMD128-NEXT: return $pop[[R]]{{$}} 269define <16 x i8> @or_v16i8(<16 x i8> %x, <16 x i8> %y) { 270 %a = or <16 x i8> %x, %y 271 ret <16 x i8> %a 272} 273 274; CHECK-LABEL: xor_v16i8: 275; NO-SIMD128-NOT: v128 276; SIMD128-NEXT: .functype xor_v16i8 (v128, v128) -> (v128){{$}} 277; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 278; SIMD128-NEXT: return $pop[[R]]{{$}} 279define <16 x i8> @xor_v16i8(<16 x i8> %x, <16 x i8> %y) { 280 %a = xor <16 x i8> %x, %y 281 ret <16 x i8> %a 282} 283 284; CHECK-LABEL: not_v16i8: 285; NO-SIMD128-NOT: v128 286; SIMD128-NEXT: .functype not_v16i8 (v128) -> (v128){{$}} 287; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 288; SIMD128-NEXT: return $pop[[R]]{{$}} 289define <16 x i8> @not_v16i8(<16 x i8> %x) { 290 %a = xor <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, 291 i8 -1, i8 -1, i8 -1, i8 -1, 292 i8 -1, i8 -1, i8 -1, i8 -1, 293 i8 -1, i8 -1, i8 -1, i8 -1> 294 ret <16 x i8> %a 295} 296 297; CHECK-LABEL: andnot_v16i8: 298; NO-SIMD128-NOT: v128 299; SIMD128-VM-NOT: v128.andnot 300; SIMD128-NEXT: .functype andnot_v16i8 (v128, v128) -> (v128){{$}} 301; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 302; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 303; SIMD128-FAST-NEXT: v128.not 304; SIMD128-FAST-NEXT: v128.and 305; SIMD128-FAST-NEXT: return 306define <16 x i8> @andnot_v16i8(<16 x i8> %x, <16 x i8> %y) { 307 %inv_y = xor <16 x i8> %y, 308 <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 309 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 310 %a = and <16 x i8> %x, %inv_y 311 ret <16 x i8> %a 312} 313 314; CHECK-LABEL: bitselect_v16i8: 315; NO-SIMD128-NOT: v128 316; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}} 317; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 318; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 319; SIMD128-FAST-NEXT: v128.and 320; SIMD128-FAST-NEXT: v128.not 321; SIMD128-FAST-NEXT: v128.and 322; SIMD128-FAST-NEXT: v128.or 323; SIMD128-FAST-NEXT: return 324define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) { 325 %masked_v1 = and <16 x i8> %c, %v1 326 %inv_mask = xor <16 x i8> %c, 327 <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 328 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 329 %masked_v2 = and <16 x i8> %inv_mask, %v2 330 %a = or <16 x i8> %masked_v1, %masked_v2 331 ret <16 x i8> %a 332} 333 334; ============================================================================== 335; 8 x i16 336; ============================================================================== 337; CHECK-LABEL: add_v8i16: 338; NO-SIMD128-NOT: i16x8 339; SIMD128-NEXT: .functype add_v8i16 (v128, v128) -> (v128){{$}} 340; SIMD128-NEXT: i16x8.add $push[[R:[0-9]+]]=, $0, $1{{$}} 341; SIMD128-NEXT: return $pop[[R]]{{$}} 342define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) { 343 %a = add <8 x i16> %x, %y 344 ret <8 x i16> %a 345} 346 347; CHECK-LABEL: sub_v8i16: 348; NO-SIMD128-NOT: i16x8 349; SIMD128-NEXT: .functype sub_v8i16 (v128, v128) -> (v128){{$}} 350; SIMD128-NEXT: i16x8.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 351; SIMD128-NEXT: return $pop[[R]]{{$}} 352define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) { 353 %a = sub <8 x i16> %x, %y 354 ret <8 x i16> %a 355} 356 357; CHECK-LABEL: mul_v8i16: 358; NO-SIMD128-NOT: i16x8 359; SIMD128-NEXT: .functype mul_v8i16 (v128, v128) -> (v128){{$}} 360; SIMD128-NEXT: i16x8.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 361; SIMD128-NEXT: return $pop[[R]]{{$}} 362define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) { 363 %a = mul <8 x i16> %x, %y 364 ret <8 x i16> %a 365} 366 367; CHECK-LABEL: min_s_v8i16: 368; NO-SIMD128-NOT: i16x8 369; SIMD128-NEXT: .functype min_s_v8i16 (v128, v128) -> (v128){{$}} 370; SIMD128-NEXT: i16x8.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 371; SIMD128-NEXT: return $pop[[R]]{{$}} 372define <8 x i16> @min_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 373 %c = icmp slt <8 x i16> %x, %y 374 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 375 ret <8 x i16> %a 376} 377 378; CHECK-LABEL: min_u_v8i16: 379; NO-SIMD128-NOT: i16x8 380; SIMD128-NEXT: .functype min_u_v8i16 (v128, v128) -> (v128){{$}} 381; SIMD128-NEXT: i16x8.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 382; SIMD128-NEXT: return $pop[[R]]{{$}} 383define <8 x i16> @min_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 384 %c = icmp ult <8 x i16> %x, %y 385 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 386 ret <8 x i16> %a 387} 388 389; CHECK-LABEL: max_s_v8i16: 390; NO-SIMD128-NOT: i16x8 391; SIMD128-NEXT: .functype max_s_v8i16 (v128, v128) -> (v128){{$}} 392; SIMD128-NEXT: i16x8.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 393; SIMD128-NEXT: return $pop[[R]]{{$}} 394define <8 x i16> @max_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 395 %c = icmp sgt <8 x i16> %x, %y 396 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 397 ret <8 x i16> %a 398} 399 400; CHECK-LABEL: max_u_v8i16: 401; NO-SIMD128-NOT: i16x8 402; SIMD128-NEXT: .functype max_u_v8i16 (v128, v128) -> (v128){{$}} 403; SIMD128-NEXT: i16x8.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 404; SIMD128-NEXT: return $pop[[R]]{{$}} 405define <8 x i16> @max_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 406 %c = icmp ugt <8 x i16> %x, %y 407 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 408 ret <8 x i16> %a 409} 410 411; CHECK-LABEL: avgr_u_v8i16: 412; NO-SIMD128-NOT: i16x8 413; SIMD128-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}} 414; SIMD128-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 415; SIMD128-NEXT: return $pop[[R]]{{$}} 416define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 417 %a = add nuw <8 x i16> %x, %y 418 %b = add nuw <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 419 %c = udiv <8 x i16> %b, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> 420 ret <8 x i16> %c 421} 422 423; CHECK-LABEL: avgr_u_v8i16_wrap: 424; NO-SIMD128-NOT: i16x8 425; SIMD128-NEXT: .functype avgr_u_v8i16_wrap (v128, v128) -> (v128){{$}} 426; SIMD128-NOT: i16x8.avgr_u 427define <8 x i16> @avgr_u_v8i16_wrap(<8 x i16> %x, <8 x i16> %y) { 428 %a = add <8 x i16> %x, %y 429 %b = add <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 430 %c = udiv <8 x i16> %b, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> 431 ret <8 x i16> %c 432} 433 434; CHECK-LABEL: neg_v8i16: 435; NO-SIMD128-NOT: i16x8 436; SIMD128-NEXT: .functype neg_v8i16 (v128) -> (v128){{$}} 437; SIMD128-NEXT: i16x8.neg $push[[R:[0-9]+]]=, $0{{$}} 438; SIMD128-NEXT: return $pop[[R]]{{$}} 439define <8 x i16> @neg_v8i16(<8 x i16> %x) { 440 %a = sub <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, 441 %x 442 ret <8 x i16> %a 443} 444 445; CHECK-LABEL: shl_v8i16: 446; NO-SIMD128-NOT: i16x8 447; SIMD128-NEXT: .functype shl_v8i16 (v128, i32) -> (v128){{$}} 448; SIMD128-NEXT: i16x8.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 449; SIMD128-NEXT: return $pop[[R]]{{$}} 450define <8 x i16> @shl_v8i16(<8 x i16> %v, i16 %x) { 451 %t = insertelement <8 x i16> undef, i16 %x, i32 0 452 %s = shufflevector <8 x i16> %t, <8 x i16> undef, 453 <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 454 %a = shl <8 x i16> %v, %s 455 ret <8 x i16> %a 456} 457 458; CHECK-LABEL: shl_const_v8i16: 459; NO-SIMD128-NOT: i16x8 460; SIMD128-NEXT: .functype shl_const_v8i16 (v128) -> (v128){{$}} 461; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5 462; SIMD128-NEXT: i16x8.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 463; SIMD128-NEXT: return $pop[[R]]{{$}} 464define <8 x i16> @shl_const_v8i16(<8 x i16> %v) { 465 %a = shl <8 x i16> %v, 466 <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> 467 ret <8 x i16> %a 468} 469 470; CHECK-LABEL: shl_vec_v8i16: 471; NO-SIMD128-NOT: i16x8 472; SIMD128-NEXT: .functype shl_vec_v8i16 (v128, v128) -> (v128){{$}} 473; SIMD128-NEXT: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}} 474; SIMD128-NEXT: i16x8.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 475; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}} 476; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 477; SIMD128-NEXT: i32.shl $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}} 478; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}} 479; Skip 6 lanes 480; SIMD128: i16x8.extract_lane_s $push[[L4:[0-9]+]]=, $0, 7{{$}} 481; SIMD128-NEXT: i16x8.extract_lane_s $push[[L5:[0-9]+]]=, $1, 7{{$}} 482; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}} 483; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 484; SIMD128-NEXT: i32.shl $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 485; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}} 486; SIMD128-NEXT: return $pop[[R]]{{$}} 487define <8 x i16> @shl_vec_v8i16(<8 x i16> %v, <8 x i16> %x) { 488 %a = shl <8 x i16> %v, %x 489 ret <8 x i16> %a 490} 491 492; CHECK-LABEL: shr_s_v8i16: 493; NO-SIMD128-NOT: i16x8 494; SIMD128-NEXT: .functype shr_s_v8i16 (v128, i32) -> (v128){{$}} 495; SIMD128-NEXT: i16x8.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 496; SIMD128-NEXT: return $pop[[R]]{{$}} 497define <8 x i16> @shr_s_v8i16(<8 x i16> %v, i16 %x) { 498 %t = insertelement <8 x i16> undef, i16 %x, i32 0 499 %s = shufflevector <8 x i16> %t, <8 x i16> undef, 500 <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 501 %a = ashr <8 x i16> %v, %s 502 ret <8 x i16> %a 503} 504 505; CHECK-LABEL: shr_s_vec_v8i16: 506; NO-SIMD128-NOT: i16x8 507; SIMD128-NEXT: .functype shr_s_vec_v8i16 (v128, v128) -> (v128){{$}} 508; SIMD128-NEXT: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}} 509; SIMD128-NEXT: i16x8.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 510; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}} 511; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 512; SIMD128-NEXT: i32.shr_s $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}} 513; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}} 514; Skip 6 lanes 515; SIMD128: i16x8.extract_lane_s $push[[L4:[0-9]+]]=, $0, 7{{$}} 516; SIMD128-NEXT: i16x8.extract_lane_s $push[[L5:[0-9]+]]=, $1, 7{{$}} 517; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}} 518; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 519; SIMD128-NEXT: i32.shr_s $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 520; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}} 521; SIMD128-NEXT: return $pop[[R]]{{$}} 522define <8 x i16> @shr_s_vec_v8i16(<8 x i16> %v, <8 x i16> %x) { 523 %a = ashr <8 x i16> %v, %x 524 ret <8 x i16> %a 525} 526 527; CHECK-LABEL: shr_u_v8i16: 528; NO-SIMD128-NOT: i16x8 529; SIMD128-NEXT: .functype shr_u_v8i16 (v128, i32) -> (v128){{$}} 530; SIMD128-NEXT: i16x8.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 531; SIMD128-NEXT: return $pop[[R]]{{$}} 532define <8 x i16> @shr_u_v8i16(<8 x i16> %v, i16 %x) { 533 %t = insertelement <8 x i16> undef, i16 %x, i32 0 534 %s = shufflevector <8 x i16> %t, <8 x i16> undef, 535 <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 536 %a = lshr <8 x i16> %v, %s 537 ret <8 x i16> %a 538} 539 540; CHECK-LABEL: shr_u_vec_v8i16: 541; NO-SIMD128-NOT: i16x8 542; SIMD128-NEXT: .functype shr_u_vec_v8i16 (v128, v128) -> (v128){{$}} 543; SIMD128-NEXT: i16x8.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}} 544; SIMD128-NEXT: i16x8.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 545; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}} 546; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 547; SIMD128-NEXT: i32.shr_u $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}} 548; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}} 549; Skip 6 lanes 550; SIMD128: i16x8.extract_lane_u $push[[L4:[0-9]+]]=, $0, 7{{$}} 551; SIMD128-NEXT: i16x8.extract_lane_s $push[[L5:[0-9]+]]=, $1, 7{{$}} 552; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}} 553; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 554; SIMD128-NEXT: i32.shr_u $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 555; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}} 556; SIMD128-NEXT: return $pop[[R]]{{$}} 557define <8 x i16> @shr_u_vec_v8i16(<8 x i16> %v, <8 x i16> %x) { 558 %a = lshr <8 x i16> %v, %x 559 ret <8 x i16> %a 560} 561 562; CHECK-LABEL: and_v8i16: 563; NO-SIMD128-NOT: v128 564; SIMD128-NEXT: .functype and_v8i16 (v128, v128) -> (v128){{$}} 565; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 566; SIMD128-NEXT: return $pop[[R]]{{$}} 567define <8 x i16> @and_v8i16(<8 x i16> %x, <8 x i16> %y) { 568 %a = and <8 x i16> %x, %y 569 ret <8 x i16> %a 570} 571 572; CHECK-LABEL: or_v8i16: 573; NO-SIMD128-NOT: v128 574; SIMD128-NEXT: .functype or_v8i16 (v128, v128) -> (v128){{$}} 575; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 576; SIMD128-NEXT: return $pop[[R]]{{$}} 577define <8 x i16> @or_v8i16(<8 x i16> %x, <8 x i16> %y) { 578 %a = or <8 x i16> %x, %y 579 ret <8 x i16> %a 580} 581 582; CHECK-LABEL: xor_v8i16: 583; NO-SIMD128-NOT: v128 584; SIMD128-NEXT: .functype xor_v8i16 (v128, v128) -> (v128){{$}} 585; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 586; SIMD128-NEXT: return $pop[[R]]{{$}} 587define <8 x i16> @xor_v8i16(<8 x i16> %x, <8 x i16> %y) { 588 %a = xor <8 x i16> %x, %y 589 ret <8 x i16> %a 590} 591 592; CHECK-LABEL: not_v8i16: 593; NO-SIMD128-NOT: v128 594; SIMD128-NEXT: .functype not_v8i16 (v128) -> (v128){{$}} 595; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 596; SIMD128-NEXT: return $pop[[R]]{{$}} 597define <8 x i16> @not_v8i16(<8 x i16> %x) { 598 %a = xor <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, 599 i16 -1, i16 -1, i16 -1, i16 -1> 600 ret <8 x i16> %a 601} 602 603; CHECK-LABEL: andnot_v8i16: 604; SIMD128-VM-NOT: v128.andnot 605; NO-SIMD128-NOT: v128 606; SIMD128-NEXT: .functype andnot_v8i16 (v128, v128) -> (v128){{$}} 607; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 608; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 609; SIMD128-FAST-NEXT: v128.not 610; SIMD128-FAST-NEXT: v128.and 611; SIMD128-FAST-NEXT: return 612define <8 x i16> @andnot_v8i16(<8 x i16> %x, <8 x i16> %y) { 613 %inv_y = xor <8 x i16> %y, 614 <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 615 %a = and <8 x i16> %x, %inv_y 616 ret <8 x i16> %a 617} 618 619; CHECK-LABEL: bitselect_v8i16: 620; NO-SIMD128-NOT: v128 621; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}} 622; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 623; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 624; SIMD128-FAST-NEXT: v128.and 625; SIMD128-FAST-NEXT: v128.not 626; SIMD128-FAST-NEXT: v128.and 627; SIMD128-FAST-NEXT: v128.or 628; SIMD128-FAST-NEXT: return 629define <8 x i16> @bitselect_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) { 630 %masked_v1 = and <8 x i16> %v1, %c 631 %inv_mask = xor <8 x i16> 632 <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, 633 %c 634 %masked_v2 = and <8 x i16> %v2, %inv_mask 635 %a = or <8 x i16> %masked_v1, %masked_v2 636 ret <8 x i16> %a 637} 638 639; ============================================================================== 640; 4 x i32 641; ============================================================================== 642; CHECK-LABEL: add_v4i32: 643; NO-SIMD128-NOT: i32x4 644; SIMD128-NEXT: .functype add_v4i32 (v128, v128) -> (v128){{$}} 645; SIMD128-NEXT: i32x4.add $push[[R:[0-9]+]]=, $0, $1{{$}} 646; SIMD128-NEXT: return $pop[[R]]{{$}} 647define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) { 648 %a = add <4 x i32> %x, %y 649 ret <4 x i32> %a 650} 651 652; CHECK-LABEL: sub_v4i32: 653; NO-SIMD128-NOT: i32x4 654; SIMD128-NEXT: .functype sub_v4i32 (v128, v128) -> (v128){{$}} 655; SIMD128-NEXT: i32x4.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 656; SIMD128-NEXT: return $pop[[R]]{{$}} 657define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) { 658 %a = sub <4 x i32> %x, %y 659 ret <4 x i32> %a 660} 661 662; CHECK-LABEL: mul_v4i32: 663; NO-SIMD128-NOT: i32x4 664; SIMD128-NEXT: .functype mul_v4i32 (v128, v128) -> (v128){{$}} 665; SIMD128-NEXT: i32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 666; SIMD128-NEXT: return $pop[[R]]{{$}} 667define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) { 668 %a = mul <4 x i32> %x, %y 669 ret <4 x i32> %a 670} 671 672; CHECK-LABEL: min_s_v4i32: 673; NO-SIMD128-NOT: i32x4 674; SIMD128-NEXT: .functype min_s_v4i32 (v128, v128) -> (v128){{$}} 675; SIMD128-NEXT: i32x4.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 676; SIMD128-NEXT: return $pop[[R]]{{$}} 677define <4 x i32> @min_s_v4i32(<4 x i32> %x, <4 x i32> %y) { 678 %c = icmp slt <4 x i32> %x, %y 679 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 680 ret <4 x i32> %a 681} 682 683; CHECK-LABEL: min_u_v4i32: 684; NO-SIMD128-NOT: i32x4 685; SIMD128-NEXT: .functype min_u_v4i32 (v128, v128) -> (v128){{$}} 686; SIMD128-NEXT: i32x4.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 687; SIMD128-NEXT: return $pop[[R]]{{$}} 688define <4 x i32> @min_u_v4i32(<4 x i32> %x, <4 x i32> %y) { 689 %c = icmp ult <4 x i32> %x, %y 690 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 691 ret <4 x i32> %a 692} 693 694; CHECK-LABEL: max_s_v4i32: 695; NO-SIMD128-NOT: i32x4 696; SIMD128-NEXT: .functype max_s_v4i32 (v128, v128) -> (v128){{$}} 697; SIMD128-NEXT: i32x4.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 698; SIMD128-NEXT: return $pop[[R]]{{$}} 699define <4 x i32> @max_s_v4i32(<4 x i32> %x, <4 x i32> %y) { 700 %c = icmp sgt <4 x i32> %x, %y 701 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 702 ret <4 x i32> %a 703} 704 705; CHECK-LABEL: max_u_v4i32: 706; NO-SIMD128-NOT: i32x4 707; SIMD128-NEXT: .functype max_u_v4i32 (v128, v128) -> (v128){{$}} 708; SIMD128-NEXT: i32x4.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 709; SIMD128-NEXT: return $pop[[R]]{{$}} 710define <4 x i32> @max_u_v4i32(<4 x i32> %x, <4 x i32> %y) { 711 %c = icmp ugt <4 x i32> %x, %y 712 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 713 ret <4 x i32> %a 714} 715 716; CHECK-LABEL: neg_v4i32: 717; NO-SIMD128-NOT: i32x4 718; SIMD128-NEXT: .functype neg_v4i32 (v128) -> (v128){{$}} 719; SIMD128-NEXT: i32x4.neg $push[[R:[0-9]+]]=, $0{{$}} 720; SIMD128-NEXT: return $pop[[R]]{{$}} 721define <4 x i32> @neg_v4i32(<4 x i32> %x) { 722 %a = sub <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %x 723 ret <4 x i32> %a 724} 725 726; CHECK-LABEL: shl_v4i32: 727; NO-SIMD128-NOT: i32x4 728; SIMD128-NEXT: .functype shl_v4i32 (v128, i32) -> (v128){{$}} 729; SIMD128-NEXT: i32x4.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 730; SIMD128-NEXT: return $pop[[R]]{{$}} 731define <4 x i32> @shl_v4i32(<4 x i32> %v, i32 %x) { 732 %t = insertelement <4 x i32> undef, i32 %x, i32 0 733 %s = shufflevector <4 x i32> %t, <4 x i32> undef, 734 <4 x i32> <i32 0, i32 0, i32 0, i32 0> 735 %a = shl <4 x i32> %v, %s 736 ret <4 x i32> %a 737} 738 739; CHECK-LABEL: shl_const_v4i32: 740; NO-SIMD128-NOT: i32x4 741; SIMD128-NEXT: .functype shl_const_v4i32 (v128) -> (v128){{$}} 742; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5 743; SIMD128-NEXT: i32x4.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 744; SIMD128-NEXT: return $pop[[R]]{{$}} 745define <4 x i32> @shl_const_v4i32(<4 x i32> %v) { 746 %a = shl <4 x i32> %v, <i32 5, i32 5, i32 5, i32 5> 747 ret <4 x i32> %a 748} 749 750; CHECK-LABEL: shl_vec_v4i32: 751; NO-SIMD128-NOT: i32x4 752; SIMD128-NEXT: .functype shl_vec_v4i32 (v128, v128) -> (v128){{$}} 753; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 754; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 755; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 756; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 757; Skip 2 lanes 758; SIMD128: i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}} 759; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}} 760; SIMD128-NEXT: i32.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 761; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}} 762; SIMD128-NEXT: return $pop[[R]]{{$}} 763define <4 x i32> @shl_vec_v4i32(<4 x i32> %v, <4 x i32> %x) { 764 %a = shl <4 x i32> %v, %x 765 ret <4 x i32> %a 766} 767 768; CHECK-LABEL: shr_s_v4i32: 769; NO-SIMD128-NOT: i32x4 770; SIMD128-NEXT: .functype shr_s_v4i32 (v128, i32) -> (v128){{$}} 771; SIMD128-NEXT: i32x4.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 772; SIMD128-NEXT: return $pop[[R]]{{$}} 773define <4 x i32> @shr_s_v4i32(<4 x i32> %v, i32 %x) { 774 %t = insertelement <4 x i32> undef, i32 %x, i32 0 775 %s = shufflevector <4 x i32> %t, <4 x i32> undef, 776 <4 x i32> <i32 0, i32 0, i32 0, i32 0> 777 %a = ashr <4 x i32> %v, %s 778 ret <4 x i32> %a 779} 780 781; CHECK-LABEL: shr_s_vec_v4i32: 782; NO-SIMD128-NOT: i32x4 783; SIMD128-NEXT: .functype shr_s_vec_v4i32 (v128, v128) -> (v128){{$}} 784; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 785; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 786; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 787; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 788; Skip 2 lanes 789; SIMD128: i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}} 790; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}} 791; SIMD128-NEXT: i32.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 792; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}} 793; SIMD128-NEXT: return $pop[[R]]{{$}} 794define <4 x i32> @shr_s_vec_v4i32(<4 x i32> %v, <4 x i32> %x) { 795 %a = ashr <4 x i32> %v, %x 796 ret <4 x i32> %a 797} 798 799; CHECK-LABEL: shr_u_v4i32: 800; NO-SIMD128-NOT: i32x4 801; SIMD128-NEXT: .functype shr_u_v4i32 (v128, i32) -> (v128){{$}} 802; SIMD128-NEXT: i32x4.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 803; SIMD128-NEXT: return $pop[[R]]{{$}} 804define <4 x i32> @shr_u_v4i32(<4 x i32> %v, i32 %x) { 805 %t = insertelement <4 x i32> undef, i32 %x, i32 0 806 %s = shufflevector <4 x i32> %t, <4 x i32> undef, 807 <4 x i32> <i32 0, i32 0, i32 0, i32 0> 808 %a = lshr <4 x i32> %v, %s 809 ret <4 x i32> %a 810} 811 812; CHECK-LABEL: shr_u_vec_v4i32: 813; NO-SIMD128-NOT: i32x4 814; SIMD128-NEXT: .functype shr_u_vec_v4i32 (v128, v128) -> (v128){{$}} 815; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 816; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 817; SIMD128-NEXT: i32.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 818; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 819; Skip 2 lanes 820; SIMD128: i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}} 821; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}} 822; SIMD128-NEXT: i32.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 823; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}} 824; SIMD128-NEXT: return $pop[[R]]{{$}} 825define <4 x i32> @shr_u_vec_v4i32(<4 x i32> %v, <4 x i32> %x) { 826 %a = lshr <4 x i32> %v, %x 827 ret <4 x i32> %a 828} 829 830; CHECK-LABEL: and_v4i32: 831; NO-SIMD128-NOT: v128 832; SIMD128-NEXT: .functype and_v4i32 (v128, v128) -> (v128){{$}} 833; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 834; SIMD128-NEXT: return $pop[[R]]{{$}} 835define <4 x i32> @and_v4i32(<4 x i32> %x, <4 x i32> %y) { 836 %a = and <4 x i32> %x, %y 837 ret <4 x i32> %a 838} 839 840; CHECK-LABEL: or_v4i32: 841; NO-SIMD128-NOT: v128 842; SIMD128-NEXT: .functype or_v4i32 (v128, v128) -> (v128){{$}} 843; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 844; SIMD128-NEXT: return $pop[[R]]{{$}} 845define <4 x i32> @or_v4i32(<4 x i32> %x, <4 x i32> %y) { 846 %a = or <4 x i32> %x, %y 847 ret <4 x i32> %a 848} 849 850; CHECK-LABEL: xor_v4i32: 851; NO-SIMD128-NOT: v128 852; SIMD128-NEXT: .functype xor_v4i32 (v128, v128) -> (v128){{$}} 853; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 854; SIMD128-NEXT: return $pop[[R]]{{$}} 855define <4 x i32> @xor_v4i32(<4 x i32> %x, <4 x i32> %y) { 856 %a = xor <4 x i32> %x, %y 857 ret <4 x i32> %a 858} 859 860; CHECK-LABEL: not_v4i32: 861; NO-SIMD128-NOT: v128 862; SIMD128-NEXT: .functype not_v4i32 (v128) -> (v128){{$}} 863; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 864; SIMD128-NEXT: return $pop[[R]]{{$}} 865define <4 x i32> @not_v4i32(<4 x i32> %x) { 866 %a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 867 ret <4 x i32> %a 868} 869 870; CHECK-LABEL: andnot_v4i32: 871; SIMD128-VM-NOT: v128.andnot 872; NO-SIMD128-NOT: v128 873; SIMD128-NEXT: .functype andnot_v4i32 (v128, v128) -> (v128){{$}} 874; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 875; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 876; SIMD128-FAST-NEXT: v128.not 877; SIMD128-FAST-NEXT: v128.and 878; SIMD128-FAST-NEXT: return 879define <4 x i32> @andnot_v4i32(<4 x i32> %x, <4 x i32> %y) { 880 %inv_y = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1> 881 %a = and <4 x i32> %x, %inv_y 882 ret <4 x i32> %a 883} 884 885; CHECK-LABEL: bitselect_v4i32: 886; NO-SIMD128-NOT: v128 887; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}} 888; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 889; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 890; SIMD128-FAST-NEXT: v128.not 891; SIMD128-FAST-NEXT: v128.and 892; SIMD128-FAST-NEXT: v128.and 893; SIMD128-FAST-NEXT: v128.or 894; SIMD128-FAST-NEXT: return 895define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) { 896 %masked_v1 = and <4 x i32> %c, %v1 897 %inv_mask = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %c 898 %masked_v2 = and <4 x i32> %inv_mask, %v2 899 %a = or <4 x i32> %masked_v2, %masked_v1 900 ret <4 x i32> %a 901} 902 903; ============================================================================== 904; 2 x i64 905; ============================================================================== 906; CHECK-LABEL: add_v2i64: 907; NO-SIMD128-NOT: i64x2 908; SIMD128-VM-NOT: i64x2 909; SIMD128-NEXT: .functype add_v2i64 (v128, v128) -> (v128){{$}} 910; SIMD128-NEXT: i64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}} 911; SIMD128-NEXT: return $pop[[R]]{{$}} 912define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) { 913 %a = add <2 x i64> %x, %y 914 ret <2 x i64> %a 915} 916 917; CHECK-LABEL: sub_v2i64: 918; NO-SIMD128-NOT: i64x2 919; SIMD128-VM-NOT: i64x2 920; SIMD128-NEXT: .functype sub_v2i64 (v128, v128) -> (v128){{$}} 921; SIMD128-NEXT: i64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 922; SIMD128-NEXT: return $pop[[R]]{{$}} 923define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) { 924 %a = sub <2 x i64> %x, %y 925 ret <2 x i64> %a 926} 927 928; v2i64.mul is not in spec 929; CHECK-LABEL: mul_v2i64: 930; NO-SIMD128-NOT: i64x2 931; SIMD128-VM-NOT: i64x2 932; SIMD128-NOT: i64x2.mul 933; SIMD128: i64x2.extract_lane 934; SIMD128: i64.mul 935define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) { 936 %a = mul <2 x i64> %x, %y 937 ret <2 x i64> %a 938} 939 940; CHECK-LABEL: neg_v2i64: 941; NO-SIMD128-NOT: i64x2 942; SIMD128-NEXT: .functype neg_v2i64 (v128) -> (v128){{$}} 943; SIMD128-NEXT: i64x2.neg $push[[R:[0-9]+]]=, $0{{$}} 944; SIMD128-NEXT: return $pop[[R]]{{$}} 945define <2 x i64> @neg_v2i64(<2 x i64> %x) { 946 %a = sub <2 x i64> <i64 0, i64 0>, %x 947 ret <2 x i64> %a 948} 949 950; CHECK-LABEL: shl_v2i64: 951; NO-SIMD128-NOT: i64x2 952; SIMD128-NEXT: .functype shl_v2i64 (v128, i32) -> (v128){{$}} 953; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 954; SIMD128-NEXT: return $pop[[R]]{{$}} 955define <2 x i64> @shl_v2i64(<2 x i64> %v, i32 %x) { 956 %x2 = zext i32 %x to i64 957 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 958 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 959 %a = shl <2 x i64> %v, %s 960 ret <2 x i64> %a 961} 962 963; CHECK-LABEL: shl_sext_v2i64: 964; NO-SIMD128-NOT: i64x2 965; SIMD128-NEXT: .functype shl_sext_v2i64 (v128, i32) -> (v128){{$}} 966; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 967; SIMD128-NEXT: return $pop[[R]]{{$}} 968define <2 x i64> @shl_sext_v2i64(<2 x i64> %v, i32 %x) { 969 %x2 = sext i32 %x to i64 970 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 971 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 972 %a = shl <2 x i64> %v, %s 973 ret <2 x i64> %a 974} 975 976; CHECK-LABEL: shl_noext_v2i64: 977; NO-SIMD128-NOT: i64x2 978; SIMD128-NEXT: .functype shl_noext_v2i64 (v128, i64) -> (v128){{$}} 979; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}} 980; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 981; SIMD128-NEXT: return $pop[[R]]{{$}} 982define <2 x i64> @shl_noext_v2i64(<2 x i64> %v, i64 %x) { 983 %t = insertelement <2 x i64> undef, i64 %x, i32 0 984 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 985 %a = shl <2 x i64> %v, %s 986 ret <2 x i64> %a 987} 988 989; CHECK-LABEL: shl_const_v2i64: 990; NO-SIMD128-NOT: i64x2 991; SIMD128-NEXT: .functype shl_const_v2i64 (v128) -> (v128){{$}} 992; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}} 993; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 994; SIMD128-NEXT: return $pop[[R]]{{$}} 995define <2 x i64> @shl_const_v2i64(<2 x i64> %v) { 996 %a = shl <2 x i64> %v, <i64 5, i64 5> 997 ret <2 x i64> %a 998} 999 1000; CHECK-LABEL: shl_vec_v2i64: 1001; NO-SIMD128-NOT: i64x2 1002; SIMD128-NEXT: .functype shl_vec_v2i64 (v128, v128) -> (v128){{$}} 1003; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 1004; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 1005; SIMD128-NEXT: i64.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 1006; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 1007; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}} 1008; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}} 1009; SIMD128-NEXT: i64.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 1010; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}} 1011; SIMD128-NEXT: return $pop[[R]]{{$}} 1012define <2 x i64> @shl_vec_v2i64(<2 x i64> %v, <2 x i64> %x) { 1013 %a = shl <2 x i64> %v, %x 1014 ret <2 x i64> %a 1015} 1016 1017; CHECK-LABEL: shr_s_v2i64: 1018; NO-SIMD128-NOT: i64x2 1019; SIMD128-NEXT: .functype shr_s_v2i64 (v128, i32) -> (v128){{$}} 1020; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 1021; SIMD128-NEXT: return $pop[[R]]{{$}} 1022define <2 x i64> @shr_s_v2i64(<2 x i64> %v, i32 %x) { 1023 %x2 = zext i32 %x to i64 1024 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1025 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1026 %a = ashr <2 x i64> %v, %s 1027 ret <2 x i64> %a 1028} 1029 1030; CHECK-LABEL: shr_s_sext_v2i64: 1031; NO-SIMD128-NOT: i64x2 1032; SIMD128-NEXT: .functype shr_s_sext_v2i64 (v128, i32) -> (v128){{$}} 1033; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 1034; SIMD128-NEXT: return $pop[[R]]{{$}} 1035define <2 x i64> @shr_s_sext_v2i64(<2 x i64> %v, i32 %x) { 1036 %x2 = sext i32 %x to i64 1037 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1038 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1039 %a = ashr <2 x i64> %v, %s 1040 ret <2 x i64> %a 1041} 1042 1043; CHECK-LABEL: shr_s_noext_v2i64: 1044; NO-SIMD128-NOT: i64x2 1045; SIMD128-NEXT: .functype shr_s_noext_v2i64 (v128, i64) -> (v128){{$}} 1046; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}} 1047; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1048; SIMD128-NEXT: return $pop[[R]]{{$}} 1049define <2 x i64> @shr_s_noext_v2i64(<2 x i64> %v, i64 %x) { 1050 %t = insertelement <2 x i64> undef, i64 %x, i32 0 1051 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1052 %a = ashr <2 x i64> %v, %s 1053 ret <2 x i64> %a 1054} 1055 1056; CHECK-LABEL: shr_s_const_v2i64: 1057; NO-SIMD128-NOT: i64x2 1058; SIMD128-NEXT: .functype shr_s_const_v2i64 (v128) -> (v128){{$}} 1059; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}} 1060; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1061; SIMD128-NEXT: return $pop[[R]]{{$}} 1062define <2 x i64> @shr_s_const_v2i64(<2 x i64> %v) { 1063 %a = ashr <2 x i64> %v, <i64 5, i64 5> 1064 ret <2 x i64> %a 1065} 1066 1067; CHECK-LABEL: shr_s_vec_v2i64: 1068; NO-SIMD128-NOT: i64x2 1069; SIMD128-NEXT: .functype shr_s_vec_v2i64 (v128, v128) -> (v128){{$}} 1070; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 1071; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 1072; SIMD128-NEXT: i64.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 1073; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 1074; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}} 1075; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}} 1076; SIMD128-NEXT: i64.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 1077; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}} 1078; SIMD128-NEXT: return $pop[[R]]{{$}} 1079define <2 x i64> @shr_s_vec_v2i64(<2 x i64> %v, <2 x i64> %x) { 1080 %a = ashr <2 x i64> %v, %x 1081 ret <2 x i64> %a 1082} 1083 1084; CHECK-LABEL: shr_u_v2i64: 1085; NO-SIMD128-NOT: i64x2 1086; SIMD128-NEXT: .functype shr_u_v2i64 (v128, i32) -> (v128){{$}} 1087; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 1088; SIMD128-NEXT: return $pop[[R]]{{$}} 1089define <2 x i64> @shr_u_v2i64(<2 x i64> %v, i32 %x) { 1090 %x2 = zext i32 %x to i64 1091 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1092 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1093 %a = lshr <2 x i64> %v, %s 1094 ret <2 x i64> %a 1095} 1096 1097; CHECK-LABEL: shr_u_sext_v2i64: 1098; NO-SIMD128-NOT: i64x2 1099; SIMD128-NEXT: .functype shr_u_sext_v2i64 (v128, i32) -> (v128){{$}} 1100; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 1101; SIMD128-NEXT: return $pop[[R]]{{$}} 1102define <2 x i64> @shr_u_sext_v2i64(<2 x i64> %v, i32 %x) { 1103 %x2 = sext i32 %x to i64 1104 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1105 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1106 %a = lshr <2 x i64> %v, %s 1107 ret <2 x i64> %a 1108} 1109 1110; CHECK-LABEL: shr_u_noext_v2i64: 1111; NO-SIMD128-NOT: i64x2 1112; SIMD128-NEXT: .functype shr_u_noext_v2i64 (v128, i64) -> (v128){{$}} 1113; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}} 1114; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1115; SIMD128-NEXT: return $pop[[R]]{{$}} 1116define <2 x i64> @shr_u_noext_v2i64(<2 x i64> %v, i64 %x) { 1117 %t = insertelement <2 x i64> undef, i64 %x, i32 0 1118 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1119 %a = lshr <2 x i64> %v, %s 1120 ret <2 x i64> %a 1121} 1122 1123; CHECK-LABEL: shr_u_const_v2i64: 1124; NO-SIMD128-NOT: i64x2 1125; SIMD128-NEXT: .functype shr_u_const_v2i64 (v128) -> (v128){{$}} 1126; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}} 1127; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1128; SIMD128-NEXT: return $pop[[R]]{{$}} 1129define <2 x i64> @shr_u_const_v2i64(<2 x i64> %v) { 1130 %a = lshr <2 x i64> %v, <i64 5, i64 5> 1131 ret <2 x i64> %a 1132} 1133 1134; CHECK-LABEL: shr_u_vec_v2i64: 1135; NO-SIMD128-NOT: i64x2 1136; SIMD128-NEXT: .functype shr_u_vec_v2i64 (v128, v128) -> (v128){{$}} 1137; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 1138; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 1139; SIMD128-NEXT: i64.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 1140; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 1141; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}} 1142; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}} 1143; SIMD128-NEXT: i64.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 1144; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}} 1145; SIMD128-NEXT: return $pop[[R]]{{$}} 1146define <2 x i64> @shr_u_vec_v2i64(<2 x i64> %v, <2 x i64> %x) { 1147 %a = lshr <2 x i64> %v, %x 1148 ret <2 x i64> %a 1149} 1150 1151; CHECK-LABEL: and_v2i64: 1152; NO-SIMD128-NOT: v128 1153; SIMD128-VM-NOT: v128 1154; SIMD128-NEXT: .functype and_v2i64 (v128, v128) -> (v128){{$}} 1155; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 1156; SIMD128-NEXT: return $pop[[R]]{{$}} 1157define <2 x i64> @and_v2i64(<2 x i64> %x, <2 x i64> %y) { 1158 %a = and <2 x i64> %x, %y 1159 ret <2 x i64> %a 1160} 1161 1162; CHECK-LABEL: or_v2i64: 1163; NO-SIMD128-NOT: v128 1164; SIMD128-VM-NOT: v128 1165; SIMD128-NEXT: .functype or_v2i64 (v128, v128) -> (v128){{$}} 1166; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 1167; SIMD128-NEXT: return $pop[[R]]{{$}} 1168define <2 x i64> @or_v2i64(<2 x i64> %x, <2 x i64> %y) { 1169 %a = or <2 x i64> %x, %y 1170 ret <2 x i64> %a 1171} 1172 1173; CHECK-LABEL: xor_v2i64: 1174; NO-SIMD128-NOT: v128 1175; SIMD128-VM-NOT: v128 1176; SIMD128-NEXT: .functype xor_v2i64 (v128, v128) -> (v128){{$}} 1177; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 1178; SIMD128-NEXT: return $pop[[R]]{{$}} 1179define <2 x i64> @xor_v2i64(<2 x i64> %x, <2 x i64> %y) { 1180 %a = xor <2 x i64> %x, %y 1181 ret <2 x i64> %a 1182} 1183 1184; CHECK-LABEL: not_v2i64: 1185; NO-SIMD128-NOT: v128 1186; SIMD128-VM-NOT: v128 1187; SIMD128-NEXT: .functype not_v2i64 (v128) -> (v128){{$}} 1188; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 1189; SIMD128-NEXT: return $pop[[R]]{{$}} 1190define <2 x i64> @not_v2i64(<2 x i64> %x) { 1191 %a = xor <2 x i64> %x, <i64 -1, i64 -1> 1192 ret <2 x i64> %a 1193} 1194 1195; CHECK-LABEL: andnot_v2i64: 1196; SIMD128-VM-NOT: v128.andnot 1197; NO-SIMD128-NOT: v128 1198; SIMD128-NEXT: .functype andnot_v2i64 (v128, v128) -> (v128){{$}} 1199; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 1200; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1201; SIMD128-FAST-NEXT: v128.not 1202; SIMD128-FAST-NEXT: v128.and 1203; SIMD128-FAST-NEXT: return 1204define <2 x i64> @andnot_v2i64(<2 x i64> %x, <2 x i64> %y) { 1205 %inv_y = xor <2 x i64> %y, <i64 -1, i64 -1> 1206 %a = and <2 x i64> %x, %inv_y 1207 ret <2 x i64> %a 1208} 1209 1210; CHECK-LABEL: bitselect_v2i64: 1211; NO-SIMD128-NOT: v128 1212; SIMD128-VM-NOT: v128 1213; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}} 1214; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 1215; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1216; SIMD128-FAST-NEXT: v128.not 1217; SIMD128-FAST-NEXT: v128.and 1218; SIMD128-FAST-NEXT: v128.and 1219; SIMD128-FAST-NEXT: v128.or 1220; SIMD128-FAST-NEXT: return 1221define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) { 1222 %masked_v1 = and <2 x i64> %v1, %c 1223 %inv_mask = xor <2 x i64> <i64 -1, i64 -1>, %c 1224 %masked_v2 = and <2 x i64> %v2, %inv_mask 1225 %a = or <2 x i64> %masked_v2, %masked_v1 1226 ret <2 x i64> %a 1227} 1228 1229; ============================================================================== 1230; 4 x float 1231; ============================================================================== 1232; CHECK-LABEL: neg_v4f32: 1233; NO-SIMD128-NOT: f32x4 1234; SIMD128-NEXT: .functype neg_v4f32 (v128) -> (v128){{$}} 1235; SIMD128-NEXT: f32x4.neg $push[[R:[0-9]+]]=, $0{{$}} 1236; SIMD128-NEXT: return $pop[[R]]{{$}} 1237define <4 x float> @neg_v4f32(<4 x float> %x) { 1238 ; nsz makes this semantically equivalent to flipping sign bit 1239 %a = fsub nsz <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, %x 1240 ret <4 x float> %a 1241} 1242 1243; CHECK-LABEL: abs_v4f32: 1244; NO-SIMD128-NOT: f32x4 1245; SIMD128-NEXT: .functype abs_v4f32 (v128) -> (v128){{$}} 1246; SIMD128-NEXT: f32x4.abs $push[[R:[0-9]+]]=, $0{{$}} 1247; SIMD128-NEXT: return $pop[[R]]{{$}} 1248declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone 1249define <4 x float> @abs_v4f32(<4 x float> %x) { 1250 %a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x) 1251 ret <4 x float> %a 1252} 1253 1254; CHECK-LABEL: min_unordered_v4f32: 1255; NO-SIMD128-NOT: f32x4 1256; SIMD128-NEXT: .functype min_unordered_v4f32 (v128) -> (v128){{$}} 1257; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 1258; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1259; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1260; SIMD128-NEXT: return $pop[[R]]{{$}} 1261define <4 x float> @min_unordered_v4f32(<4 x float> %x) { 1262 %cmps = fcmp ule <4 x float> %x, <float 5., float 5., float 5., float 5.> 1263 %a = select <4 x i1> %cmps, <4 x float> %x, 1264 <4 x float> <float 5., float 5., float 5., float 5.> 1265 ret <4 x float> %a 1266} 1267 1268; CHECK-LABEL: max_unordered_v4f32: 1269; NO-SIMD128-NOT: f32x4 1270; SIMD128-NEXT: .functype max_unordered_v4f32 (v128) -> (v128){{$}} 1271; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 1272; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1273; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1274; SIMD128-NEXT: return $pop[[R]]{{$}} 1275define <4 x float> @max_unordered_v4f32(<4 x float> %x) { 1276 %cmps = fcmp uge <4 x float> %x, <float 5., float 5., float 5., float 5.> 1277 %a = select <4 x i1> %cmps, <4 x float> %x, 1278 <4 x float> <float 5., float 5., float 5., float 5.> 1279 ret <4 x float> %a 1280} 1281 1282; CHECK-LABEL: min_ordered_v4f32: 1283; NO-SIMD128-NOT: f32x4 1284; SIMD128-NEXT: .functype min_ordered_v4f32 (v128) -> (v128){{$}} 1285; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 1286; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1287; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1288; SIMD128-NEXT: return $pop[[R]]{{$}} 1289define <4 x float> @min_ordered_v4f32(<4 x float> %x) { 1290 %cmps = fcmp ole <4 x float> <float 5., float 5., float 5., float 5.>, %x 1291 %a = select <4 x i1> %cmps, 1292 <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x 1293 ret <4 x float> %a 1294} 1295 1296; CHECK-LABEL: max_ordered_v4f32: 1297; NO-SIMD128-NOT: f32x4 1298; SIMD128-NEXT: .functype max_ordered_v4f32 (v128) -> (v128){{$}} 1299; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 1300; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1301; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1302; SIMD128-NEXT: return $pop[[R]]{{$}} 1303define <4 x float> @max_ordered_v4f32(<4 x float> %x) { 1304 %cmps = fcmp oge <4 x float> <float 5., float 5., float 5., float 5.>, %x 1305 %a = select <4 x i1> %cmps, 1306 <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x 1307 ret <4 x float> %a 1308} 1309 1310; CHECK-LABEL: min_intrinsic_v4f32: 1311; NO-SIMD128-NOT: f32x4 1312; SIMD128-NEXT: .functype min_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1313; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $1{{$}} 1314; SIMD128-NEXT: return $pop[[R]]{{$}} 1315declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>) 1316define <4 x float> @min_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1317 %a = call <4 x float> @llvm.minimum.v4f32(<4 x float> %x, <4 x float> %y) 1318 ret <4 x float> %a 1319} 1320 1321; CHECK-LABEL: minnum_intrinsic_v4f32: 1322; NO-SIMD128-NOT: f32x4 1323; SIMD128-NEXT: .functype minnum_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1324; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $1{{$}} 1325; SIMD128-NEXT: return $pop[[R]]{{$}} 1326declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) 1327define <4 x float> @minnum_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1328 %a = call nnan <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float> %y) 1329 ret <4 x float> %a 1330} 1331 1332; CHECK-LABEL: max_intrinsic_v4f32: 1333; NO-SIMD128-NOT: f32x4 1334; SIMD128-NEXT: .functype max_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1335; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $1{{$}} 1336; SIMD128-NEXT: return $pop[[R]]{{$}} 1337declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>) 1338define <4 x float> @max_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1339 %a = call <4 x float> @llvm.maximum.v4f32(<4 x float> %x, <4 x float> %y) 1340 ret <4 x float> %a 1341} 1342 1343; CHECK-LABEL: maxnum_intrinsic_v4f32: 1344; NO-SIMD128-NOT: f32x4 1345; SIMD128-NEXT: .functype maxnum_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1346; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $1{{$}} 1347; SIMD128-NEXT: return $pop[[R]]{{$}} 1348declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) 1349define <4 x float> @maxnum_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1350 %a = call nnan <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float> %y) 1351 ret <4 x float> %a 1352} 1353 1354; CHECK-LABEL: min_const_intrinsic_v4f32: 1355; NO-SIMD128-NOT: f32x4 1356; SIMD128-NEXT: .functype min_const_intrinsic_v4f32 () -> (v128){{$}} 1357; SIMD128-NEXT: f32.const $push[[L:[0-9]+]]=, 0x1.4p2{{$}} 1358; SIMD128-NEXT: f32x4.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}} 1359; SIMD128-NEXT: return $pop[[R]]{{$}} 1360define <4 x float> @min_const_intrinsic_v4f32() { 1361 %a = call <4 x float> @llvm.minimum.v4f32( 1362 <4 x float> <float 42., float 42., float 42., float 42.>, 1363 <4 x float> <float 5., float 5., float 5., float 5.> 1364 ) 1365 ret <4 x float> %a 1366} 1367 1368; CHECK-LABEL: max_const_intrinsic_v4f32: 1369; NO-SIMD128-NOT: f32x4 1370; SIMD128-NEXT: .functype max_const_intrinsic_v4f32 () -> (v128){{$}} 1371; SIMD128-NEXT: f32.const $push[[L:[0-9]+]]=, 0x1.5p5{{$}} 1372; SIMD128-NEXT: f32x4.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}} 1373; SIMD128-NEXT: return $pop[[R]]{{$}} 1374define <4 x float> @max_const_intrinsic_v4f32() { 1375 %a = call <4 x float> @llvm.maximum.v4f32( 1376 <4 x float> <float 42., float 42., float 42., float 42.>, 1377 <4 x float> <float 5., float 5., float 5., float 5.> 1378 ) 1379 ret <4 x float> %a 1380} 1381 1382; CHECK-LABEL: add_v4f32: 1383; NO-SIMD128-NOT: f32x4 1384; SIMD128-NEXT: .functype add_v4f32 (v128, v128) -> (v128){{$}} 1385; SIMD128-NEXT: f32x4.add $push[[R:[0-9]+]]=, $0, $1{{$}} 1386; SIMD128-NEXT: return $pop[[R]]{{$}} 1387define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) { 1388 %a = fadd <4 x float> %x, %y 1389 ret <4 x float> %a 1390} 1391 1392; CHECK-LABEL: sub_v4f32: 1393; NO-SIMD128-NOT: f32x4 1394; SIMD128-NEXT: .functype sub_v4f32 (v128, v128) -> (v128){{$}} 1395; SIMD128-NEXT: f32x4.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 1396; SIMD128-NEXT: return $pop[[R]]{{$}} 1397define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) { 1398 %a = fsub <4 x float> %x, %y 1399 ret <4 x float> %a 1400} 1401 1402; CHECK-LABEL: div_v4f32: 1403; NO-SIMD128-NOT: f32x4 1404; SIMD128-VM-NOT: f32x4.div 1405; SIMD128-NEXT: .functype div_v4f32 (v128, v128) -> (v128){{$}} 1406; SIMD128-NEXT: f32x4.div $push[[R:[0-9]+]]=, $0, $1{{$}} 1407; SIMD128-NEXT: return $pop[[R]]{{$}} 1408define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) { 1409 %a = fdiv <4 x float> %x, %y 1410 ret <4 x float> %a 1411} 1412 1413; CHECK-LABEL: mul_v4f32: 1414; NO-SIMD128-NOT: f32x4 1415; SIMD128-NEXT: .functype mul_v4f32 (v128, v128) -> (v128){{$}} 1416; SIMD128-NEXT: f32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 1417; SIMD128-NEXT: return $pop[[R]]{{$}} 1418define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) { 1419 %a = fmul <4 x float> %x, %y 1420 ret <4 x float> %a 1421} 1422 1423; CHECK-LABEL: sqrt_v4f32: 1424; NO-SIMD128-NOT: f32x4 1425; SIMD128-VM-NOT: f32x4.sqrt 1426; SIMD128-NEXT: .functype sqrt_v4f32 (v128) -> (v128){{$}} 1427; SIMD128-NEXT: f32x4.sqrt $push[[R:[0-9]+]]=, $0{{$}} 1428; SIMD128-NEXT: return $pop[[R]]{{$}} 1429declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) 1430define <4 x float> @sqrt_v4f32(<4 x float> %x) { 1431 %a = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) 1432 ret <4 x float> %a 1433} 1434 1435; ============================================================================== 1436; 2 x double 1437; ============================================================================== 1438; CHECK-LABEL: neg_v2f64: 1439; NO-SIMD128-NOT: f64x2 1440; SIMD128-NEXT: .functype neg_v2f64 (v128) -> (v128){{$}} 1441; SIMD128-NEXT: f64x2.neg $push[[R:[0-9]+]]=, $0{{$}} 1442; SIMD128-NEXT: return $pop[[R]]{{$}} 1443define <2 x double> @neg_v2f64(<2 x double> %x) { 1444 ; nsz makes this semantically equivalent to flipping sign bit 1445 %a = fsub nsz <2 x double> <double 0., double 0.>, %x 1446 ret <2 x double> %a 1447} 1448 1449; CHECK-LABEL: abs_v2f64: 1450; NO-SIMD128-NOT: f64x2 1451; SIMD128-NEXT: .functype abs_v2f64 (v128) -> (v128){{$}} 1452; SIMD128-NEXT: f64x2.abs $push[[R:[0-9]+]]=, $0{{$}} 1453; SIMD128-NEXT: return $pop[[R]]{{$}} 1454declare <2 x double> @llvm.fabs.v2f64(<2 x double>) nounwind readnone 1455define <2 x double> @abs_v2f64(<2 x double> %x) { 1456 %a = call <2 x double> @llvm.fabs.v2f64(<2 x double> %x) 1457 ret <2 x double> %a 1458} 1459 1460; CHECK-LABEL: min_unordered_v2f64: 1461; NO-SIMD128-NOT: f64x2 1462; SIMD128-NEXT: .functype min_unordered_v2f64 (v128) -> (v128){{$}} 1463; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 1464; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1465; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1466; SIMD128-NEXT: return $pop[[R]]{{$}} 1467define <2 x double> @min_unordered_v2f64(<2 x double> %x) { 1468 %cmps = fcmp ule <2 x double> %x, <double 5., double 5.> 1469 %a = select <2 x i1> %cmps, <2 x double> %x, 1470 <2 x double> <double 5., double 5.> 1471 ret <2 x double> %a 1472} 1473 1474; CHECK-LABEL: max_unordered_v2f64: 1475; NO-SIMD128-NOT: f64x2 1476; SIMD128-NEXT: .functype max_unordered_v2f64 (v128) -> (v128){{$}} 1477; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 1478; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1479; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1480; SIMD128-NEXT: return $pop[[R]]{{$}} 1481define <2 x double> @max_unordered_v2f64(<2 x double> %x) { 1482 %cmps = fcmp uge <2 x double> %x, <double 5., double 5.> 1483 %a = select <2 x i1> %cmps, <2 x double> %x, 1484 <2 x double> <double 5., double 5.> 1485 ret <2 x double> %a 1486} 1487 1488; CHECK-LABEL: min_ordered_v2f64: 1489; NO-SIMD128-NOT: f64x2 1490; SIMD128-NEXT: .functype min_ordered_v2f64 (v128) -> (v128){{$}} 1491; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 1492; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1493; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1494; SIMD128-NEXT: return $pop[[R]]{{$}} 1495define <2 x double> @min_ordered_v2f64(<2 x double> %x) { 1496 %cmps = fcmp ole <2 x double> <double 5., double 5.>, %x 1497 %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>, 1498 <2 x double> %x 1499 ret <2 x double> %a 1500} 1501 1502; CHECK-LABEL: max_ordered_v2f64: 1503; NO-SIMD128-NOT: f64x2 1504; SIMD128-NEXT: .functype max_ordered_v2f64 (v128) -> (v128){{$}} 1505; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 1506; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1507; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1508; SIMD128-NEXT: return $pop[[R]]{{$}} 1509define <2 x double> @max_ordered_v2f64(<2 x double> %x) { 1510 %cmps = fcmp oge <2 x double> <double 5., double 5.>, %x 1511 %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>, 1512 <2 x double> %x 1513 ret <2 x double> %a 1514} 1515 1516; CHECK-LABEL: min_intrinsic_v2f64: 1517; NO-SIMD128-NOT: f64x2 1518; SIMD128-NEXT: .functype min_intrinsic_v2f64 (v128, v128) -> (v128){{$}} 1519; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $1{{$}} 1520; SIMD128-NEXT: return $pop[[R]]{{$}} 1521declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>) 1522define <2 x double> @min_intrinsic_v2f64(<2 x double> %x, <2 x double> %y) { 1523 %a = call <2 x double> @llvm.minimum.v2f64(<2 x double> %x, <2 x double> %y) 1524 ret <2 x double> %a 1525} 1526 1527; CHECK-LABEL: max_intrinsic_v2f64: 1528; NO-SIMD128-NOT: f64x2 1529; SIMD128-NEXT: .functype max_intrinsic_v2f64 (v128, v128) -> (v128){{$}} 1530; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $1{{$}} 1531; SIMD128-NEXT: return $pop[[R]]{{$}} 1532declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>) 1533define <2 x double> @max_intrinsic_v2f64(<2 x double> %x, <2 x double> %y) { 1534 %a = call <2 x double> @llvm.maximum.v2f64(<2 x double> %x, <2 x double> %y) 1535 ret <2 x double> %a 1536} 1537 1538; CHECK-LABEL: min_const_intrinsic_v2f64: 1539; NO-SIMD128-NOT: f64x2 1540; SIMD128-NEXT: .functype min_const_intrinsic_v2f64 () -> (v128){{$}} 1541; SIMD128-NEXT: f64.const $push[[L:[0-9]+]]=, 0x1.4p2{{$}} 1542; SIMD128-NEXT: f64x2.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}} 1543; SIMD128-NEXT: return $pop[[R]]{{$}} 1544define <2 x double> @min_const_intrinsic_v2f64() { 1545 %a = call <2 x double> @llvm.minimum.v2f64( 1546 <2 x double> <double 42., double 42.>, 1547 <2 x double> <double 5., double 5.> 1548 ) 1549 ret <2 x double> %a 1550} 1551 1552; CHECK-LABEL: max_const_intrinsic_v2f64: 1553; NO-SIMD128-NOT: f64x2 1554; SIMD128-NEXT: .functype max_const_intrinsic_v2f64 () -> (v128){{$}} 1555; SIMD128-NEXT: f64.const $push[[L:[0-9]+]]=, 0x1.5p5{{$}} 1556; SIMD128-NEXT: f64x2.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}} 1557; SIMD128-NEXT: return $pop[[R]]{{$}} 1558define <2 x double> @max_const_intrinsic_v2f64() { 1559 %a = call <2 x double> @llvm.maximum.v2f64( 1560 <2 x double> <double 42., double 42.>, 1561 <2 x double> <double 5., double 5.> 1562 ) 1563 ret <2 x double> %a 1564} 1565 1566; CHECK-LABEL: add_v2f64: 1567; NO-SIMD128-NOT: f64x2 1568; SIMD128-VM-NOT: f62x2 1569; SIMD128-NEXT: .functype add_v2f64 (v128, v128) -> (v128){{$}} 1570; SIMD128-NEXT: f64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}} 1571; SIMD128-NEXT: return $pop[[R]]{{$}} 1572define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) { 1573 %a = fadd <2 x double> %x, %y 1574 ret <2 x double> %a 1575} 1576 1577; CHECK-LABEL: sub_v2f64: 1578; NO-SIMD128-NOT: f64x2 1579; SIMD128-VM-NOT: f62x2 1580; SIMD128-NEXT: .functype sub_v2f64 (v128, v128) -> (v128){{$}} 1581; SIMD128-NEXT: f64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 1582; SIMD128-NEXT: return $pop[[R]]{{$}} 1583define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) { 1584 %a = fsub <2 x double> %x, %y 1585 ret <2 x double> %a 1586} 1587 1588; CHECK-LABEL: div_v2f64: 1589; NO-SIMD128-NOT: f64x2 1590; SIMD128-VM-NOT: f62x2 1591; SIMD128-NEXT: .functype div_v2f64 (v128, v128) -> (v128){{$}} 1592; SIMD128-NEXT: f64x2.div $push[[R:[0-9]+]]=, $0, $1{{$}} 1593; SIMD128-NEXT: return $pop[[R]]{{$}} 1594define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) { 1595 %a = fdiv <2 x double> %x, %y 1596 ret <2 x double> %a 1597} 1598 1599; CHECK-LABEL: mul_v2f64: 1600; NO-SIMD128-NOT: f64x2 1601; SIMD128-VM-NOT: f62x2 1602; SIMD128-NEXT: .functype mul_v2f64 (v128, v128) -> (v128){{$}} 1603; SIMD128-NEXT: f64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 1604; SIMD128-NEXT: return $pop[[R]]{{$}} 1605define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) { 1606 %a = fmul <2 x double> %x, %y 1607 ret <2 x double> %a 1608} 1609 1610; CHECK-LABEL: sqrt_v2f64: 1611; NO-SIMD128-NOT: f64x2 1612; SIMD128-NEXT: .functype sqrt_v2f64 (v128) -> (v128){{$}} 1613; SIMD128-NEXT: f64x2.sqrt $push[[R:[0-9]+]]=, $0{{$}} 1614; SIMD128-NEXT: return $pop[[R]]{{$}} 1615declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %x) 1616define <2 x double> @sqrt_v2f64(<2 x double> %x) { 1617 %a = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %x) 1618 ret <2 x double> %a 1619} 1620