1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW 2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST 3; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM 4; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM 5; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128 6; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128 7 8; check that a non-test run (including explicit locals pass) at least finishes 9; RUN: llc < %s -O0 -mattr=+unimplemented-simd128 10; RUN: llc < %s -O2 -mattr=+unimplemented-simd128 11 12; Test that basic SIMD128 arithmetic operations assemble as expected. 13 14target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" 15target triple = "wasm32-unknown-unknown" 16 17; ============================================================================== 18; 16 x i8 19; ============================================================================== 20; CHECK-LABEL: add_v16i8: 21; NO-SIMD128-NOT: i8x16 22; SIMD128-NEXT: .functype add_v16i8 (v128, v128) -> (v128){{$}} 23; SIMD128-NEXT: i8x16.add $push[[R:[0-9]+]]=, $0, $1{{$}} 24; SIMD128-NEXT: return $pop[[R]]{{$}} 25define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) { 26 %a = add <16 x i8> %x, %y 27 ret <16 x i8> %a 28} 29 30; CHECK-LABEL: sub_v16i8: 31; NO-SIMD128-NOT: i8x16 32; SIMD128-NEXT: .functype sub_v16i8 (v128, v128) -> (v128){{$}} 33; SIMD128-NEXT: i8x16.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 34; SIMD128-NEXT: return $pop[[R]]{{$}} 35define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) { 36 %a = sub <16 x i8> %x, %y 37 ret <16 x i8> %a 38} 39 40; CHECK-LABEL: mul_v16i8: 41; NO-SIMD128-NOT: i8x16 42; SIMD128-NEXT: .functype mul_v16i8 (v128, v128) -> (v128){{$}} 43; SIMD128-NEXT: i8x16.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 44; SIMD128-NEXT: return $pop[[R]]{{$}} 45define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) { 46 %a = mul <16 x i8> %x, %y 47 ret <16 x i8> %a 48} 49 50; CHECK-LABEL: min_s_v16i8: 51; NO-SIMD128-NOT: i8x16 52; SIMD128-NEXT: .functype min_s_v16i8 (v128, v128) -> (v128){{$}} 53; SIMD128-NEXT: i8x16.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 54; SIMD128-NEXT: return $pop[[R]]{{$}} 55define <16 x i8> @min_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 56 %c = icmp slt <16 x i8> %x, %y 57 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 58 ret <16 x i8> %a 59} 60 61; CHECK-LABEL: min_u_v16i8: 62; NO-SIMD128-NOT: i8x16 63; SIMD128-NEXT: .functype min_u_v16i8 (v128, v128) -> (v128){{$}} 64; SIMD128-NEXT: i8x16.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 65; SIMD128-NEXT: return $pop[[R]]{{$}} 66define <16 x i8> @min_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 67 %c = icmp ult <16 x i8> %x, %y 68 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 69 ret <16 x i8> %a 70} 71 72; CHECK-LABEL: max_s_v16i8: 73; NO-SIMD128-NOT: i8x16 74; SIMD128-NEXT: .functype max_s_v16i8 (v128, v128) -> (v128){{$}} 75; SIMD128-NEXT: i8x16.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 76; SIMD128-NEXT: return $pop[[R]]{{$}} 77define <16 x i8> @max_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 78 %c = icmp sgt <16 x i8> %x, %y 79 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 80 ret <16 x i8> %a 81} 82 83; CHECK-LABEL: max_u_v16i8: 84; NO-SIMD128-NOT: i8x16 85; SIMD128-NEXT: .functype max_u_v16i8 (v128, v128) -> (v128){{$}} 86; SIMD128-NEXT: i8x16.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 87; SIMD128-NEXT: return $pop[[R]]{{$}} 88define <16 x i8> @max_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 89 %c = icmp ugt <16 x i8> %x, %y 90 %a = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %y 91 ret <16 x i8> %a 92} 93 94; CHECK-LABEL: avgr_u_v16i8: 95; NO-SIMD128-NOT: i8x16 96; SIMD128-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}} 97; SIMD128-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 98; SIMD128-NEXT: return $pop[[R]]{{$}} 99define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 100 %a = add nuw <16 x i8> %x, %y 101 %b = add nuw <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, 102 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 103 %c = udiv <16 x i8> %b, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, 104 i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 105 ret <16 x i8> %c 106} 107 108; CHECK-LABEL: avgr_u_v16i8_wrap: 109; NO-SIMD128-NOT: i8x16 110; SIMD128-NEXT: .functype avgr_u_v16i8_wrap (v128, v128) -> (v128){{$}} 111; SIMD128-NOT: i8x16.avgr_u 112define <16 x i8> @avgr_u_v16i8_wrap(<16 x i8> %x, <16 x i8> %y) { 113 %a = add <16 x i8> %x, %y 114 %b = add <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, 115 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 116 %c = udiv <16 x i8> %b, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, 117 i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 118 ret <16 x i8> %c 119} 120 121; CHECK-LABEL: neg_v16i8: 122; NO-SIMD128-NOT: i8x16 123; SIMD128-NEXT: .functype neg_v16i8 (v128) -> (v128){{$}} 124; SIMD128-NEXT: i8x16.neg $push[[R:[0-9]+]]=, $0{{$}} 125; SIMD128-NEXT: return $pop[[R]]{{$}} 126define <16 x i8> @neg_v16i8(<16 x i8> %x) { 127 %a = sub <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, 128 i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, 129 %x 130 ret <16 x i8> %a 131} 132 133; CHECK-LABEL: shl_v16i8: 134; NO-SIMD128-NOT: i8x16 135; SIMD128-NEXT: .functype shl_v16i8 (v128, i32) -> (v128){{$}} 136; SIMD128-NEXT: i8x16.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 137; SIMD128-NEXT: return $pop[[R]]{{$}} 138define <16 x i8> @shl_v16i8(<16 x i8> %v, i8 %x) { 139 %t = insertelement <16 x i8> undef, i8 %x, i32 0 140 %s = shufflevector <16 x i8> %t, <16 x i8> undef, 141 <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, 142 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 143 %a = shl <16 x i8> %v, %s 144 ret <16 x i8> %a 145} 146 147; CHECK-LABEL: shl_const_v16i8: 148; NO-SIMD128-NOT: i8x16 149; SIMD128-NEXT: .functype shl_const_v16i8 (v128) -> (v128){{$}} 150; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5 151; SIMD128-NEXT: i8x16.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 152; SIMD128-NEXT: return $pop[[R]]{{$}} 153define <16 x i8> @shl_const_v16i8(<16 x i8> %v) { 154 %a = shl <16 x i8> %v, 155 <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, 156 i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> 157 ret <16 x i8> %a 158} 159 160; CHECK-LABEL: shl_vec_v16i8: 161; NO-SIMD128-NOT: i8x16 162; SIMD128-NEXT: .functype shl_vec_v16i8 (v128, v128) -> (v128){{$}} 163; SIMD128-NEXT: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}} 164; SIMD128-NEXT: i8x16.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 165; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}} 166; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 167; SIMD128-NEXT: i32.shl $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]] 168; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]] 169; Skip 14 lanes 170; SIMD128: i8x16.extract_lane_s $push[[L4:[0-9]+]]=, $0, 15{{$}} 171; SIMD128-NEXT: i8x16.extract_lane_s $push[[L5:[0-9]+]]=, $1, 15{{$}} 172; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}} 173; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 174; SIMD128-NEXT: i32.shl $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 175; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}} 176; SIMD128-NEXT: return $pop[[R]]{{$}} 177define <16 x i8> @shl_vec_v16i8(<16 x i8> %v, <16 x i8> %x) { 178 %a = shl <16 x i8> %v, %x 179 ret <16 x i8> %a 180} 181 182; CHECK-LABEL: shr_s_v16i8: 183; NO-SIMD128-NOT: i8x16 184; SIMD128-NEXT: .functype shr_s_v16i8 (v128, i32) -> (v128){{$}} 185; SIMD128-NEXT: i8x16.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 186; SIMD128-NEXT: return $pop[[R]]{{$}} 187define <16 x i8> @shr_s_v16i8(<16 x i8> %v, i8 %x) { 188 %t = insertelement <16 x i8> undef, i8 %x, i32 0 189 %s = shufflevector <16 x i8> %t, <16 x i8> undef, 190 <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, 191 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 192 %a = ashr <16 x i8> %v, %s 193 ret <16 x i8> %a 194} 195 196; CHECK-LABEL: shr_s_vec_v16i8: 197; NO-SIMD128-NOT: i8x16 198; SIMD128-NEXT: .functype shr_s_vec_v16i8 (v128, v128) -> (v128){{$}} 199; SIMD128-NEXT: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}} 200; SIMD128-NEXT: i8x16.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 201; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}} 202; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 203; SIMD128-NEXT: i32.shr_s $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]] 204; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]] 205; Skip 14 lanes 206; SIMD128: i8x16.extract_lane_s $push[[L4:[0-9]+]]=, $0, 15{{$}} 207; SIMD128-NEXT: i8x16.extract_lane_s $push[[L5:[0-9]+]]=, $1, 15{{$}} 208; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}} 209; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 210; SIMD128-NEXT: i32.shr_s $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 211; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}} 212; SIMD128-NEXT: return $pop[[R]]{{$}} 213define <16 x i8> @shr_s_vec_v16i8(<16 x i8> %v, <16 x i8> %x) { 214 %a = ashr <16 x i8> %v, %x 215 ret <16 x i8> %a 216} 217 218; CHECK-LABEL: shr_u_v16i8: 219; NO-SIMD128-NOT: i8x16 220; SIMD128-NEXT: .functype shr_u_v16i8 (v128, i32) -> (v128){{$}} 221; SIMD128-NEXT: i8x16.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 222; SIMD128-NEXT: return $pop[[R]]{{$}} 223define <16 x i8> @shr_u_v16i8(<16 x i8> %v, i8 %x) { 224 %t = insertelement <16 x i8> undef, i8 %x, i32 0 225 %s = shufflevector <16 x i8> %t, <16 x i8> undef, 226 <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, 227 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 228 %a = lshr <16 x i8> %v, %s 229 ret <16 x i8> %a 230} 231 232; CHECK-LABEL: shr_u_vec_v16i8: 233; NO-SIMD128-NOT: i8x16 234; SIMD128-NEXT: .functype shr_u_vec_v16i8 (v128, v128) -> (v128){{$}} 235; SIMD128-NEXT: i8x16.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}} 236; SIMD128-NEXT: i8x16.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 237; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}} 238; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 239; SIMD128-NEXT: i32.shr_u $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]] 240; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]] 241; Skip 14 lanes 242; SIMD128: i8x16.extract_lane_u $push[[L4:[0-9]+]]=, $0, 15{{$}} 243; SIMD128-NEXT: i8x16.extract_lane_s $push[[L5:[0-9]+]]=, $1, 15{{$}} 244; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}} 245; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 246; SIMD128-NEXT: i32.shr_u $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 247; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}} 248; SIMD128-NEXT: return $pop[[R]]{{$}} 249define <16 x i8> @shr_u_vec_v16i8(<16 x i8> %v, <16 x i8> %x) { 250 %a = lshr <16 x i8> %v, %x 251 ret <16 x i8> %a 252} 253 254; CHECK-LABEL: and_v16i8: 255; NO-SIMD128-NOT: v128 256; SIMD128-NEXT: .functype and_v16i8 (v128, v128) -> (v128){{$}} 257; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 258; SIMD128-NEXT: return $pop[[R]]{{$}} 259define <16 x i8> @and_v16i8(<16 x i8> %x, <16 x i8> %y) { 260 %a = and <16 x i8> %x, %y 261 ret <16 x i8> %a 262} 263 264; CHECK-LABEL: or_v16i8: 265; NO-SIMD128-NOT: v128 266; SIMD128-NEXT: .functype or_v16i8 (v128, v128) -> (v128){{$}} 267; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 268; SIMD128-NEXT: return $pop[[R]]{{$}} 269define <16 x i8> @or_v16i8(<16 x i8> %x, <16 x i8> %y) { 270 %a = or <16 x i8> %x, %y 271 ret <16 x i8> %a 272} 273 274; CHECK-LABEL: xor_v16i8: 275; NO-SIMD128-NOT: v128 276; SIMD128-NEXT: .functype xor_v16i8 (v128, v128) -> (v128){{$}} 277; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 278; SIMD128-NEXT: return $pop[[R]]{{$}} 279define <16 x i8> @xor_v16i8(<16 x i8> %x, <16 x i8> %y) { 280 %a = xor <16 x i8> %x, %y 281 ret <16 x i8> %a 282} 283 284; CHECK-LABEL: not_v16i8: 285; NO-SIMD128-NOT: v128 286; SIMD128-NEXT: .functype not_v16i8 (v128) -> (v128){{$}} 287; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 288; SIMD128-NEXT: return $pop[[R]]{{$}} 289define <16 x i8> @not_v16i8(<16 x i8> %x) { 290 %a = xor <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, 291 i8 -1, i8 -1, i8 -1, i8 -1, 292 i8 -1, i8 -1, i8 -1, i8 -1, 293 i8 -1, i8 -1, i8 -1, i8 -1> 294 ret <16 x i8> %a 295} 296 297; CHECK-LABEL: andnot_v16i8: 298; NO-SIMD128-NOT: v128 299; SIMD128-VM-NOT: v128.andnot 300; SIMD128-NEXT: .functype andnot_v16i8 (v128, v128) -> (v128){{$}} 301; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 302; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 303; SIMD128-FAST-NEXT: v128.not 304; SIMD128-FAST-NEXT: v128.and 305; SIMD128-FAST-NEXT: return 306define <16 x i8> @andnot_v16i8(<16 x i8> %x, <16 x i8> %y) { 307 %inv_y = xor <16 x i8> %y, 308 <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 309 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 310 %a = and <16 x i8> %x, %inv_y 311 ret <16 x i8> %a 312} 313 314; CHECK-LABEL: bitselect_v16i8: 315; NO-SIMD128-NOT: v128 316; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}} 317; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 318; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 319; SIMD128-FAST-NEXT: v128.and 320; SIMD128-FAST-NEXT: v128.not 321; SIMD128-FAST-NEXT: v128.and 322; SIMD128-FAST-NEXT: v128.or 323; SIMD128-FAST-NEXT: return 324define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) { 325 %masked_v1 = and <16 x i8> %c, %v1 326 %inv_mask = xor <16 x i8> %c, 327 <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 328 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 329 %masked_v2 = and <16 x i8> %inv_mask, %v2 330 %a = or <16 x i8> %masked_v1, %masked_v2 331 ret <16 x i8> %a 332} 333 334; ============================================================================== 335; 8 x i16 336; ============================================================================== 337; CHECK-LABEL: add_v8i16: 338; NO-SIMD128-NOT: i16x8 339; SIMD128-NEXT: .functype add_v8i16 (v128, v128) -> (v128){{$}} 340; SIMD128-NEXT: i16x8.add $push[[R:[0-9]+]]=, $0, $1{{$}} 341; SIMD128-NEXT: return $pop[[R]]{{$}} 342define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) { 343 %a = add <8 x i16> %x, %y 344 ret <8 x i16> %a 345} 346 347; CHECK-LABEL: sub_v8i16: 348; NO-SIMD128-NOT: i16x8 349; SIMD128-NEXT: .functype sub_v8i16 (v128, v128) -> (v128){{$}} 350; SIMD128-NEXT: i16x8.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 351; SIMD128-NEXT: return $pop[[R]]{{$}} 352define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) { 353 %a = sub <8 x i16> %x, %y 354 ret <8 x i16> %a 355} 356 357; CHECK-LABEL: mul_v8i16: 358; NO-SIMD128-NOT: i16x8 359; SIMD128-NEXT: .functype mul_v8i16 (v128, v128) -> (v128){{$}} 360; SIMD128-NEXT: i16x8.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 361; SIMD128-NEXT: return $pop[[R]]{{$}} 362define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) { 363 %a = mul <8 x i16> %x, %y 364 ret <8 x i16> %a 365} 366 367; CHECK-LABEL: min_s_v8i16: 368; NO-SIMD128-NOT: i16x8 369; SIMD128-NEXT: .functype min_s_v8i16 (v128, v128) -> (v128){{$}} 370; SIMD128-NEXT: i16x8.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 371; SIMD128-NEXT: return $pop[[R]]{{$}} 372define <8 x i16> @min_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 373 %c = icmp slt <8 x i16> %x, %y 374 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 375 ret <8 x i16> %a 376} 377 378; CHECK-LABEL: min_u_v8i16: 379; NO-SIMD128-NOT: i16x8 380; SIMD128-NEXT: .functype min_u_v8i16 (v128, v128) -> (v128){{$}} 381; SIMD128-NEXT: i16x8.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 382; SIMD128-NEXT: return $pop[[R]]{{$}} 383define <8 x i16> @min_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 384 %c = icmp ult <8 x i16> %x, %y 385 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 386 ret <8 x i16> %a 387} 388 389; CHECK-LABEL: max_s_v8i16: 390; NO-SIMD128-NOT: i16x8 391; SIMD128-NEXT: .functype max_s_v8i16 (v128, v128) -> (v128){{$}} 392; SIMD128-NEXT: i16x8.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 393; SIMD128-NEXT: return $pop[[R]]{{$}} 394define <8 x i16> @max_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 395 %c = icmp sgt <8 x i16> %x, %y 396 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 397 ret <8 x i16> %a 398} 399 400; CHECK-LABEL: max_u_v8i16: 401; NO-SIMD128-NOT: i16x8 402; SIMD128-NEXT: .functype max_u_v8i16 (v128, v128) -> (v128){{$}} 403; SIMD128-NEXT: i16x8.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 404; SIMD128-NEXT: return $pop[[R]]{{$}} 405define <8 x i16> @max_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 406 %c = icmp ugt <8 x i16> %x, %y 407 %a = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %y 408 ret <8 x i16> %a 409} 410 411; CHECK-LABEL: avgr_u_v8i16: 412; NO-SIMD128-NOT: i16x8 413; SIMD128-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}} 414; SIMD128-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 415; SIMD128-NEXT: return $pop[[R]]{{$}} 416define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 417 %a = add nuw <8 x i16> %x, %y 418 %b = add nuw <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 419 %c = udiv <8 x i16> %b, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> 420 ret <8 x i16> %c 421} 422 423; CHECK-LABEL: avgr_u_v8i16_wrap: 424; NO-SIMD128-NOT: i16x8 425; SIMD128-NEXT: .functype avgr_u_v8i16_wrap (v128, v128) -> (v128){{$}} 426; SIMD128-NOT: i16x8.avgr_u 427define <8 x i16> @avgr_u_v8i16_wrap(<8 x i16> %x, <8 x i16> %y) { 428 %a = add <8 x i16> %x, %y 429 %b = add <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 430 %c = udiv <8 x i16> %b, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> 431 ret <8 x i16> %c 432} 433 434; CHECK-LABEL: neg_v8i16: 435; NO-SIMD128-NOT: i16x8 436; SIMD128-NEXT: .functype neg_v8i16 (v128) -> (v128){{$}} 437; SIMD128-NEXT: i16x8.neg $push[[R:[0-9]+]]=, $0{{$}} 438; SIMD128-NEXT: return $pop[[R]]{{$}} 439define <8 x i16> @neg_v8i16(<8 x i16> %x) { 440 %a = sub <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, 441 %x 442 ret <8 x i16> %a 443} 444 445; CHECK-LABEL: shl_v8i16: 446; NO-SIMD128-NOT: i16x8 447; SIMD128-NEXT: .functype shl_v8i16 (v128, i32) -> (v128){{$}} 448; SIMD128-NEXT: i16x8.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 449; SIMD128-NEXT: return $pop[[R]]{{$}} 450define <8 x i16> @shl_v8i16(<8 x i16> %v, i16 %x) { 451 %t = insertelement <8 x i16> undef, i16 %x, i32 0 452 %s = shufflevector <8 x i16> %t, <8 x i16> undef, 453 <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 454 %a = shl <8 x i16> %v, %s 455 ret <8 x i16> %a 456} 457 458; CHECK-LABEL: shl_const_v8i16: 459; NO-SIMD128-NOT: i16x8 460; SIMD128-NEXT: .functype shl_const_v8i16 (v128) -> (v128){{$}} 461; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5 462; SIMD128-NEXT: i16x8.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 463; SIMD128-NEXT: return $pop[[R]]{{$}} 464define <8 x i16> @shl_const_v8i16(<8 x i16> %v) { 465 %a = shl <8 x i16> %v, 466 <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> 467 ret <8 x i16> %a 468} 469 470; CHECK-LABEL: shl_vec_v8i16: 471; NO-SIMD128-NOT: i16x8 472; SIMD128-NEXT: .functype shl_vec_v8i16 (v128, v128) -> (v128){{$}} 473; SIMD128-NEXT: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}} 474; SIMD128-NEXT: i16x8.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 475; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}} 476; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 477; SIMD128-NEXT: i32.shl $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}} 478; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}} 479; Skip 6 lanes 480; SIMD128: i16x8.extract_lane_s $push[[L4:[0-9]+]]=, $0, 7{{$}} 481; SIMD128-NEXT: i16x8.extract_lane_s $push[[L5:[0-9]+]]=, $1, 7{{$}} 482; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}} 483; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 484; SIMD128-NEXT: i32.shl $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 485; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}} 486; SIMD128-NEXT: return $pop[[R]]{{$}} 487define <8 x i16> @shl_vec_v8i16(<8 x i16> %v, <8 x i16> %x) { 488 %a = shl <8 x i16> %v, %x 489 ret <8 x i16> %a 490} 491 492; CHECK-LABEL: shr_s_v8i16: 493; NO-SIMD128-NOT: i16x8 494; SIMD128-NEXT: .functype shr_s_v8i16 (v128, i32) -> (v128){{$}} 495; SIMD128-NEXT: i16x8.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 496; SIMD128-NEXT: return $pop[[R]]{{$}} 497define <8 x i16> @shr_s_v8i16(<8 x i16> %v, i16 %x) { 498 %t = insertelement <8 x i16> undef, i16 %x, i32 0 499 %s = shufflevector <8 x i16> %t, <8 x i16> undef, 500 <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 501 %a = ashr <8 x i16> %v, %s 502 ret <8 x i16> %a 503} 504 505; CHECK-LABEL: shr_s_vec_v8i16: 506; NO-SIMD128-NOT: i16x8 507; SIMD128-NEXT: .functype shr_s_vec_v8i16 (v128, v128) -> (v128){{$}} 508; SIMD128-NEXT: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}} 509; SIMD128-NEXT: i16x8.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 510; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}} 511; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 512; SIMD128-NEXT: i32.shr_s $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}} 513; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}} 514; Skip 6 lanes 515; SIMD128: i16x8.extract_lane_s $push[[L4:[0-9]+]]=, $0, 7{{$}} 516; SIMD128-NEXT: i16x8.extract_lane_s $push[[L5:[0-9]+]]=, $1, 7{{$}} 517; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}} 518; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 519; SIMD128-NEXT: i32.shr_s $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 520; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}} 521; SIMD128-NEXT: return $pop[[R]]{{$}} 522define <8 x i16> @shr_s_vec_v8i16(<8 x i16> %v, <8 x i16> %x) { 523 %a = ashr <8 x i16> %v, %x 524 ret <8 x i16> %a 525} 526 527; CHECK-LABEL: shr_u_v8i16: 528; NO-SIMD128-NOT: i16x8 529; SIMD128-NEXT: .functype shr_u_v8i16 (v128, i32) -> (v128){{$}} 530; SIMD128-NEXT: i16x8.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 531; SIMD128-NEXT: return $pop[[R]]{{$}} 532define <8 x i16> @shr_u_v8i16(<8 x i16> %v, i16 %x) { 533 %t = insertelement <8 x i16> undef, i16 %x, i32 0 534 %s = shufflevector <8 x i16> %t, <8 x i16> undef, 535 <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 536 %a = lshr <8 x i16> %v, %s 537 ret <8 x i16> %a 538} 539 540; CHECK-LABEL: shr_u_vec_v8i16: 541; NO-SIMD128-NOT: i16x8 542; SIMD128-NEXT: .functype shr_u_vec_v8i16 (v128, v128) -> (v128){{$}} 543; SIMD128-NEXT: i16x8.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}} 544; SIMD128-NEXT: i16x8.extract_lane_s $push[[L1:[0-9]+]]=, $1, 0{{$}} 545; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}} 546; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}} 547; SIMD128-NEXT: i32.shr_u $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}} 548; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}} 549; Skip 6 lanes 550; SIMD128: i16x8.extract_lane_u $push[[L4:[0-9]+]]=, $0, 7{{$}} 551; SIMD128-NEXT: i16x8.extract_lane_s $push[[L5:[0-9]+]]=, $1, 7{{$}} 552; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}} 553; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}} 554; SIMD128-NEXT: i32.shr_u $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}} 555; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}} 556; SIMD128-NEXT: return $pop[[R]]{{$}} 557define <8 x i16> @shr_u_vec_v8i16(<8 x i16> %v, <8 x i16> %x) { 558 %a = lshr <8 x i16> %v, %x 559 ret <8 x i16> %a 560} 561 562; CHECK-LABEL: and_v8i16: 563; NO-SIMD128-NOT: v128 564; SIMD128-NEXT: .functype and_v8i16 (v128, v128) -> (v128){{$}} 565; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 566; SIMD128-NEXT: return $pop[[R]]{{$}} 567define <8 x i16> @and_v8i16(<8 x i16> %x, <8 x i16> %y) { 568 %a = and <8 x i16> %x, %y 569 ret <8 x i16> %a 570} 571 572; CHECK-LABEL: or_v8i16: 573; NO-SIMD128-NOT: v128 574; SIMD128-NEXT: .functype or_v8i16 (v128, v128) -> (v128){{$}} 575; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 576; SIMD128-NEXT: return $pop[[R]]{{$}} 577define <8 x i16> @or_v8i16(<8 x i16> %x, <8 x i16> %y) { 578 %a = or <8 x i16> %x, %y 579 ret <8 x i16> %a 580} 581 582; CHECK-LABEL: xor_v8i16: 583; NO-SIMD128-NOT: v128 584; SIMD128-NEXT: .functype xor_v8i16 (v128, v128) -> (v128){{$}} 585; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 586; SIMD128-NEXT: return $pop[[R]]{{$}} 587define <8 x i16> @xor_v8i16(<8 x i16> %x, <8 x i16> %y) { 588 %a = xor <8 x i16> %x, %y 589 ret <8 x i16> %a 590} 591 592; CHECK-LABEL: not_v8i16: 593; NO-SIMD128-NOT: v128 594; SIMD128-NEXT: .functype not_v8i16 (v128) -> (v128){{$}} 595; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 596; SIMD128-NEXT: return $pop[[R]]{{$}} 597define <8 x i16> @not_v8i16(<8 x i16> %x) { 598 %a = xor <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, 599 i16 -1, i16 -1, i16 -1, i16 -1> 600 ret <8 x i16> %a 601} 602 603; CHECK-LABEL: andnot_v8i16: 604; SIMD128-VM-NOT: v128.andnot 605; NO-SIMD128-NOT: v128 606; SIMD128-NEXT: .functype andnot_v8i16 (v128, v128) -> (v128){{$}} 607; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 608; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 609; SIMD128-FAST-NEXT: v128.not 610; SIMD128-FAST-NEXT: v128.and 611; SIMD128-FAST-NEXT: return 612define <8 x i16> @andnot_v8i16(<8 x i16> %x, <8 x i16> %y) { 613 %inv_y = xor <8 x i16> %y, 614 <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 615 %a = and <8 x i16> %x, %inv_y 616 ret <8 x i16> %a 617} 618 619; CHECK-LABEL: bitselect_v8i16: 620; NO-SIMD128-NOT: v128 621; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}} 622; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 623; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 624; SIMD128-FAST-NEXT: v128.and 625; SIMD128-FAST-NEXT: v128.not 626; SIMD128-FAST-NEXT: v128.and 627; SIMD128-FAST-NEXT: v128.or 628; SIMD128-FAST-NEXT: return 629define <8 x i16> @bitselect_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) { 630 %masked_v1 = and <8 x i16> %v1, %c 631 %inv_mask = xor <8 x i16> 632 <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, 633 %c 634 %masked_v2 = and <8 x i16> %v2, %inv_mask 635 %a = or <8 x i16> %masked_v1, %masked_v2 636 ret <8 x i16> %a 637} 638 639; ============================================================================== 640; 4 x i32 641; ============================================================================== 642; CHECK-LABEL: add_v4i32: 643; NO-SIMD128-NOT: i32x4 644; SIMD128-NEXT: .functype add_v4i32 (v128, v128) -> (v128){{$}} 645; SIMD128-NEXT: i32x4.add $push[[R:[0-9]+]]=, $0, $1{{$}} 646; SIMD128-NEXT: return $pop[[R]]{{$}} 647define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) { 648 %a = add <4 x i32> %x, %y 649 ret <4 x i32> %a 650} 651 652; CHECK-LABEL: sub_v4i32: 653; NO-SIMD128-NOT: i32x4 654; SIMD128-NEXT: .functype sub_v4i32 (v128, v128) -> (v128){{$}} 655; SIMD128-NEXT: i32x4.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 656; SIMD128-NEXT: return $pop[[R]]{{$}} 657define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) { 658 %a = sub <4 x i32> %x, %y 659 ret <4 x i32> %a 660} 661 662; CHECK-LABEL: mul_v4i32: 663; NO-SIMD128-NOT: i32x4 664; SIMD128-NEXT: .functype mul_v4i32 (v128, v128) -> (v128){{$}} 665; SIMD128-NEXT: i32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 666; SIMD128-NEXT: return $pop[[R]]{{$}} 667define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) { 668 %a = mul <4 x i32> %x, %y 669 ret <4 x i32> %a 670} 671 672; CHECK-LABEL: min_s_v4i32: 673; NO-SIMD128-NOT: i32x4 674; SIMD128-NEXT: .functype min_s_v4i32 (v128, v128) -> (v128){{$}} 675; SIMD128-NEXT: i32x4.min_s $push[[R:[0-9]+]]=, $0, $1{{$}} 676; SIMD128-NEXT: return $pop[[R]]{{$}} 677define <4 x i32> @min_s_v4i32(<4 x i32> %x, <4 x i32> %y) { 678 %c = icmp slt <4 x i32> %x, %y 679 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 680 ret <4 x i32> %a 681} 682 683; CHECK-LABEL: min_u_v4i32: 684; NO-SIMD128-NOT: i32x4 685; SIMD128-NEXT: .functype min_u_v4i32 (v128, v128) -> (v128){{$}} 686; SIMD128-NEXT: i32x4.min_u $push[[R:[0-9]+]]=, $0, $1{{$}} 687; SIMD128-NEXT: return $pop[[R]]{{$}} 688define <4 x i32> @min_u_v4i32(<4 x i32> %x, <4 x i32> %y) { 689 %c = icmp ult <4 x i32> %x, %y 690 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 691 ret <4 x i32> %a 692} 693 694; CHECK-LABEL: max_s_v4i32: 695; NO-SIMD128-NOT: i32x4 696; SIMD128-NEXT: .functype max_s_v4i32 (v128, v128) -> (v128){{$}} 697; SIMD128-NEXT: i32x4.max_s $push[[R:[0-9]+]]=, $0, $1{{$}} 698; SIMD128-NEXT: return $pop[[R]]{{$}} 699define <4 x i32> @max_s_v4i32(<4 x i32> %x, <4 x i32> %y) { 700 %c = icmp sgt <4 x i32> %x, %y 701 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 702 ret <4 x i32> %a 703} 704 705; CHECK-LABEL: max_u_v4i32: 706; NO-SIMD128-NOT: i32x4 707; SIMD128-NEXT: .functype max_u_v4i32 (v128, v128) -> (v128){{$}} 708; SIMD128-NEXT: i32x4.max_u $push[[R:[0-9]+]]=, $0, $1{{$}} 709; SIMD128-NEXT: return $pop[[R]]{{$}} 710define <4 x i32> @max_u_v4i32(<4 x i32> %x, <4 x i32> %y) { 711 %c = icmp ugt <4 x i32> %x, %y 712 %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y 713 ret <4 x i32> %a 714} 715 716; CHECK-LABEL: neg_v4i32: 717; NO-SIMD128-NOT: i32x4 718; SIMD128-NEXT: .functype neg_v4i32 (v128) -> (v128){{$}} 719; SIMD128-NEXT: i32x4.neg $push[[R:[0-9]+]]=, $0{{$}} 720; SIMD128-NEXT: return $pop[[R]]{{$}} 721define <4 x i32> @neg_v4i32(<4 x i32> %x) { 722 %a = sub <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %x 723 ret <4 x i32> %a 724} 725 726; CHECK-LABEL: shl_v4i32: 727; NO-SIMD128-NOT: i32x4 728; SIMD128-NEXT: .functype shl_v4i32 (v128, i32) -> (v128){{$}} 729; SIMD128-NEXT: i32x4.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 730; SIMD128-NEXT: return $pop[[R]]{{$}} 731define <4 x i32> @shl_v4i32(<4 x i32> %v, i32 %x) { 732 %t = insertelement <4 x i32> undef, i32 %x, i32 0 733 %s = shufflevector <4 x i32> %t, <4 x i32> undef, 734 <4 x i32> <i32 0, i32 0, i32 0, i32 0> 735 %a = shl <4 x i32> %v, %s 736 ret <4 x i32> %a 737} 738 739; CHECK-LABEL: shl_const_v4i32: 740; NO-SIMD128-NOT: i32x4 741; SIMD128-NEXT: .functype shl_const_v4i32 (v128) -> (v128){{$}} 742; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5 743; SIMD128-NEXT: i32x4.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 744; SIMD128-NEXT: return $pop[[R]]{{$}} 745define <4 x i32> @shl_const_v4i32(<4 x i32> %v) { 746 %a = shl <4 x i32> %v, <i32 5, i32 5, i32 5, i32 5> 747 ret <4 x i32> %a 748} 749 750; CHECK-LABEL: shl_vec_v4i32: 751; NO-SIMD128-NOT: i32x4 752; SIMD128-NEXT: .functype shl_vec_v4i32 (v128, v128) -> (v128){{$}} 753; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 754; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 755; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 756; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 757; Skip 2 lanes 758; SIMD128: i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}} 759; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}} 760; SIMD128-NEXT: i32.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 761; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}} 762; SIMD128-NEXT: return $pop[[R]]{{$}} 763define <4 x i32> @shl_vec_v4i32(<4 x i32> %v, <4 x i32> %x) { 764 %a = shl <4 x i32> %v, %x 765 ret <4 x i32> %a 766} 767 768; CHECK-LABEL: shr_s_v4i32: 769; NO-SIMD128-NOT: i32x4 770; SIMD128-NEXT: .functype shr_s_v4i32 (v128, i32) -> (v128){{$}} 771; SIMD128-NEXT: i32x4.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 772; SIMD128-NEXT: return $pop[[R]]{{$}} 773define <4 x i32> @shr_s_v4i32(<4 x i32> %v, i32 %x) { 774 %t = insertelement <4 x i32> undef, i32 %x, i32 0 775 %s = shufflevector <4 x i32> %t, <4 x i32> undef, 776 <4 x i32> <i32 0, i32 0, i32 0, i32 0> 777 %a = ashr <4 x i32> %v, %s 778 ret <4 x i32> %a 779} 780 781; CHECK-LABEL: shr_s_vec_v4i32: 782; NO-SIMD128-NOT: i32x4 783; SIMD128-NEXT: .functype shr_s_vec_v4i32 (v128, v128) -> (v128){{$}} 784; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 785; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 786; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 787; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 788; Skip 2 lanes 789; SIMD128: i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}} 790; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}} 791; SIMD128-NEXT: i32.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 792; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}} 793; SIMD128-NEXT: return $pop[[R]]{{$}} 794define <4 x i32> @shr_s_vec_v4i32(<4 x i32> %v, <4 x i32> %x) { 795 %a = ashr <4 x i32> %v, %x 796 ret <4 x i32> %a 797} 798 799; CHECK-LABEL: shr_u_v4i32: 800; NO-SIMD128-NOT: i32x4 801; SIMD128-NEXT: .functype shr_u_v4i32 (v128, i32) -> (v128){{$}} 802; SIMD128-NEXT: i32x4.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 803; SIMD128-NEXT: return $pop[[R]]{{$}} 804define <4 x i32> @shr_u_v4i32(<4 x i32> %v, i32 %x) { 805 %t = insertelement <4 x i32> undef, i32 %x, i32 0 806 %s = shufflevector <4 x i32> %t, <4 x i32> undef, 807 <4 x i32> <i32 0, i32 0, i32 0, i32 0> 808 %a = lshr <4 x i32> %v, %s 809 ret <4 x i32> %a 810} 811 812; CHECK-LABEL: shr_u_vec_v4i32: 813; NO-SIMD128-NOT: i32x4 814; SIMD128-NEXT: .functype shr_u_vec_v4i32 (v128, v128) -> (v128){{$}} 815; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 816; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 817; SIMD128-NEXT: i32.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 818; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 819; Skip 2 lanes 820; SIMD128: i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}} 821; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}} 822; SIMD128-NEXT: i32.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 823; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}} 824; SIMD128-NEXT: return $pop[[R]]{{$}} 825define <4 x i32> @shr_u_vec_v4i32(<4 x i32> %v, <4 x i32> %x) { 826 %a = lshr <4 x i32> %v, %x 827 ret <4 x i32> %a 828} 829 830; CHECK-LABEL: and_v4i32: 831; NO-SIMD128-NOT: v128 832; SIMD128-NEXT: .functype and_v4i32 (v128, v128) -> (v128){{$}} 833; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 834; SIMD128-NEXT: return $pop[[R]]{{$}} 835define <4 x i32> @and_v4i32(<4 x i32> %x, <4 x i32> %y) { 836 %a = and <4 x i32> %x, %y 837 ret <4 x i32> %a 838} 839 840; CHECK-LABEL: or_v4i32: 841; NO-SIMD128-NOT: v128 842; SIMD128-NEXT: .functype or_v4i32 (v128, v128) -> (v128){{$}} 843; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 844; SIMD128-NEXT: return $pop[[R]]{{$}} 845define <4 x i32> @or_v4i32(<4 x i32> %x, <4 x i32> %y) { 846 %a = or <4 x i32> %x, %y 847 ret <4 x i32> %a 848} 849 850; CHECK-LABEL: xor_v4i32: 851; NO-SIMD128-NOT: v128 852; SIMD128-NEXT: .functype xor_v4i32 (v128, v128) -> (v128){{$}} 853; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 854; SIMD128-NEXT: return $pop[[R]]{{$}} 855define <4 x i32> @xor_v4i32(<4 x i32> %x, <4 x i32> %y) { 856 %a = xor <4 x i32> %x, %y 857 ret <4 x i32> %a 858} 859 860; CHECK-LABEL: not_v4i32: 861; NO-SIMD128-NOT: v128 862; SIMD128-NEXT: .functype not_v4i32 (v128) -> (v128){{$}} 863; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 864; SIMD128-NEXT: return $pop[[R]]{{$}} 865define <4 x i32> @not_v4i32(<4 x i32> %x) { 866 %a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 867 ret <4 x i32> %a 868} 869 870; CHECK-LABEL: andnot_v4i32: 871; SIMD128-VM-NOT: v128.andnot 872; NO-SIMD128-NOT: v128 873; SIMD128-NEXT: .functype andnot_v4i32 (v128, v128) -> (v128){{$}} 874; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 875; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 876; SIMD128-FAST-NEXT: v128.not 877; SIMD128-FAST-NEXT: v128.and 878; SIMD128-FAST-NEXT: return 879define <4 x i32> @andnot_v4i32(<4 x i32> %x, <4 x i32> %y) { 880 %inv_y = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1> 881 %a = and <4 x i32> %x, %inv_y 882 ret <4 x i32> %a 883} 884 885; CHECK-LABEL: bitselect_v4i32: 886; NO-SIMD128-NOT: v128 887; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}} 888; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 889; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 890; SIMD128-FAST-NEXT: v128.not 891; SIMD128-FAST-NEXT: v128.and 892; SIMD128-FAST-NEXT: v128.and 893; SIMD128-FAST-NEXT: v128.or 894; SIMD128-FAST-NEXT: return 895define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) { 896 %masked_v1 = and <4 x i32> %c, %v1 897 %inv_mask = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %c 898 %masked_v2 = and <4 x i32> %inv_mask, %v2 899 %a = or <4 x i32> %masked_v2, %masked_v1 900 ret <4 x i32> %a 901} 902 903; ============================================================================== 904; 2 x i64 905; ============================================================================== 906; CHECK-LABEL: add_v2i64: 907; NO-SIMD128-NOT: i64x2 908; SIMD128-NEXT: .functype add_v2i64 (v128, v128) -> (v128){{$}} 909; SIMD128-NEXT: i64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}} 910; SIMD128-NEXT: return $pop[[R]]{{$}} 911define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) { 912 %a = add <2 x i64> %x, %y 913 ret <2 x i64> %a 914} 915 916; CHECK-LABEL: sub_v2i64: 917; NO-SIMD128-NOT: i64x2 918; SIMD128-NEXT: .functype sub_v2i64 (v128, v128) -> (v128){{$}} 919; SIMD128-NEXT: i64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 920; SIMD128-NEXT: return $pop[[R]]{{$}} 921define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) { 922 %a = sub <2 x i64> %x, %y 923 ret <2 x i64> %a 924} 925 926; v2i64.mul is not in spec 927; CHECK-LABEL: mul_v2i64: 928; NO-SIMD128-NOT: i64x2 929; SIMD128-NOT: i64x2.mul 930; SIMD128: i64x2.extract_lane 931; SIMD128: i64.mul 932define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) { 933 %a = mul <2 x i64> %x, %y 934 ret <2 x i64> %a 935} 936 937; CHECK-LABEL: neg_v2i64: 938; NO-SIMD128-NOT: i64x2 939; SIMD128-NEXT: .functype neg_v2i64 (v128) -> (v128){{$}} 940; SIMD128-NEXT: i64x2.neg $push[[R:[0-9]+]]=, $0{{$}} 941; SIMD128-NEXT: return $pop[[R]]{{$}} 942define <2 x i64> @neg_v2i64(<2 x i64> %x) { 943 %a = sub <2 x i64> <i64 0, i64 0>, %x 944 ret <2 x i64> %a 945} 946 947; CHECK-LABEL: shl_v2i64: 948; NO-SIMD128-NOT: i64x2 949; SIMD128-NEXT: .functype shl_v2i64 (v128, i32) -> (v128){{$}} 950; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 951; SIMD128-NEXT: return $pop[[R]]{{$}} 952define <2 x i64> @shl_v2i64(<2 x i64> %v, i32 %x) { 953 %x2 = zext i32 %x to i64 954 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 955 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 956 %a = shl <2 x i64> %v, %s 957 ret <2 x i64> %a 958} 959 960; CHECK-LABEL: shl_sext_v2i64: 961; NO-SIMD128-NOT: i64x2 962; SIMD128-NEXT: .functype shl_sext_v2i64 (v128, i32) -> (v128){{$}} 963; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $1{{$}} 964; SIMD128-NEXT: return $pop[[R]]{{$}} 965define <2 x i64> @shl_sext_v2i64(<2 x i64> %v, i32 %x) { 966 %x2 = sext i32 %x to i64 967 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 968 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 969 %a = shl <2 x i64> %v, %s 970 ret <2 x i64> %a 971} 972 973; CHECK-LABEL: shl_noext_v2i64: 974; NO-SIMD128-NOT: i64x2 975; SIMD128-NEXT: .functype shl_noext_v2i64 (v128, i64) -> (v128){{$}} 976; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}} 977; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 978; SIMD128-NEXT: return $pop[[R]]{{$}} 979define <2 x i64> @shl_noext_v2i64(<2 x i64> %v, i64 %x) { 980 %t = insertelement <2 x i64> undef, i64 %x, i32 0 981 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 982 %a = shl <2 x i64> %v, %s 983 ret <2 x i64> %a 984} 985 986; CHECK-LABEL: shl_const_v2i64: 987; NO-SIMD128-NOT: i64x2 988; SIMD128-NEXT: .functype shl_const_v2i64 (v128) -> (v128){{$}} 989; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}} 990; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 991; SIMD128-NEXT: return $pop[[R]]{{$}} 992define <2 x i64> @shl_const_v2i64(<2 x i64> %v) { 993 %a = shl <2 x i64> %v, <i64 5, i64 5> 994 ret <2 x i64> %a 995} 996 997; CHECK-LABEL: shl_vec_v2i64: 998; NO-SIMD128-NOT: i64x2 999; SIMD128-NEXT: .functype shl_vec_v2i64 (v128, v128) -> (v128){{$}} 1000; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 1001; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 1002; SIMD128-NEXT: i64.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 1003; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 1004; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}} 1005; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}} 1006; SIMD128-NEXT: i64.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 1007; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}} 1008; SIMD128-NEXT: return $pop[[R]]{{$}} 1009define <2 x i64> @shl_vec_v2i64(<2 x i64> %v, <2 x i64> %x) { 1010 %a = shl <2 x i64> %v, %x 1011 ret <2 x i64> %a 1012} 1013 1014; CHECK-LABEL: shr_s_v2i64: 1015; NO-SIMD128-NOT: i64x2 1016; SIMD128-NEXT: .functype shr_s_v2i64 (v128, i32) -> (v128){{$}} 1017; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 1018; SIMD128-NEXT: return $pop[[R]]{{$}} 1019define <2 x i64> @shr_s_v2i64(<2 x i64> %v, i32 %x) { 1020 %x2 = zext i32 %x to i64 1021 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1022 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1023 %a = ashr <2 x i64> %v, %s 1024 ret <2 x i64> %a 1025} 1026 1027; CHECK-LABEL: shr_s_sext_v2i64: 1028; NO-SIMD128-NOT: i64x2 1029; SIMD128-NEXT: .functype shr_s_sext_v2i64 (v128, i32) -> (v128){{$}} 1030; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}} 1031; SIMD128-NEXT: return $pop[[R]]{{$}} 1032define <2 x i64> @shr_s_sext_v2i64(<2 x i64> %v, i32 %x) { 1033 %x2 = sext i32 %x to i64 1034 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1035 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1036 %a = ashr <2 x i64> %v, %s 1037 ret <2 x i64> %a 1038} 1039 1040; CHECK-LABEL: shr_s_noext_v2i64: 1041; NO-SIMD128-NOT: i64x2 1042; SIMD128-NEXT: .functype shr_s_noext_v2i64 (v128, i64) -> (v128){{$}} 1043; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}} 1044; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1045; SIMD128-NEXT: return $pop[[R]]{{$}} 1046define <2 x i64> @shr_s_noext_v2i64(<2 x i64> %v, i64 %x) { 1047 %t = insertelement <2 x i64> undef, i64 %x, i32 0 1048 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1049 %a = ashr <2 x i64> %v, %s 1050 ret <2 x i64> %a 1051} 1052 1053; CHECK-LABEL: shr_s_const_v2i64: 1054; NO-SIMD128-NOT: i64x2 1055; SIMD128-NEXT: .functype shr_s_const_v2i64 (v128) -> (v128){{$}} 1056; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}} 1057; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1058; SIMD128-NEXT: return $pop[[R]]{{$}} 1059define <2 x i64> @shr_s_const_v2i64(<2 x i64> %v) { 1060 %a = ashr <2 x i64> %v, <i64 5, i64 5> 1061 ret <2 x i64> %a 1062} 1063 1064; CHECK-LABEL: shr_s_vec_v2i64: 1065; NO-SIMD128-NOT: i64x2 1066; SIMD128-NEXT: .functype shr_s_vec_v2i64 (v128, v128) -> (v128){{$}} 1067; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 1068; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 1069; SIMD128-NEXT: i64.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 1070; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 1071; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}} 1072; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}} 1073; SIMD128-NEXT: i64.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 1074; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}} 1075; SIMD128-NEXT: return $pop[[R]]{{$}} 1076define <2 x i64> @shr_s_vec_v2i64(<2 x i64> %v, <2 x i64> %x) { 1077 %a = ashr <2 x i64> %v, %x 1078 ret <2 x i64> %a 1079} 1080 1081; CHECK-LABEL: shr_u_v2i64: 1082; NO-SIMD128-NOT: i64x2 1083; SIMD128-NEXT: .functype shr_u_v2i64 (v128, i32) -> (v128){{$}} 1084; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 1085; SIMD128-NEXT: return $pop[[R]]{{$}} 1086define <2 x i64> @shr_u_v2i64(<2 x i64> %v, i32 %x) { 1087 %x2 = zext i32 %x to i64 1088 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1089 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1090 %a = lshr <2 x i64> %v, %s 1091 ret <2 x i64> %a 1092} 1093 1094; CHECK-LABEL: shr_u_sext_v2i64: 1095; NO-SIMD128-NOT: i64x2 1096; SIMD128-NEXT: .functype shr_u_sext_v2i64 (v128, i32) -> (v128){{$}} 1097; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 1098; SIMD128-NEXT: return $pop[[R]]{{$}} 1099define <2 x i64> @shr_u_sext_v2i64(<2 x i64> %v, i32 %x) { 1100 %x2 = sext i32 %x to i64 1101 %t = insertelement <2 x i64> undef, i64 %x2, i32 0 1102 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1103 %a = lshr <2 x i64> %v, %s 1104 ret <2 x i64> %a 1105} 1106 1107; CHECK-LABEL: shr_u_noext_v2i64: 1108; NO-SIMD128-NOT: i64x2 1109; SIMD128-NEXT: .functype shr_u_noext_v2i64 (v128, i64) -> (v128){{$}} 1110; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}} 1111; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1112; SIMD128-NEXT: return $pop[[R]]{{$}} 1113define <2 x i64> @shr_u_noext_v2i64(<2 x i64> %v, i64 %x) { 1114 %t = insertelement <2 x i64> undef, i64 %x, i32 0 1115 %s = shufflevector <2 x i64> %t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> 1116 %a = lshr <2 x i64> %v, %s 1117 ret <2 x i64> %a 1118} 1119 1120; CHECK-LABEL: shr_u_const_v2i64: 1121; NO-SIMD128-NOT: i64x2 1122; SIMD128-NEXT: .functype shr_u_const_v2i64 (v128) -> (v128){{$}} 1123; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}} 1124; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1125; SIMD128-NEXT: return $pop[[R]]{{$}} 1126define <2 x i64> @shr_u_const_v2i64(<2 x i64> %v) { 1127 %a = lshr <2 x i64> %v, <i64 5, i64 5> 1128 ret <2 x i64> %a 1129} 1130 1131; CHECK-LABEL: shr_u_vec_v2i64: 1132; NO-SIMD128-NOT: i64x2 1133; SIMD128-NEXT: .functype shr_u_vec_v2i64 (v128, v128) -> (v128){{$}} 1134; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}} 1135; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}} 1136; SIMD128-NEXT: i64.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} 1137; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}} 1138; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}} 1139; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}} 1140; SIMD128-NEXT: i64.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} 1141; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}} 1142; SIMD128-NEXT: return $pop[[R]]{{$}} 1143define <2 x i64> @shr_u_vec_v2i64(<2 x i64> %v, <2 x i64> %x) { 1144 %a = lshr <2 x i64> %v, %x 1145 ret <2 x i64> %a 1146} 1147 1148; CHECK-LABEL: and_v2i64: 1149; NO-SIMD128-NOT: v128 1150; SIMD128-NEXT: .functype and_v2i64 (v128, v128) -> (v128){{$}} 1151; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}} 1152; SIMD128-NEXT: return $pop[[R]]{{$}} 1153define <2 x i64> @and_v2i64(<2 x i64> %x, <2 x i64> %y) { 1154 %a = and <2 x i64> %x, %y 1155 ret <2 x i64> %a 1156} 1157 1158; CHECK-LABEL: or_v2i64: 1159; NO-SIMD128-NOT: v128 1160; SIMD128-NEXT: .functype or_v2i64 (v128, v128) -> (v128){{$}} 1161; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}} 1162; SIMD128-NEXT: return $pop[[R]]{{$}} 1163define <2 x i64> @or_v2i64(<2 x i64> %x, <2 x i64> %y) { 1164 %a = or <2 x i64> %x, %y 1165 ret <2 x i64> %a 1166} 1167 1168; CHECK-LABEL: xor_v2i64: 1169; NO-SIMD128-NOT: v128 1170; SIMD128-NEXT: .functype xor_v2i64 (v128, v128) -> (v128){{$}} 1171; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}} 1172; SIMD128-NEXT: return $pop[[R]]{{$}} 1173define <2 x i64> @xor_v2i64(<2 x i64> %x, <2 x i64> %y) { 1174 %a = xor <2 x i64> %x, %y 1175 ret <2 x i64> %a 1176} 1177 1178; CHECK-LABEL: not_v2i64: 1179; NO-SIMD128-NOT: v128 1180; SIMD128-NEXT: .functype not_v2i64 (v128) -> (v128){{$}} 1181; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} 1182; SIMD128-NEXT: return $pop[[R]]{{$}} 1183define <2 x i64> @not_v2i64(<2 x i64> %x) { 1184 %a = xor <2 x i64> %x, <i64 -1, i64 -1> 1185 ret <2 x i64> %a 1186} 1187 1188; CHECK-LABEL: andnot_v2i64: 1189; SIMD128-VM-NOT: v128.andnot 1190; NO-SIMD128-NOT: v128 1191; SIMD128-NEXT: .functype andnot_v2i64 (v128, v128) -> (v128){{$}} 1192; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}} 1193; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1194; SIMD128-FAST-NEXT: v128.not 1195; SIMD128-FAST-NEXT: v128.and 1196; SIMD128-FAST-NEXT: return 1197define <2 x i64> @andnot_v2i64(<2 x i64> %x, <2 x i64> %y) { 1198 %inv_y = xor <2 x i64> %y, <i64 -1, i64 -1> 1199 %a = and <2 x i64> %x, %inv_y 1200 ret <2 x i64> %a 1201} 1202 1203; CHECK-LABEL: bitselect_v2i64: 1204; NO-SIMD128-NOT: v128 1205; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}} 1206; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} 1207; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} 1208; SIMD128-FAST-NEXT: v128.not 1209; SIMD128-FAST-NEXT: v128.and 1210; SIMD128-FAST-NEXT: v128.and 1211; SIMD128-FAST-NEXT: v128.or 1212; SIMD128-FAST-NEXT: return 1213define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) { 1214 %masked_v1 = and <2 x i64> %v1, %c 1215 %inv_mask = xor <2 x i64> <i64 -1, i64 -1>, %c 1216 %masked_v2 = and <2 x i64> %v2, %inv_mask 1217 %a = or <2 x i64> %masked_v2, %masked_v1 1218 ret <2 x i64> %a 1219} 1220 1221; ============================================================================== 1222; 4 x float 1223; ============================================================================== 1224; CHECK-LABEL: neg_v4f32: 1225; NO-SIMD128-NOT: f32x4 1226; SIMD128-NEXT: .functype neg_v4f32 (v128) -> (v128){{$}} 1227; SIMD128-NEXT: f32x4.neg $push[[R:[0-9]+]]=, $0{{$}} 1228; SIMD128-NEXT: return $pop[[R]]{{$}} 1229define <4 x float> @neg_v4f32(<4 x float> %x) { 1230 ; nsz makes this semantically equivalent to flipping sign bit 1231 %a = fsub nsz <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, %x 1232 ret <4 x float> %a 1233} 1234 1235; CHECK-LABEL: abs_v4f32: 1236; NO-SIMD128-NOT: f32x4 1237; SIMD128-NEXT: .functype abs_v4f32 (v128) -> (v128){{$}} 1238; SIMD128-NEXT: f32x4.abs $push[[R:[0-9]+]]=, $0{{$}} 1239; SIMD128-NEXT: return $pop[[R]]{{$}} 1240declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone 1241define <4 x float> @abs_v4f32(<4 x float> %x) { 1242 %a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x) 1243 ret <4 x float> %a 1244} 1245 1246; CHECK-LABEL: min_unordered_v4f32: 1247; NO-SIMD128-NOT: f32x4 1248; SIMD128-NEXT: .functype min_unordered_v4f32 (v128) -> (v128){{$}} 1249; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 1250; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1251; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1252; SIMD128-NEXT: return $pop[[R]]{{$}} 1253define <4 x float> @min_unordered_v4f32(<4 x float> %x) { 1254 %cmps = fcmp ule <4 x float> %x, <float 5., float 5., float 5., float 5.> 1255 %a = select <4 x i1> %cmps, <4 x float> %x, 1256 <4 x float> <float 5., float 5., float 5., float 5.> 1257 ret <4 x float> %a 1258} 1259 1260; CHECK-LABEL: max_unordered_v4f32: 1261; NO-SIMD128-NOT: f32x4 1262; SIMD128-NEXT: .functype max_unordered_v4f32 (v128) -> (v128){{$}} 1263; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 1264; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1265; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1266; SIMD128-NEXT: return $pop[[R]]{{$}} 1267define <4 x float> @max_unordered_v4f32(<4 x float> %x) { 1268 %cmps = fcmp uge <4 x float> %x, <float 5., float 5., float 5., float 5.> 1269 %a = select <4 x i1> %cmps, <4 x float> %x, 1270 <4 x float> <float 5., float 5., float 5., float 5.> 1271 ret <4 x float> %a 1272} 1273 1274; CHECK-LABEL: min_ordered_v4f32: 1275; NO-SIMD128-NOT: f32x4 1276; SIMD128-NEXT: .functype min_ordered_v4f32 (v128) -> (v128){{$}} 1277; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 1278; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1279; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1280; SIMD128-NEXT: return $pop[[R]]{{$}} 1281define <4 x float> @min_ordered_v4f32(<4 x float> %x) { 1282 %cmps = fcmp ole <4 x float> <float 5., float 5., float 5., float 5.>, %x 1283 %a = select <4 x i1> %cmps, 1284 <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x 1285 ret <4 x float> %a 1286} 1287 1288; CHECK-LABEL: max_ordered_v4f32: 1289; NO-SIMD128-NOT: f32x4 1290; SIMD128-NEXT: .functype max_ordered_v4f32 (v128) -> (v128){{$}} 1291; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 1292; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1293; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1294; SIMD128-NEXT: return $pop[[R]]{{$}} 1295define <4 x float> @max_ordered_v4f32(<4 x float> %x) { 1296 %cmps = fcmp oge <4 x float> <float 5., float 5., float 5., float 5.>, %x 1297 %a = select <4 x i1> %cmps, 1298 <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x 1299 ret <4 x float> %a 1300} 1301 1302; CHECK-LABEL: min_intrinsic_v4f32: 1303; NO-SIMD128-NOT: f32x4 1304; SIMD128-NEXT: .functype min_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1305; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $1{{$}} 1306; SIMD128-NEXT: return $pop[[R]]{{$}} 1307declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>) 1308define <4 x float> @min_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1309 %a = call <4 x float> @llvm.minimum.v4f32(<4 x float> %x, <4 x float> %y) 1310 ret <4 x float> %a 1311} 1312 1313; CHECK-LABEL: minnum_intrinsic_v4f32: 1314; NO-SIMD128-NOT: f32x4 1315; SIMD128-NEXT: .functype minnum_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1316; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $1{{$}} 1317; SIMD128-NEXT: return $pop[[R]]{{$}} 1318declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) 1319define <4 x float> @minnum_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1320 %a = call nnan <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float> %y) 1321 ret <4 x float> %a 1322} 1323 1324; CHECK-LABEL: max_intrinsic_v4f32: 1325; NO-SIMD128-NOT: f32x4 1326; SIMD128-NEXT: .functype max_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1327; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $1{{$}} 1328; SIMD128-NEXT: return $pop[[R]]{{$}} 1329declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>) 1330define <4 x float> @max_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1331 %a = call <4 x float> @llvm.maximum.v4f32(<4 x float> %x, <4 x float> %y) 1332 ret <4 x float> %a 1333} 1334 1335; CHECK-LABEL: maxnum_intrinsic_v4f32: 1336; NO-SIMD128-NOT: f32x4 1337; SIMD128-NEXT: .functype maxnum_intrinsic_v4f32 (v128, v128) -> (v128){{$}} 1338; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $1{{$}} 1339; SIMD128-NEXT: return $pop[[R]]{{$}} 1340declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) 1341define <4 x float> @maxnum_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) { 1342 %a = call nnan <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float> %y) 1343 ret <4 x float> %a 1344} 1345 1346; CHECK-LABEL: min_const_intrinsic_v4f32: 1347; NO-SIMD128-NOT: f32x4 1348; SIMD128-NEXT: .functype min_const_intrinsic_v4f32 () -> (v128){{$}} 1349; SIMD128-NEXT: f32.const $push[[L:[0-9]+]]=, 0x1.4p2{{$}} 1350; SIMD128-NEXT: f32x4.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}} 1351; SIMD128-NEXT: return $pop[[R]]{{$}} 1352define <4 x float> @min_const_intrinsic_v4f32() { 1353 %a = call <4 x float> @llvm.minimum.v4f32( 1354 <4 x float> <float 42., float 42., float 42., float 42.>, 1355 <4 x float> <float 5., float 5., float 5., float 5.> 1356 ) 1357 ret <4 x float> %a 1358} 1359 1360; CHECK-LABEL: max_const_intrinsic_v4f32: 1361; NO-SIMD128-NOT: f32x4 1362; SIMD128-NEXT: .functype max_const_intrinsic_v4f32 () -> (v128){{$}} 1363; SIMD128-NEXT: f32.const $push[[L:[0-9]+]]=, 0x1.5p5{{$}} 1364; SIMD128-NEXT: f32x4.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}} 1365; SIMD128-NEXT: return $pop[[R]]{{$}} 1366define <4 x float> @max_const_intrinsic_v4f32() { 1367 %a = call <4 x float> @llvm.maximum.v4f32( 1368 <4 x float> <float 42., float 42., float 42., float 42.>, 1369 <4 x float> <float 5., float 5., float 5., float 5.> 1370 ) 1371 ret <4 x float> %a 1372} 1373 1374; CHECK-LABEL: add_v4f32: 1375; NO-SIMD128-NOT: f32x4 1376; SIMD128-NEXT: .functype add_v4f32 (v128, v128) -> (v128){{$}} 1377; SIMD128-NEXT: f32x4.add $push[[R:[0-9]+]]=, $0, $1{{$}} 1378; SIMD128-NEXT: return $pop[[R]]{{$}} 1379define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) { 1380 %a = fadd <4 x float> %x, %y 1381 ret <4 x float> %a 1382} 1383 1384; CHECK-LABEL: sub_v4f32: 1385; NO-SIMD128-NOT: f32x4 1386; SIMD128-NEXT: .functype sub_v4f32 (v128, v128) -> (v128){{$}} 1387; SIMD128-NEXT: f32x4.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 1388; SIMD128-NEXT: return $pop[[R]]{{$}} 1389define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) { 1390 %a = fsub <4 x float> %x, %y 1391 ret <4 x float> %a 1392} 1393 1394; CHECK-LABEL: div_v4f32: 1395; NO-SIMD128-NOT: f32x4 1396; SIMD128-NEXT: .functype div_v4f32 (v128, v128) -> (v128){{$}} 1397; SIMD128-NEXT: f32x4.div $push[[R:[0-9]+]]=, $0, $1{{$}} 1398; SIMD128-NEXT: return $pop[[R]]{{$}} 1399define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) { 1400 %a = fdiv <4 x float> %x, %y 1401 ret <4 x float> %a 1402} 1403 1404; CHECK-LABEL: mul_v4f32: 1405; NO-SIMD128-NOT: f32x4 1406; SIMD128-NEXT: .functype mul_v4f32 (v128, v128) -> (v128){{$}} 1407; SIMD128-NEXT: f32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 1408; SIMD128-NEXT: return $pop[[R]]{{$}} 1409define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) { 1410 %a = fmul <4 x float> %x, %y 1411 ret <4 x float> %a 1412} 1413 1414; CHECK-LABEL: sqrt_v4f32: 1415; NO-SIMD128-NOT: f32x4 1416; SIMD128-NEXT: .functype sqrt_v4f32 (v128) -> (v128){{$}} 1417; SIMD128-NEXT: f32x4.sqrt $push[[R:[0-9]+]]=, $0{{$}} 1418; SIMD128-NEXT: return $pop[[R]]{{$}} 1419declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) 1420define <4 x float> @sqrt_v4f32(<4 x float> %x) { 1421 %a = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) 1422 ret <4 x float> %a 1423} 1424 1425; ============================================================================== 1426; 2 x double 1427; ============================================================================== 1428; CHECK-LABEL: neg_v2f64: 1429; NO-SIMD128-NOT: f64x2 1430; SIMD128-NEXT: .functype neg_v2f64 (v128) -> (v128){{$}} 1431; SIMD128-NEXT: f64x2.neg $push[[R:[0-9]+]]=, $0{{$}} 1432; SIMD128-NEXT: return $pop[[R]]{{$}} 1433define <2 x double> @neg_v2f64(<2 x double> %x) { 1434 ; nsz makes this semantically equivalent to flipping sign bit 1435 %a = fsub nsz <2 x double> <double 0., double 0.>, %x 1436 ret <2 x double> %a 1437} 1438 1439; CHECK-LABEL: abs_v2f64: 1440; NO-SIMD128-NOT: f64x2 1441; SIMD128-NEXT: .functype abs_v2f64 (v128) -> (v128){{$}} 1442; SIMD128-NEXT: f64x2.abs $push[[R:[0-9]+]]=, $0{{$}} 1443; SIMD128-NEXT: return $pop[[R]]{{$}} 1444declare <2 x double> @llvm.fabs.v2f64(<2 x double>) nounwind readnone 1445define <2 x double> @abs_v2f64(<2 x double> %x) { 1446 %a = call <2 x double> @llvm.fabs.v2f64(<2 x double> %x) 1447 ret <2 x double> %a 1448} 1449 1450; CHECK-LABEL: min_unordered_v2f64: 1451; NO-SIMD128-NOT: f64x2 1452; SIMD128-NEXT: .functype min_unordered_v2f64 (v128) -> (v128){{$}} 1453; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 1454; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1455; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1456; SIMD128-NEXT: return $pop[[R]]{{$}} 1457define <2 x double> @min_unordered_v2f64(<2 x double> %x) { 1458 %cmps = fcmp ule <2 x double> %x, <double 5., double 5.> 1459 %a = select <2 x i1> %cmps, <2 x double> %x, 1460 <2 x double> <double 5., double 5.> 1461 ret <2 x double> %a 1462} 1463 1464; CHECK-LABEL: max_unordered_v2f64: 1465; NO-SIMD128-NOT: f64x2 1466; SIMD128-NEXT: .functype max_unordered_v2f64 (v128) -> (v128){{$}} 1467; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 1468; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1469; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1470; SIMD128-NEXT: return $pop[[R]]{{$}} 1471define <2 x double> @max_unordered_v2f64(<2 x double> %x) { 1472 %cmps = fcmp uge <2 x double> %x, <double 5., double 5.> 1473 %a = select <2 x i1> %cmps, <2 x double> %x, 1474 <2 x double> <double 5., double 5.> 1475 ret <2 x double> %a 1476} 1477 1478; CHECK-LABEL: min_ordered_v2f64: 1479; NO-SIMD128-NOT: f64x2 1480; SIMD128-NEXT: .functype min_ordered_v2f64 (v128) -> (v128){{$}} 1481; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 1482; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1483; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1484; SIMD128-NEXT: return $pop[[R]]{{$}} 1485define <2 x double> @min_ordered_v2f64(<2 x double> %x) { 1486 %cmps = fcmp ole <2 x double> <double 5., double 5.>, %x 1487 %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>, 1488 <2 x double> %x 1489 ret <2 x double> %a 1490} 1491 1492; CHECK-LABEL: max_ordered_v2f64: 1493; NO-SIMD128-NOT: f64x2 1494; SIMD128-NEXT: .functype max_ordered_v2f64 (v128) -> (v128){{$}} 1495; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 1496; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] 1497; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} 1498; SIMD128-NEXT: return $pop[[R]]{{$}} 1499define <2 x double> @max_ordered_v2f64(<2 x double> %x) { 1500 %cmps = fcmp oge <2 x double> <double 5., double 5.>, %x 1501 %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>, 1502 <2 x double> %x 1503 ret <2 x double> %a 1504} 1505 1506; CHECK-LABEL: min_intrinsic_v2f64: 1507; NO-SIMD128-NOT: f64x2 1508; SIMD128-NEXT: .functype min_intrinsic_v2f64 (v128, v128) -> (v128){{$}} 1509; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $1{{$}} 1510; SIMD128-NEXT: return $pop[[R]]{{$}} 1511declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>) 1512define <2 x double> @min_intrinsic_v2f64(<2 x double> %x, <2 x double> %y) { 1513 %a = call <2 x double> @llvm.minimum.v2f64(<2 x double> %x, <2 x double> %y) 1514 ret <2 x double> %a 1515} 1516 1517; CHECK-LABEL: max_intrinsic_v2f64: 1518; NO-SIMD128-NOT: f64x2 1519; SIMD128-NEXT: .functype max_intrinsic_v2f64 (v128, v128) -> (v128){{$}} 1520; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $1{{$}} 1521; SIMD128-NEXT: return $pop[[R]]{{$}} 1522declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>) 1523define <2 x double> @max_intrinsic_v2f64(<2 x double> %x, <2 x double> %y) { 1524 %a = call <2 x double> @llvm.maximum.v2f64(<2 x double> %x, <2 x double> %y) 1525 ret <2 x double> %a 1526} 1527 1528; CHECK-LABEL: min_const_intrinsic_v2f64: 1529; NO-SIMD128-NOT: f64x2 1530; SIMD128-NEXT: .functype min_const_intrinsic_v2f64 () -> (v128){{$}} 1531; SIMD128-NEXT: f64.const $push[[L:[0-9]+]]=, 0x1.4p2{{$}} 1532; SIMD128-NEXT: f64x2.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}} 1533; SIMD128-NEXT: return $pop[[R]]{{$}} 1534define <2 x double> @min_const_intrinsic_v2f64() { 1535 %a = call <2 x double> @llvm.minimum.v2f64( 1536 <2 x double> <double 42., double 42.>, 1537 <2 x double> <double 5., double 5.> 1538 ) 1539 ret <2 x double> %a 1540} 1541 1542; CHECK-LABEL: max_const_intrinsic_v2f64: 1543; NO-SIMD128-NOT: f64x2 1544; SIMD128-NEXT: .functype max_const_intrinsic_v2f64 () -> (v128){{$}} 1545; SIMD128-NEXT: f64.const $push[[L:[0-9]+]]=, 0x1.5p5{{$}} 1546; SIMD128-NEXT: f64x2.splat $push[[R:[0-9]+]]=, $pop[[L]]{{$}} 1547; SIMD128-NEXT: return $pop[[R]]{{$}} 1548define <2 x double> @max_const_intrinsic_v2f64() { 1549 %a = call <2 x double> @llvm.maximum.v2f64( 1550 <2 x double> <double 42., double 42.>, 1551 <2 x double> <double 5., double 5.> 1552 ) 1553 ret <2 x double> %a 1554} 1555 1556; CHECK-LABEL: add_v2f64: 1557; NO-SIMD128-NOT: f64x2 1558; SIMD128-NEXT: .functype add_v2f64 (v128, v128) -> (v128){{$}} 1559; SIMD128-NEXT: f64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}} 1560; SIMD128-NEXT: return $pop[[R]]{{$}} 1561define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) { 1562 %a = fadd <2 x double> %x, %y 1563 ret <2 x double> %a 1564} 1565 1566; CHECK-LABEL: sub_v2f64: 1567; NO-SIMD128-NOT: f64x2 1568; SIMD128-NEXT: .functype sub_v2f64 (v128, v128) -> (v128){{$}} 1569; SIMD128-NEXT: f64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}} 1570; SIMD128-NEXT: return $pop[[R]]{{$}} 1571define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) { 1572 %a = fsub <2 x double> %x, %y 1573 ret <2 x double> %a 1574} 1575 1576; CHECK-LABEL: div_v2f64: 1577; NO-SIMD128-NOT: f64x2 1578; SIMD128-NEXT: .functype div_v2f64 (v128, v128) -> (v128){{$}} 1579; SIMD128-NEXT: f64x2.div $push[[R:[0-9]+]]=, $0, $1{{$}} 1580; SIMD128-NEXT: return $pop[[R]]{{$}} 1581define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) { 1582 %a = fdiv <2 x double> %x, %y 1583 ret <2 x double> %a 1584} 1585 1586; CHECK-LABEL: mul_v2f64: 1587; NO-SIMD128-NOT: f64x2 1588; SIMD128-NEXT: .functype mul_v2f64 (v128, v128) -> (v128){{$}} 1589; SIMD128-NEXT: f64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}} 1590; SIMD128-NEXT: return $pop[[R]]{{$}} 1591define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) { 1592 %a = fmul <2 x double> %x, %y 1593 ret <2 x double> %a 1594} 1595 1596; CHECK-LABEL: sqrt_v2f64: 1597; NO-SIMD128-NOT: f64x2 1598; SIMD128-NEXT: .functype sqrt_v2f64 (v128) -> (v128){{$}} 1599; SIMD128-NEXT: f64x2.sqrt $push[[R:[0-9]+]]=, $0{{$}} 1600; SIMD128-NEXT: return $pop[[R]]{{$}} 1601declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %x) 1602define <2 x double> @sqrt_v2f64(<2 x double> %x) { 1603 %a = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %x) 1604 ret <2 x double> %a 1605} 1606