1; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
2; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
3; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
4; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
5; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
6; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
7
8; Test that basic SIMD128 arithmetic operations assemble as expected.
9
10target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
11target triple = "wasm32-unknown-unknown"
12
13; ==============================================================================
14; 16 x i8
15; ==============================================================================
16; CHECK-LABEL: add_v16i8
17; NO-SIMD128-NOT: i8x16
18; SIMD128: .param v128, v128{{$}}
19; SIMD128: .result v128{{$}}
20; SIMD128: i8x16.add $push0=, $0, $1 # encoding: [0xfd,0x18]{{$}}
21; SIMD128: return $pop0 #
22define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) {
23  %a = add <16 x i8> %x, %y
24  ret <16 x i8> %a
25}
26
27; CHECK-LABEL: sub_v16i8
28; NO-SIMD128-NOT: i8x16
29; SIMD128: .param v128, v128{{$}}
30; SIMD128: .result v128{{$}}
31; SIMD128: i8x16.sub $push0=, $0, $1 # encoding: [0xfd,0x1c]{{$}}
32; SIMD128: return $pop0 #
33define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) {
34  %a = sub <16 x i8> %x, %y
35  ret <16 x i8> %a
36}
37
38; CHECK-LABEL: mul_v16i8
39; NO-SIMD128-NOT: i8x16
40; SIMD128: .param v128, v128{{$}}
41; SIMD128: .result v128{{$}}
42; SIMD128: i8x16.mul $push0=, $0, $1 # encoding: [0xfd,0x20]{{$}}
43; SIMD128: return $pop0 #
44define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
45  %a = mul <16 x i8> %x, %y
46  ret <16 x i8> %a
47}
48
49; ==============================================================================
50; 8 x i16
51; ==============================================================================
52; CHECK-LABEL: add_v8i16
53; NO-SIMD128-NOT: i16x8
54; SIMD128: .param v128, v128{{$}}
55; SIMD128: .result v128{{$}}
56; SIMD128: i16x8.add $push0=, $0, $1 # encoding: [0xfd,0x19]{{$}}
57; SIMD128: return $pop0 #
58define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) {
59  %a = add <8 x i16> %x, %y
60  ret <8 x i16> %a
61}
62
63; CHECK-LABEL: sub_v8i16
64; NO-SIMD128-NOT: i16x8
65; SIMD128: .param v128, v128{{$}}
66; SIMD128: .result v128{{$}}
67; SIMD128: i16x8.sub $push0=, $0, $1 # encoding: [0xfd,0x1d]{{$}}
68; SIMD128: return $pop0 #
69define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) {
70  %a = sub <8 x i16> %x, %y
71  ret <8 x i16> %a
72}
73
74; CHECK-LABEL: mul_v8i16
75; NO-SIMD128-NOT: i16x8
76; SIMD128: .param v128, v128{{$}}
77; SIMD128: .result v128{{$}}
78; SIMD128: i16x8.mul $push0=, $0, $1 # encoding: [0xfd,0x21]{{$}}
79; SIMD128: return $pop0 #
80define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) {
81  %a = mul <8 x i16> %x, %y
82  ret <8 x i16> %a
83}
84
85; ==============================================================================
86; 4 x i32
87; ==============================================================================
88; CHECK-LABEL: add_v4i32
89; NO-SIMD128-NOT: i32x4
90; SIMD128: .param v128, v128{{$}}
91; SIMD128: .result v128{{$}}
92; SIMD128: i32x4.add $push0=, $0, $1 # encoding: [0xfd,0x1a]{{$}}
93; SIMD128: return $pop0 #
94define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) {
95  %a = add <4 x i32> %x, %y
96  ret <4 x i32> %a
97}
98
99; CHECK-LABEL: sub_v4i32
100; NO-SIMD128-NOT: i32x4
101; SIMD128: .param v128, v128{{$}}
102; SIMD128: .result v128{{$}}
103; SIMD128: i32x4.sub $push0=, $0, $1 # encoding: [0xfd,0x1e]{{$}}
104; SIMD128: return $pop0 #
105define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) {
106  %a = sub <4 x i32> %x, %y
107  ret <4 x i32> %a
108}
109
110; CHECK-LABEL: mul_v4i32
111; NO-SIMD128-NOT: i32x4
112; SIMD128: .param v128, v128{{$}}
113; SIMD128: .result v128{{$}}
114; SIMD128: i32x4.mul $push0=, $0, $1 # encoding: [0xfd,0x22]{{$}}
115; SIMD128: return $pop0 #
116define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
117  %a = mul <4 x i32> %x, %y
118  ret <4 x i32> %a
119}
120
121; ==============================================================================
122; 2 x i64
123; ==============================================================================
124; CHECK-LABEL: add_v2i64
125; NO-SIMD128-NOT: i64x2
126; SIMD128-VM-NOT: i64x2
127; SIMD128: .param v128, v128{{$}}
128; SIMD128: .result v128{{$}}
129; SIMD128: i64x2.add $push0=, $0, $1 # encoding: [0xfd,0x1b]{{$}}
130; SIMD128: return $pop0 #
131define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) {
132  %a = add <2 x i64> %x, %y
133  ret <2 x i64> %a
134}
135
136; CHECK-LABEL: sub_v2i64
137; NO-SIMD128-NOT: i64x2
138; SIMD128-VM-NOT: i64x2
139; SIMD128: .param v128, v128{{$}}
140; SIMD128: .result v128{{$}}
141; SIMD128: i64x2.sub $push0=, $0, $1 # encoding: [0xfd,0x1f]{{$}}
142; SIMD128: return $pop0 #
143define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
144  %a = sub <2 x i64> %x, %y
145  ret <2 x i64> %a
146}
147
148; v2i64.mul is not in spec
149; CHECK-LABEL: mul_v2i64
150; NO-SIMD128-NOT: i64x2
151; SIMD128-VM-NOT: i64x2
152; SIMD128-NOT: i64x2.mul
153; SIMD128: i64x2.extract_lane
154; SIMD128: i64.mul
155define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
156  %a = mul <2 x i64> %x, %y
157  ret <2 x i64> %a
158}
159
160; ==============================================================================
161; 4 x float
162; ==============================================================================
163; CHECK-LABEL: add_v4f32
164; NO-SIMD128-NOT: f32x4
165; SIMD128: .param v128, v128{{$}}
166; SIMD128: .result v128{{$}}
167; SIMD128: f32x4.add $push0=, $0, $1 # encoding: [0xfd,0x7a]{{$}}
168; SIMD128: return $pop0 #
169define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
170  %a = fadd <4 x float> %x, %y
171  ret <4 x float> %a
172}
173
174; CHECK-LABEL: sub_v4f32
175; NO-SIMD128-NOT: f32x4
176; SIMD128: .param v128, v128{{$}}
177; SIMD128: .result v128{{$}}
178; SIMD128: f32x4.sub $push0=, $0, $1 # encoding: [0xfd,0x7c]{{$}}
179; SIMD128: return $pop0 #
180define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) {
181  %a = fsub <4 x float> %x, %y
182  ret <4 x float> %a
183}
184
185; CHECK-LABEL: div_v4f32
186; NO-SIMD128-NOT: f32x4
187; SIMD128: .param v128, v128{{$}}
188; SIMD128: .result v128{{$}}
189; SIMD128: f32x4.div $push0=, $0, $1 # encoding: [0xfd,0x7e]{{$}}
190; SIMD128: return $pop0 #
191define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) {
192  %a = fdiv <4 x float> %x, %y
193  ret <4 x float> %a
194}
195
196; CHECK-LABEL: mul_v4f32
197; NO-SIMD128-NOT: f32x4
198; SIMD128: .param v128, v128{{$}}
199; SIMD128: .result v128{{$}}
200; SIMD128: f32x4.mul $push0=, $0, $1 # encoding: [0xfd,0x80]{{$}}
201; SIMD128: return $pop0 #
202define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
203  %a = fmul <4 x float> %x, %y
204  ret <4 x float> %a
205}
206
207; ==============================================================================
208; 2 x double
209; ==============================================================================
210; CHECK-LABEL: add_v2f64
211; NO-SIMD128-NOT: f64x2
212; SIMD129-VM-NOT: f62x2
213; SIMD128: .param v128, v128{{$}}
214; SIMD128: .result v128{{$}}
215; SIMD128: f64x2.add $push0=, $0, $1 # encoding: [0xfd,0x7b]{{$}}
216; SIMD128: return $pop0 #
217define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
218  %a = fadd <2 x double> %x, %y
219  ret <2 x double> %a
220}
221
222; CHECK-LABEL: sub_v2f64
223; NO-SIMD128-NOT: f64x2
224; SIMD129-VM-NOT: f62x2
225; SIMD128: .param v128, v128{{$}}
226; SIMD128: .result v128{{$}}
227; SIMD128: f64x2.sub $push0=, $0, $1 # encoding: [0xfd,0x7d]{{$}}
228; SIMD128: return $pop0 #
229define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) {
230  %a = fsub <2 x double> %x, %y
231  ret <2 x double> %a
232}
233
234; CHECK-LABEL: div_v2f64
235; NO-SIMD128-NOT: f64x2
236; SIMD129-VM-NOT: f62x2
237; SIMD128: .param v128, v128{{$}}
238; SIMD128: .result v128{{$}}
239; SIMD128: f64x2.div $push0=, $0, $1 # encoding: [0xfd,0x7f]{{$}}
240; SIMD128: return $pop0 #
241define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) {
242  %a = fdiv <2 x double> %x, %y
243  ret <2 x double> %a
244}
245
246; CHECK-LABEL: mul_v2f64
247; NO-SIMD128-NOT: f64x2
248; SIMD129-VM-NOT: f62x2
249; SIMD128: .param v128, v128{{$}}
250; SIMD128: .result v128{{$}}
251; SIMD128: f64x2.mul $push0=, $0, $1 # encoding: [0xfd,0x81]{{$}}
252; SIMD128: return $pop0 #
253define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) {
254  %a = fmul <2 x double> %x, %y
255  ret <2 x double> %a
256}
257