1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3
4declare <256 x float> @llvm.vp.fsub.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
5
6define fastcc <256 x float> @test_vp_fsub_v256f32_vv(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
7; CHECK-LABEL: test_vp_fsub_v256f32_vv:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    and %s0, %s0, (32)0
10; CHECK-NEXT:    lvl %s0
11; CHECK-NEXT:    pvfsub.up %v0, %v0, %v1, %vm1
12; CHECK-NEXT:    b.l.t (, %s10)
13  %r0 = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
14  ret <256 x float> %r0
15}
16
17define fastcc <256 x float> @test_vp_fsub_v256f32_rv(float %s0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
18; CHECK-LABEL: test_vp_fsub_v256f32_rv:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    and %s1, %s1, (32)0
21; CHECK-NEXT:    lvl %s1
22; CHECK-NEXT:    pvfsub.up %v0, %s0, %v0, %vm1
23; CHECK-NEXT:    b.l.t (, %s10)
24  %xins = insertelement <256 x float> undef, float %s0, i32 0
25  %i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
26  %r0 = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
27  ret <256 x float> %r0
28}
29
30define fastcc <256 x float> @test_vp_fsub_v256f32_vr(<256 x float> %i0, float %s1, <256 x i1> %m, i32 %n) {
31; CHECK-LABEL: test_vp_fsub_v256f32_vr:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    and %s1, %s1, (32)0
34; CHECK-NEXT:    lea %s2, 256
35; CHECK-NEXT:    lvl %s2
36; CHECK-NEXT:    vbrd %v1, %s0
37; CHECK-NEXT:    lvl %s1
38; CHECK-NEXT:    pvfsub.up %v0, %v0, %v1, %vm1
39; CHECK-NEXT:    b.l.t (, %s10)
40  %yins = insertelement <256 x float> undef, float %s1, i32 0
41  %i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
42  %r0 = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
43  ret <256 x float> %r0
44}
45
46
47declare <256 x double> @llvm.vp.fsub.v256f64(<256 x double>, <256 x double>, <256 x i1>, i32)
48
49define fastcc <256 x double> @test_vp_fsub_v256f64_vv(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
50; CHECK-LABEL: test_vp_fsub_v256f64_vv:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    and %s0, %s0, (32)0
53; CHECK-NEXT:    lvl %s0
54; CHECK-NEXT:    vfsub.d %v0, %v0, %v1, %vm1
55; CHECK-NEXT:    b.l.t (, %s10)
56  %r0 = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
57  ret <256 x double> %r0
58}
59
60define fastcc <256 x double> @test_vp_fsub_v256f64_rv(double %s0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
61; CHECK-LABEL: test_vp_fsub_v256f64_rv:
62; CHECK:       # %bb.0:
63; CHECK-NEXT:    and %s1, %s1, (32)0
64; CHECK-NEXT:    lvl %s1
65; CHECK-NEXT:    vfsub.d %v0, %s0, %v0, %vm1
66; CHECK-NEXT:    b.l.t (, %s10)
67  %xins = insertelement <256 x double> undef, double %s0, i32 0
68  %i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer
69  %r0 = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
70  ret <256 x double> %r0
71}
72
73define fastcc <256 x double> @test_vp_fsub_v256f64_vr(<256 x double> %i0, double %s1, <256 x i1> %m, i32 %n) {
74; CHECK-LABEL: test_vp_fsub_v256f64_vr:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    and %s1, %s1, (32)0
77; CHECK-NEXT:    lea %s2, 256
78; CHECK-NEXT:    lvl %s2
79; CHECK-NEXT:    vbrd %v1, %s0
80; CHECK-NEXT:    lvl %s1
81; CHECK-NEXT:    vfsub.d %v0, %v0, %v1, %vm1
82; CHECK-NEXT:    b.l.t (, %s10)
83  %yins = insertelement <256 x double> undef, double %s1, i32 0
84  %i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer
85  %r0 = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
86  ret <256 x double> %r0
87}
88