1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV64I
6
7define i1 @and_icmp_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
8; RV32I-LABEL: and_icmp_eq:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    xor a0, a0, a1
11; RV32I-NEXT:    xor a1, a2, a3
12; RV32I-NEXT:    or a0, a0, a1
13; RV32I-NEXT:    seqz a0, a0
14; RV32I-NEXT:    ret
15;
16; RV64I-LABEL: and_icmp_eq:
17; RV64I:       # %bb.0:
18; RV64I-NEXT:    xor a0, a0, a1
19; RV64I-NEXT:    xor a1, a2, a3
20; RV64I-NEXT:    or a0, a0, a1
21; RV64I-NEXT:    sext.w a0, a0
22; RV64I-NEXT:    seqz a0, a0
23; RV64I-NEXT:    ret
24  %cmp1 = icmp eq i32 %a, %b
25  %cmp2 = icmp eq i32 %c, %d
26  %and = and i1 %cmp1, %cmp2
27  ret i1 %and
28}
29
30define i1 @or_icmp_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
31; RV32I-LABEL: or_icmp_ne:
32; RV32I:       # %bb.0:
33; RV32I-NEXT:    xor a0, a0, a1
34; RV32I-NEXT:    xor a1, a2, a3
35; RV32I-NEXT:    or a0, a0, a1
36; RV32I-NEXT:    snez a0, a0
37; RV32I-NEXT:    ret
38;
39; RV64I-LABEL: or_icmp_ne:
40; RV64I:       # %bb.0:
41; RV64I-NEXT:    xor a0, a0, a1
42; RV64I-NEXT:    xor a1, a2, a3
43; RV64I-NEXT:    or a0, a0, a1
44; RV64I-NEXT:    sext.w a0, a0
45; RV64I-NEXT:    snez a0, a0
46; RV64I-NEXT:    ret
47  %cmp1 = icmp ne i32 %a, %b
48  %cmp2 = icmp ne i32 %c, %d
49  %or = or i1 %cmp1, %cmp2
50  ret i1 %or
51}
52
53define i1 @or_icmps_const_1bit_diff(i64 %x) nounwind {
54; RV32I-LABEL: or_icmps_const_1bit_diff:
55; RV32I:       # %bb.0:
56; RV32I-NEXT:    addi a2, a0, -13
57; RV32I-NEXT:    sltu a0, a2, a0
58; RV32I-NEXT:    add a0, a1, a0
59; RV32I-NEXT:    addi a0, a0, -1
60; RV32I-NEXT:    andi a1, a2, -5
61; RV32I-NEXT:    or a0, a1, a0
62; RV32I-NEXT:    seqz a0, a0
63; RV32I-NEXT:    ret
64;
65; RV64I-LABEL: or_icmps_const_1bit_diff:
66; RV64I:       # %bb.0:
67; RV64I-NEXT:    addi a0, a0, -13
68; RV64I-NEXT:    andi a0, a0, -5
69; RV64I-NEXT:    seqz a0, a0
70; RV64I-NEXT:    ret
71  %a = icmp eq i64 %x, 17
72  %b = icmp eq i64 %x, 13
73  %r = or i1 %a, %b
74  ret i1 %r
75}
76
77define i1 @and_icmps_const_1bit_diff(i32 %x) nounwind {
78; RV32I-LABEL: and_icmps_const_1bit_diff:
79; RV32I:       # %bb.0:
80; RV32I-NEXT:    addi a0, a0, -44
81; RV32I-NEXT:    andi a0, a0, -17
82; RV32I-NEXT:    snez a0, a0
83; RV32I-NEXT:    ret
84;
85; RV64I-LABEL: and_icmps_const_1bit_diff:
86; RV64I:       # %bb.0:
87; RV64I-NEXT:    addiw a0, a0, -44
88; RV64I-NEXT:    andi a0, a0, -17
89; RV64I-NEXT:    snez a0, a0
90; RV64I-NEXT:    ret
91  %a = icmp ne i32 %x, 44
92  %b = icmp ne i32 %x, 60
93  %r = and i1 %a, %b
94  ret i1 %r
95}
96
97define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {
98; RV32I-LABEL: and_icmps_const_not1bit_diff:
99; RV32I:       # %bb.0:
100; RV32I-NEXT:    addi a1, a0, -44
101; RV32I-NEXT:    snez a1, a1
102; RV32I-NEXT:    addi a0, a0, -92
103; RV32I-NEXT:    snez a0, a0
104; RV32I-NEXT:    and a0, a1, a0
105; RV32I-NEXT:    ret
106;
107; RV64I-LABEL: and_icmps_const_not1bit_diff:
108; RV64I:       # %bb.0:
109; RV64I-NEXT:    sext.w a0, a0
110; RV64I-NEXT:    addi a1, a0, -44
111; RV64I-NEXT:    snez a1, a1
112; RV64I-NEXT:    addi a0, a0, -92
113; RV64I-NEXT:    snez a0, a0
114; RV64I-NEXT:    and a0, a1, a0
115; RV64I-NEXT:    ret
116  %a = icmp ne i32 %x, 44
117  %b = icmp ne i32 %x, 92
118  %r = and i1 %a, %b
119  ret i1 %r
120}
121