1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV32IF %s
6; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
7; RUN:   | FileCheck -check-prefix=RV32IBT %s
8; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
9; RUN:   | FileCheck -check-prefix=RV32IFBT %s
10; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
11; RUN:   | FileCheck -check-prefix=RV64I %s
12; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \
13; RUN:   | FileCheck -check-prefix=RV64IFD %s
14; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
15; RUN:   | FileCheck -check-prefix=RV64IBT %s
16; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
17; RUN:   | FileCheck -check-prefix=RV64IFDBT %s
18
19;; This tests how good we are at materialising constants using `select`. The aim
20;; is that we do so without a branch if possible (at the moment our lowering of
21;; select always introduces a branch).
22;;
23;; Currently the hook `convertSelectOfConstantsToMath` only is useful when the
24;; constants are either 1 away from each other, or one is a power of two and
25;; the other is zero.
26
27define signext i32 @select_const_int_easy(i1 zeroext %a) nounwind {
28; RV32I-LABEL: select_const_int_easy:
29; RV32I:       # %bb.0:
30; RV32I-NEXT:    ret
31;
32; RV32IF-LABEL: select_const_int_easy:
33; RV32IF:       # %bb.0:
34; RV32IF-NEXT:    ret
35;
36; RV32IBT-LABEL: select_const_int_easy:
37; RV32IBT:       # %bb.0:
38; RV32IBT-NEXT:    ret
39;
40; RV32IFBT-LABEL: select_const_int_easy:
41; RV32IFBT:       # %bb.0:
42; RV32IFBT-NEXT:    ret
43;
44; RV64I-LABEL: select_const_int_easy:
45; RV64I:       # %bb.0:
46; RV64I-NEXT:    ret
47;
48; RV64IFD-LABEL: select_const_int_easy:
49; RV64IFD:       # %bb.0:
50; RV64IFD-NEXT:    ret
51;
52; RV64IBT-LABEL: select_const_int_easy:
53; RV64IBT:       # %bb.0:
54; RV64IBT-NEXT:    ret
55;
56; RV64IFDBT-LABEL: select_const_int_easy:
57; RV64IFDBT:       # %bb.0:
58; RV64IFDBT-NEXT:    ret
59  %1 = select i1 %a, i32 1, i32 0
60  ret i32 %1
61}
62
63define signext i32 @select_const_int_one_away(i1 zeroext %a) nounwind {
64; RV32I-LABEL: select_const_int_one_away:
65; RV32I:       # %bb.0:
66; RV32I-NEXT:    li a1, 4
67; RV32I-NEXT:    sub a0, a1, a0
68; RV32I-NEXT:    ret
69;
70; RV32IF-LABEL: select_const_int_one_away:
71; RV32IF:       # %bb.0:
72; RV32IF-NEXT:    li a1, 4
73; RV32IF-NEXT:    sub a0, a1, a0
74; RV32IF-NEXT:    ret
75;
76; RV32IBT-LABEL: select_const_int_one_away:
77; RV32IBT:       # %bb.0:
78; RV32IBT-NEXT:    li a1, 4
79; RV32IBT-NEXT:    sub a0, a1, a0
80; RV32IBT-NEXT:    ret
81;
82; RV32IFBT-LABEL: select_const_int_one_away:
83; RV32IFBT:       # %bb.0:
84; RV32IFBT-NEXT:    li a1, 4
85; RV32IFBT-NEXT:    sub a0, a1, a0
86; RV32IFBT-NEXT:    ret
87;
88; RV64I-LABEL: select_const_int_one_away:
89; RV64I:       # %bb.0:
90; RV64I-NEXT:    li a1, 4
91; RV64I-NEXT:    sub a0, a1, a0
92; RV64I-NEXT:    ret
93;
94; RV64IFD-LABEL: select_const_int_one_away:
95; RV64IFD:       # %bb.0:
96; RV64IFD-NEXT:    li a1, 4
97; RV64IFD-NEXT:    sub a0, a1, a0
98; RV64IFD-NEXT:    ret
99;
100; RV64IBT-LABEL: select_const_int_one_away:
101; RV64IBT:       # %bb.0:
102; RV64IBT-NEXT:    li a1, 4
103; RV64IBT-NEXT:    sub a0, a1, a0
104; RV64IBT-NEXT:    ret
105;
106; RV64IFDBT-LABEL: select_const_int_one_away:
107; RV64IFDBT:       # %bb.0:
108; RV64IFDBT-NEXT:    li a1, 4
109; RV64IFDBT-NEXT:    sub a0, a1, a0
110; RV64IFDBT-NEXT:    ret
111  %1 = select i1 %a, i32 3, i32 4
112  ret i32 %1
113}
114
115define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {
116; RV32I-LABEL: select_const_int_pow2_zero:
117; RV32I:       # %bb.0:
118; RV32I-NEXT:    slli a0, a0, 2
119; RV32I-NEXT:    ret
120;
121; RV32IF-LABEL: select_const_int_pow2_zero:
122; RV32IF:       # %bb.0:
123; RV32IF-NEXT:    slli a0, a0, 2
124; RV32IF-NEXT:    ret
125;
126; RV32IBT-LABEL: select_const_int_pow2_zero:
127; RV32IBT:       # %bb.0:
128; RV32IBT-NEXT:    slli a0, a0, 2
129; RV32IBT-NEXT:    ret
130;
131; RV32IFBT-LABEL: select_const_int_pow2_zero:
132; RV32IFBT:       # %bb.0:
133; RV32IFBT-NEXT:    slli a0, a0, 2
134; RV32IFBT-NEXT:    ret
135;
136; RV64I-LABEL: select_const_int_pow2_zero:
137; RV64I:       # %bb.0:
138; RV64I-NEXT:    slli a0, a0, 2
139; RV64I-NEXT:    ret
140;
141; RV64IFD-LABEL: select_const_int_pow2_zero:
142; RV64IFD:       # %bb.0:
143; RV64IFD-NEXT:    slli a0, a0, 2
144; RV64IFD-NEXT:    ret
145;
146; RV64IBT-LABEL: select_const_int_pow2_zero:
147; RV64IBT:       # %bb.0:
148; RV64IBT-NEXT:    slli a0, a0, 2
149; RV64IBT-NEXT:    ret
150;
151; RV64IFDBT-LABEL: select_const_int_pow2_zero:
152; RV64IFDBT:       # %bb.0:
153; RV64IFDBT-NEXT:    slli a0, a0, 2
154; RV64IFDBT-NEXT:    ret
155  %1 = select i1 %a, i32 4, i32 0
156  ret i32 %1
157}
158
159define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
160; RV32I-LABEL: select_const_int_harder:
161; RV32I:       # %bb.0:
162; RV32I-NEXT:    mv a1, a0
163; RV32I-NEXT:    li a0, 6
164; RV32I-NEXT:    bnez a1, .LBB3_2
165; RV32I-NEXT:  # %bb.1:
166; RV32I-NEXT:    li a0, 38
167; RV32I-NEXT:  .LBB3_2:
168; RV32I-NEXT:    ret
169;
170; RV32IF-LABEL: select_const_int_harder:
171; RV32IF:       # %bb.0:
172; RV32IF-NEXT:    mv a1, a0
173; RV32IF-NEXT:    li a0, 6
174; RV32IF-NEXT:    bnez a1, .LBB3_2
175; RV32IF-NEXT:  # %bb.1:
176; RV32IF-NEXT:    li a0, 38
177; RV32IF-NEXT:  .LBB3_2:
178; RV32IF-NEXT:    ret
179;
180; RV32IBT-LABEL: select_const_int_harder:
181; RV32IBT:       # %bb.0:
182; RV32IBT-NEXT:    li a1, 38
183; RV32IBT-NEXT:    li a2, 6
184; RV32IBT-NEXT:    cmov a0, a0, a2, a1
185; RV32IBT-NEXT:    ret
186;
187; RV32IFBT-LABEL: select_const_int_harder:
188; RV32IFBT:       # %bb.0:
189; RV32IFBT-NEXT:    li a1, 38
190; RV32IFBT-NEXT:    li a2, 6
191; RV32IFBT-NEXT:    cmov a0, a0, a2, a1
192; RV32IFBT-NEXT:    ret
193;
194; RV64I-LABEL: select_const_int_harder:
195; RV64I:       # %bb.0:
196; RV64I-NEXT:    mv a1, a0
197; RV64I-NEXT:    li a0, 6
198; RV64I-NEXT:    bnez a1, .LBB3_2
199; RV64I-NEXT:  # %bb.1:
200; RV64I-NEXT:    li a0, 38
201; RV64I-NEXT:  .LBB3_2:
202; RV64I-NEXT:    ret
203;
204; RV64IFD-LABEL: select_const_int_harder:
205; RV64IFD:       # %bb.0:
206; RV64IFD-NEXT:    mv a1, a0
207; RV64IFD-NEXT:    li a0, 6
208; RV64IFD-NEXT:    bnez a1, .LBB3_2
209; RV64IFD-NEXT:  # %bb.1:
210; RV64IFD-NEXT:    li a0, 38
211; RV64IFD-NEXT:  .LBB3_2:
212; RV64IFD-NEXT:    ret
213;
214; RV64IBT-LABEL: select_const_int_harder:
215; RV64IBT:       # %bb.0:
216; RV64IBT-NEXT:    li a1, 38
217; RV64IBT-NEXT:    li a2, 6
218; RV64IBT-NEXT:    cmov a0, a0, a2, a1
219; RV64IBT-NEXT:    ret
220;
221; RV64IFDBT-LABEL: select_const_int_harder:
222; RV64IFDBT:       # %bb.0:
223; RV64IFDBT-NEXT:    li a1, 38
224; RV64IFDBT-NEXT:    li a2, 6
225; RV64IFDBT-NEXT:    cmov a0, a0, a2, a1
226; RV64IFDBT-NEXT:    ret
227  %1 = select i1 %a, i32 6, i32 38
228  ret i32 %1
229}
230
231define float @select_const_fp(i1 zeroext %a) nounwind {
232; RV32I-LABEL: select_const_fp:
233; RV32I:       # %bb.0:
234; RV32I-NEXT:    mv a1, a0
235; RV32I-NEXT:    lui a0, 263168
236; RV32I-NEXT:    bnez a1, .LBB4_2
237; RV32I-NEXT:  # %bb.1:
238; RV32I-NEXT:    lui a0, 264192
239; RV32I-NEXT:  .LBB4_2:
240; RV32I-NEXT:    ret
241;
242; RV32IF-LABEL: select_const_fp:
243; RV32IF:       # %bb.0:
244; RV32IF-NEXT:    bnez a0, .LBB4_2
245; RV32IF-NEXT:  # %bb.1:
246; RV32IF-NEXT:    lui a0, %hi(.LCPI4_0)
247; RV32IF-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
248; RV32IF-NEXT:    fmv.x.w a0, ft0
249; RV32IF-NEXT:    ret
250; RV32IF-NEXT:  .LBB4_2:
251; RV32IF-NEXT:    lui a0, %hi(.LCPI4_1)
252; RV32IF-NEXT:    flw ft0, %lo(.LCPI4_1)(a0)
253; RV32IF-NEXT:    fmv.x.w a0, ft0
254; RV32IF-NEXT:    ret
255;
256; RV32IBT-LABEL: select_const_fp:
257; RV32IBT:       # %bb.0:
258; RV32IBT-NEXT:    lui a1, 264192
259; RV32IBT-NEXT:    lui a2, 263168
260; RV32IBT-NEXT:    cmov a0, a0, a2, a1
261; RV32IBT-NEXT:    ret
262;
263; RV32IFBT-LABEL: select_const_fp:
264; RV32IFBT:       # %bb.0:
265; RV32IFBT-NEXT:    bnez a0, .LBB4_2
266; RV32IFBT-NEXT:  # %bb.1:
267; RV32IFBT-NEXT:    lui a0, %hi(.LCPI4_0)
268; RV32IFBT-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
269; RV32IFBT-NEXT:    fmv.x.w a0, ft0
270; RV32IFBT-NEXT:    ret
271; RV32IFBT-NEXT:  .LBB4_2:
272; RV32IFBT-NEXT:    lui a0, %hi(.LCPI4_1)
273; RV32IFBT-NEXT:    flw ft0, %lo(.LCPI4_1)(a0)
274; RV32IFBT-NEXT:    fmv.x.w a0, ft0
275; RV32IFBT-NEXT:    ret
276;
277; RV64I-LABEL: select_const_fp:
278; RV64I:       # %bb.0:
279; RV64I-NEXT:    mv a1, a0
280; RV64I-NEXT:    lui a0, 263168
281; RV64I-NEXT:    bnez a1, .LBB4_2
282; RV64I-NEXT:  # %bb.1:
283; RV64I-NEXT:    lui a0, 264192
284; RV64I-NEXT:  .LBB4_2:
285; RV64I-NEXT:    ret
286;
287; RV64IFD-LABEL: select_const_fp:
288; RV64IFD:       # %bb.0:
289; RV64IFD-NEXT:    bnez a0, .LBB4_2
290; RV64IFD-NEXT:  # %bb.1:
291; RV64IFD-NEXT:    lui a0, %hi(.LCPI4_0)
292; RV64IFD-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
293; RV64IFD-NEXT:    fmv.x.w a0, ft0
294; RV64IFD-NEXT:    ret
295; RV64IFD-NEXT:  .LBB4_2:
296; RV64IFD-NEXT:    lui a0, %hi(.LCPI4_1)
297; RV64IFD-NEXT:    flw ft0, %lo(.LCPI4_1)(a0)
298; RV64IFD-NEXT:    fmv.x.w a0, ft0
299; RV64IFD-NEXT:    ret
300;
301; RV64IBT-LABEL: select_const_fp:
302; RV64IBT:       # %bb.0:
303; RV64IBT-NEXT:    lui a1, 264192
304; RV64IBT-NEXT:    lui a2, 263168
305; RV64IBT-NEXT:    cmov a0, a0, a2, a1
306; RV64IBT-NEXT:    ret
307;
308; RV64IFDBT-LABEL: select_const_fp:
309; RV64IFDBT:       # %bb.0:
310; RV64IFDBT-NEXT:    bnez a0, .LBB4_2
311; RV64IFDBT-NEXT:  # %bb.1:
312; RV64IFDBT-NEXT:    lui a0, %hi(.LCPI4_0)
313; RV64IFDBT-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
314; RV64IFDBT-NEXT:    fmv.x.w a0, ft0
315; RV64IFDBT-NEXT:    ret
316; RV64IFDBT-NEXT:  .LBB4_2:
317; RV64IFDBT-NEXT:    lui a0, %hi(.LCPI4_1)
318; RV64IFDBT-NEXT:    flw ft0, %lo(.LCPI4_1)(a0)
319; RV64IFDBT-NEXT:    fmv.x.w a0, ft0
320; RV64IFDBT-NEXT:    ret
321  %1 = select i1 %a, float 3.0, float 4.0
322  ret float %1
323}
324
325define signext i32 @select_eq_zero_negone(i32 signext %a, i32 signext %b) nounwind {
326; RV32I-LABEL: select_eq_zero_negone:
327; RV32I:       # %bb.0:
328; RV32I-NEXT:    xor a0, a0, a1
329; RV32I-NEXT:    seqz a0, a0
330; RV32I-NEXT:    neg a0, a0
331; RV32I-NEXT:    ret
332;
333; RV32IF-LABEL: select_eq_zero_negone:
334; RV32IF:       # %bb.0:
335; RV32IF-NEXT:    xor a0, a0, a1
336; RV32IF-NEXT:    seqz a0, a0
337; RV32IF-NEXT:    neg a0, a0
338; RV32IF-NEXT:    ret
339;
340; RV32IBT-LABEL: select_eq_zero_negone:
341; RV32IBT:       # %bb.0:
342; RV32IBT-NEXT:    xor a0, a0, a1
343; RV32IBT-NEXT:    seqz a0, a0
344; RV32IBT-NEXT:    neg a0, a0
345; RV32IBT-NEXT:    ret
346;
347; RV32IFBT-LABEL: select_eq_zero_negone:
348; RV32IFBT:       # %bb.0:
349; RV32IFBT-NEXT:    xor a0, a0, a1
350; RV32IFBT-NEXT:    seqz a0, a0
351; RV32IFBT-NEXT:    neg a0, a0
352; RV32IFBT-NEXT:    ret
353;
354; RV64I-LABEL: select_eq_zero_negone:
355; RV64I:       # %bb.0:
356; RV64I-NEXT:    xor a0, a0, a1
357; RV64I-NEXT:    seqz a0, a0
358; RV64I-NEXT:    neg a0, a0
359; RV64I-NEXT:    ret
360;
361; RV64IFD-LABEL: select_eq_zero_negone:
362; RV64IFD:       # %bb.0:
363; RV64IFD-NEXT:    xor a0, a0, a1
364; RV64IFD-NEXT:    seqz a0, a0
365; RV64IFD-NEXT:    neg a0, a0
366; RV64IFD-NEXT:    ret
367;
368; RV64IBT-LABEL: select_eq_zero_negone:
369; RV64IBT:       # %bb.0:
370; RV64IBT-NEXT:    xor a0, a0, a1
371; RV64IBT-NEXT:    seqz a0, a0
372; RV64IBT-NEXT:    neg a0, a0
373; RV64IBT-NEXT:    ret
374;
375; RV64IFDBT-LABEL: select_eq_zero_negone:
376; RV64IFDBT:       # %bb.0:
377; RV64IFDBT-NEXT:    xor a0, a0, a1
378; RV64IFDBT-NEXT:    seqz a0, a0
379; RV64IFDBT-NEXT:    neg a0, a0
380; RV64IFDBT-NEXT:    ret
381  %1 = icmp eq i32 %a, %b
382  %2 = select i1 %1, i32 -1, i32 0
383  ret i32 %2
384}
385
386define signext i32 @select_ne_zero_negone(i32 signext %a, i32 signext %b) nounwind {
387; RV32I-LABEL: select_ne_zero_negone:
388; RV32I:       # %bb.0:
389; RV32I-NEXT:    xor a0, a0, a1
390; RV32I-NEXT:    snez a0, a0
391; RV32I-NEXT:    neg a0, a0
392; RV32I-NEXT:    ret
393;
394; RV32IF-LABEL: select_ne_zero_negone:
395; RV32IF:       # %bb.0:
396; RV32IF-NEXT:    xor a0, a0, a1
397; RV32IF-NEXT:    snez a0, a0
398; RV32IF-NEXT:    neg a0, a0
399; RV32IF-NEXT:    ret
400;
401; RV32IBT-LABEL: select_ne_zero_negone:
402; RV32IBT:       # %bb.0:
403; RV32IBT-NEXT:    xor a0, a0, a1
404; RV32IBT-NEXT:    snez a0, a0
405; RV32IBT-NEXT:    neg a0, a0
406; RV32IBT-NEXT:    ret
407;
408; RV32IFBT-LABEL: select_ne_zero_negone:
409; RV32IFBT:       # %bb.0:
410; RV32IFBT-NEXT:    xor a0, a0, a1
411; RV32IFBT-NEXT:    snez a0, a0
412; RV32IFBT-NEXT:    neg a0, a0
413; RV32IFBT-NEXT:    ret
414;
415; RV64I-LABEL: select_ne_zero_negone:
416; RV64I:       # %bb.0:
417; RV64I-NEXT:    xor a0, a0, a1
418; RV64I-NEXT:    snez a0, a0
419; RV64I-NEXT:    neg a0, a0
420; RV64I-NEXT:    ret
421;
422; RV64IFD-LABEL: select_ne_zero_negone:
423; RV64IFD:       # %bb.0:
424; RV64IFD-NEXT:    xor a0, a0, a1
425; RV64IFD-NEXT:    snez a0, a0
426; RV64IFD-NEXT:    neg a0, a0
427; RV64IFD-NEXT:    ret
428;
429; RV64IBT-LABEL: select_ne_zero_negone:
430; RV64IBT:       # %bb.0:
431; RV64IBT-NEXT:    xor a0, a0, a1
432; RV64IBT-NEXT:    snez a0, a0
433; RV64IBT-NEXT:    neg a0, a0
434; RV64IBT-NEXT:    ret
435;
436; RV64IFDBT-LABEL: select_ne_zero_negone:
437; RV64IFDBT:       # %bb.0:
438; RV64IFDBT-NEXT:    xor a0, a0, a1
439; RV64IFDBT-NEXT:    snez a0, a0
440; RV64IFDBT-NEXT:    neg a0, a0
441; RV64IFDBT-NEXT:    ret
442  %1 = icmp ne i32 %a, %b
443  %2 = select i1 %1, i32 -1, i32 0
444  ret i32 %2
445}
446
447define signext i32 @select_sgt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
448; RV32I-LABEL: select_sgt_zero_negone:
449; RV32I:       # %bb.0:
450; RV32I-NEXT:    slt a0, a1, a0
451; RV32I-NEXT:    neg a0, a0
452; RV32I-NEXT:    ret
453;
454; RV32IF-LABEL: select_sgt_zero_negone:
455; RV32IF:       # %bb.0:
456; RV32IF-NEXT:    slt a0, a1, a0
457; RV32IF-NEXT:    neg a0, a0
458; RV32IF-NEXT:    ret
459;
460; RV32IBT-LABEL: select_sgt_zero_negone:
461; RV32IBT:       # %bb.0:
462; RV32IBT-NEXT:    slt a0, a1, a0
463; RV32IBT-NEXT:    neg a0, a0
464; RV32IBT-NEXT:    ret
465;
466; RV32IFBT-LABEL: select_sgt_zero_negone:
467; RV32IFBT:       # %bb.0:
468; RV32IFBT-NEXT:    slt a0, a1, a0
469; RV32IFBT-NEXT:    neg a0, a0
470; RV32IFBT-NEXT:    ret
471;
472; RV64I-LABEL: select_sgt_zero_negone:
473; RV64I:       # %bb.0:
474; RV64I-NEXT:    slt a0, a1, a0
475; RV64I-NEXT:    neg a0, a0
476; RV64I-NEXT:    ret
477;
478; RV64IFD-LABEL: select_sgt_zero_negone:
479; RV64IFD:       # %bb.0:
480; RV64IFD-NEXT:    slt a0, a1, a0
481; RV64IFD-NEXT:    neg a0, a0
482; RV64IFD-NEXT:    ret
483;
484; RV64IBT-LABEL: select_sgt_zero_negone:
485; RV64IBT:       # %bb.0:
486; RV64IBT-NEXT:    slt a0, a1, a0
487; RV64IBT-NEXT:    neg a0, a0
488; RV64IBT-NEXT:    ret
489;
490; RV64IFDBT-LABEL: select_sgt_zero_negone:
491; RV64IFDBT:       # %bb.0:
492; RV64IFDBT-NEXT:    slt a0, a1, a0
493; RV64IFDBT-NEXT:    neg a0, a0
494; RV64IFDBT-NEXT:    ret
495  %1 = icmp sgt i32 %a, %b
496  %2 = select i1 %1, i32 -1, i32 0
497  ret i32 %2
498}
499
500define signext i32 @select_slt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
501; RV32I-LABEL: select_slt_zero_negone:
502; RV32I:       # %bb.0:
503; RV32I-NEXT:    slt a0, a0, a1
504; RV32I-NEXT:    neg a0, a0
505; RV32I-NEXT:    ret
506;
507; RV32IF-LABEL: select_slt_zero_negone:
508; RV32IF:       # %bb.0:
509; RV32IF-NEXT:    slt a0, a0, a1
510; RV32IF-NEXT:    neg a0, a0
511; RV32IF-NEXT:    ret
512;
513; RV32IBT-LABEL: select_slt_zero_negone:
514; RV32IBT:       # %bb.0:
515; RV32IBT-NEXT:    slt a0, a0, a1
516; RV32IBT-NEXT:    neg a0, a0
517; RV32IBT-NEXT:    ret
518;
519; RV32IFBT-LABEL: select_slt_zero_negone:
520; RV32IFBT:       # %bb.0:
521; RV32IFBT-NEXT:    slt a0, a0, a1
522; RV32IFBT-NEXT:    neg a0, a0
523; RV32IFBT-NEXT:    ret
524;
525; RV64I-LABEL: select_slt_zero_negone:
526; RV64I:       # %bb.0:
527; RV64I-NEXT:    slt a0, a0, a1
528; RV64I-NEXT:    neg a0, a0
529; RV64I-NEXT:    ret
530;
531; RV64IFD-LABEL: select_slt_zero_negone:
532; RV64IFD:       # %bb.0:
533; RV64IFD-NEXT:    slt a0, a0, a1
534; RV64IFD-NEXT:    neg a0, a0
535; RV64IFD-NEXT:    ret
536;
537; RV64IBT-LABEL: select_slt_zero_negone:
538; RV64IBT:       # %bb.0:
539; RV64IBT-NEXT:    slt a0, a0, a1
540; RV64IBT-NEXT:    neg a0, a0
541; RV64IBT-NEXT:    ret
542;
543; RV64IFDBT-LABEL: select_slt_zero_negone:
544; RV64IFDBT:       # %bb.0:
545; RV64IFDBT-NEXT:    slt a0, a0, a1
546; RV64IFDBT-NEXT:    neg a0, a0
547; RV64IFDBT-NEXT:    ret
548  %1 = icmp slt i32 %a, %b
549  %2 = select i1 %1, i32 -1, i32 0
550  ret i32 %2
551}
552
553define signext i32 @select_sge_zero_negone(i32 signext %a, i32 signext %b) nounwind {
554; RV32I-LABEL: select_sge_zero_negone:
555; RV32I:       # %bb.0:
556; RV32I-NEXT:    slt a0, a0, a1
557; RV32I-NEXT:    addi a0, a0, -1
558; RV32I-NEXT:    ret
559;
560; RV32IF-LABEL: select_sge_zero_negone:
561; RV32IF:       # %bb.0:
562; RV32IF-NEXT:    slt a0, a0, a1
563; RV32IF-NEXT:    addi a0, a0, -1
564; RV32IF-NEXT:    ret
565;
566; RV32IBT-LABEL: select_sge_zero_negone:
567; RV32IBT:       # %bb.0:
568; RV32IBT-NEXT:    slt a0, a0, a1
569; RV32IBT-NEXT:    addi a0, a0, -1
570; RV32IBT-NEXT:    ret
571;
572; RV32IFBT-LABEL: select_sge_zero_negone:
573; RV32IFBT:       # %bb.0:
574; RV32IFBT-NEXT:    slt a0, a0, a1
575; RV32IFBT-NEXT:    addi a0, a0, -1
576; RV32IFBT-NEXT:    ret
577;
578; RV64I-LABEL: select_sge_zero_negone:
579; RV64I:       # %bb.0:
580; RV64I-NEXT:    slt a0, a0, a1
581; RV64I-NEXT:    addi a0, a0, -1
582; RV64I-NEXT:    ret
583;
584; RV64IFD-LABEL: select_sge_zero_negone:
585; RV64IFD:       # %bb.0:
586; RV64IFD-NEXT:    slt a0, a0, a1
587; RV64IFD-NEXT:    addi a0, a0, -1
588; RV64IFD-NEXT:    ret
589;
590; RV64IBT-LABEL: select_sge_zero_negone:
591; RV64IBT:       # %bb.0:
592; RV64IBT-NEXT:    slt a0, a0, a1
593; RV64IBT-NEXT:    addi a0, a0, -1
594; RV64IBT-NEXT:    ret
595;
596; RV64IFDBT-LABEL: select_sge_zero_negone:
597; RV64IFDBT:       # %bb.0:
598; RV64IFDBT-NEXT:    slt a0, a0, a1
599; RV64IFDBT-NEXT:    addi a0, a0, -1
600; RV64IFDBT-NEXT:    ret
601  %1 = icmp sge i32 %a, %b
602  %2 = select i1 %1, i32 -1, i32 0
603  ret i32 %2
604}
605
606define signext i32 @select_sle_zero_negone(i32 signext %a, i32 signext %b) nounwind {
607; RV32I-LABEL: select_sle_zero_negone:
608; RV32I:       # %bb.0:
609; RV32I-NEXT:    slt a0, a1, a0
610; RV32I-NEXT:    addi a0, a0, -1
611; RV32I-NEXT:    ret
612;
613; RV32IF-LABEL: select_sle_zero_negone:
614; RV32IF:       # %bb.0:
615; RV32IF-NEXT:    slt a0, a1, a0
616; RV32IF-NEXT:    addi a0, a0, -1
617; RV32IF-NEXT:    ret
618;
619; RV32IBT-LABEL: select_sle_zero_negone:
620; RV32IBT:       # %bb.0:
621; RV32IBT-NEXT:    slt a0, a1, a0
622; RV32IBT-NEXT:    addi a0, a0, -1
623; RV32IBT-NEXT:    ret
624;
625; RV32IFBT-LABEL: select_sle_zero_negone:
626; RV32IFBT:       # %bb.0:
627; RV32IFBT-NEXT:    slt a0, a1, a0
628; RV32IFBT-NEXT:    addi a0, a0, -1
629; RV32IFBT-NEXT:    ret
630;
631; RV64I-LABEL: select_sle_zero_negone:
632; RV64I:       # %bb.0:
633; RV64I-NEXT:    slt a0, a1, a0
634; RV64I-NEXT:    addi a0, a0, -1
635; RV64I-NEXT:    ret
636;
637; RV64IFD-LABEL: select_sle_zero_negone:
638; RV64IFD:       # %bb.0:
639; RV64IFD-NEXT:    slt a0, a1, a0
640; RV64IFD-NEXT:    addi a0, a0, -1
641; RV64IFD-NEXT:    ret
642;
643; RV64IBT-LABEL: select_sle_zero_negone:
644; RV64IBT:       # %bb.0:
645; RV64IBT-NEXT:    slt a0, a1, a0
646; RV64IBT-NEXT:    addi a0, a0, -1
647; RV64IBT-NEXT:    ret
648;
649; RV64IFDBT-LABEL: select_sle_zero_negone:
650; RV64IFDBT:       # %bb.0:
651; RV64IFDBT-NEXT:    slt a0, a1, a0
652; RV64IFDBT-NEXT:    addi a0, a0, -1
653; RV64IFDBT-NEXT:    ret
654  %1 = icmp sle i32 %a, %b
655  %2 = select i1 %1, i32 -1, i32 0
656  ret i32 %2
657}
658
659define signext i32 @select_ugt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
660; RV32I-LABEL: select_ugt_zero_negone:
661; RV32I:       # %bb.0:
662; RV32I-NEXT:    sltu a0, a1, a0
663; RV32I-NEXT:    neg a0, a0
664; RV32I-NEXT:    ret
665;
666; RV32IF-LABEL: select_ugt_zero_negone:
667; RV32IF:       # %bb.0:
668; RV32IF-NEXT:    sltu a0, a1, a0
669; RV32IF-NEXT:    neg a0, a0
670; RV32IF-NEXT:    ret
671;
672; RV32IBT-LABEL: select_ugt_zero_negone:
673; RV32IBT:       # %bb.0:
674; RV32IBT-NEXT:    sltu a0, a1, a0
675; RV32IBT-NEXT:    neg a0, a0
676; RV32IBT-NEXT:    ret
677;
678; RV32IFBT-LABEL: select_ugt_zero_negone:
679; RV32IFBT:       # %bb.0:
680; RV32IFBT-NEXT:    sltu a0, a1, a0
681; RV32IFBT-NEXT:    neg a0, a0
682; RV32IFBT-NEXT:    ret
683;
684; RV64I-LABEL: select_ugt_zero_negone:
685; RV64I:       # %bb.0:
686; RV64I-NEXT:    sltu a0, a1, a0
687; RV64I-NEXT:    neg a0, a0
688; RV64I-NEXT:    ret
689;
690; RV64IFD-LABEL: select_ugt_zero_negone:
691; RV64IFD:       # %bb.0:
692; RV64IFD-NEXT:    sltu a0, a1, a0
693; RV64IFD-NEXT:    neg a0, a0
694; RV64IFD-NEXT:    ret
695;
696; RV64IBT-LABEL: select_ugt_zero_negone:
697; RV64IBT:       # %bb.0:
698; RV64IBT-NEXT:    sltu a0, a1, a0
699; RV64IBT-NEXT:    neg a0, a0
700; RV64IBT-NEXT:    ret
701;
702; RV64IFDBT-LABEL: select_ugt_zero_negone:
703; RV64IFDBT:       # %bb.0:
704; RV64IFDBT-NEXT:    sltu a0, a1, a0
705; RV64IFDBT-NEXT:    neg a0, a0
706; RV64IFDBT-NEXT:    ret
707  %1 = icmp ugt i32 %a, %b
708  %2 = select i1 %1, i32 -1, i32 0
709  ret i32 %2
710}
711
712define signext i32 @select_ult_zero_negone(i32 signext %a, i32 signext %b) nounwind {
713; RV32I-LABEL: select_ult_zero_negone:
714; RV32I:       # %bb.0:
715; RV32I-NEXT:    sltu a0, a0, a1
716; RV32I-NEXT:    neg a0, a0
717; RV32I-NEXT:    ret
718;
719; RV32IF-LABEL: select_ult_zero_negone:
720; RV32IF:       # %bb.0:
721; RV32IF-NEXT:    sltu a0, a0, a1
722; RV32IF-NEXT:    neg a0, a0
723; RV32IF-NEXT:    ret
724;
725; RV32IBT-LABEL: select_ult_zero_negone:
726; RV32IBT:       # %bb.0:
727; RV32IBT-NEXT:    sltu a0, a0, a1
728; RV32IBT-NEXT:    neg a0, a0
729; RV32IBT-NEXT:    ret
730;
731; RV32IFBT-LABEL: select_ult_zero_negone:
732; RV32IFBT:       # %bb.0:
733; RV32IFBT-NEXT:    sltu a0, a0, a1
734; RV32IFBT-NEXT:    neg a0, a0
735; RV32IFBT-NEXT:    ret
736;
737; RV64I-LABEL: select_ult_zero_negone:
738; RV64I:       # %bb.0:
739; RV64I-NEXT:    sltu a0, a0, a1
740; RV64I-NEXT:    neg a0, a0
741; RV64I-NEXT:    ret
742;
743; RV64IFD-LABEL: select_ult_zero_negone:
744; RV64IFD:       # %bb.0:
745; RV64IFD-NEXT:    sltu a0, a0, a1
746; RV64IFD-NEXT:    neg a0, a0
747; RV64IFD-NEXT:    ret
748;
749; RV64IBT-LABEL: select_ult_zero_negone:
750; RV64IBT:       # %bb.0:
751; RV64IBT-NEXT:    sltu a0, a0, a1
752; RV64IBT-NEXT:    neg a0, a0
753; RV64IBT-NEXT:    ret
754;
755; RV64IFDBT-LABEL: select_ult_zero_negone:
756; RV64IFDBT:       # %bb.0:
757; RV64IFDBT-NEXT:    sltu a0, a0, a1
758; RV64IFDBT-NEXT:    neg a0, a0
759; RV64IFDBT-NEXT:    ret
760  %1 = icmp ult i32 %a, %b
761  %2 = select i1 %1, i32 -1, i32 0
762  ret i32 %2
763}
764
765define signext i32 @select_uge_zero_negone(i32 signext %a, i32 signext %b) nounwind {
766; RV32I-LABEL: select_uge_zero_negone:
767; RV32I:       # %bb.0:
768; RV32I-NEXT:    sltu a0, a0, a1
769; RV32I-NEXT:    addi a0, a0, -1
770; RV32I-NEXT:    ret
771;
772; RV32IF-LABEL: select_uge_zero_negone:
773; RV32IF:       # %bb.0:
774; RV32IF-NEXT:    sltu a0, a0, a1
775; RV32IF-NEXT:    addi a0, a0, -1
776; RV32IF-NEXT:    ret
777;
778; RV32IBT-LABEL: select_uge_zero_negone:
779; RV32IBT:       # %bb.0:
780; RV32IBT-NEXT:    sltu a0, a0, a1
781; RV32IBT-NEXT:    addi a0, a0, -1
782; RV32IBT-NEXT:    ret
783;
784; RV32IFBT-LABEL: select_uge_zero_negone:
785; RV32IFBT:       # %bb.0:
786; RV32IFBT-NEXT:    sltu a0, a0, a1
787; RV32IFBT-NEXT:    addi a0, a0, -1
788; RV32IFBT-NEXT:    ret
789;
790; RV64I-LABEL: select_uge_zero_negone:
791; RV64I:       # %bb.0:
792; RV64I-NEXT:    sltu a0, a0, a1
793; RV64I-NEXT:    addi a0, a0, -1
794; RV64I-NEXT:    ret
795;
796; RV64IFD-LABEL: select_uge_zero_negone:
797; RV64IFD:       # %bb.0:
798; RV64IFD-NEXT:    sltu a0, a0, a1
799; RV64IFD-NEXT:    addi a0, a0, -1
800; RV64IFD-NEXT:    ret
801;
802; RV64IBT-LABEL: select_uge_zero_negone:
803; RV64IBT:       # %bb.0:
804; RV64IBT-NEXT:    sltu a0, a0, a1
805; RV64IBT-NEXT:    addi a0, a0, -1
806; RV64IBT-NEXT:    ret
807;
808; RV64IFDBT-LABEL: select_uge_zero_negone:
809; RV64IFDBT:       # %bb.0:
810; RV64IFDBT-NEXT:    sltu a0, a0, a1
811; RV64IFDBT-NEXT:    addi a0, a0, -1
812; RV64IFDBT-NEXT:    ret
813  %1 = icmp uge i32 %a, %b
814  %2 = select i1 %1, i32 -1, i32 0
815  ret i32 %2
816}
817
818define signext i32 @select_ule_zero_negone(i32 signext %a, i32 signext %b) nounwind {
819; RV32I-LABEL: select_ule_zero_negone:
820; RV32I:       # %bb.0:
821; RV32I-NEXT:    sltu a0, a1, a0
822; RV32I-NEXT:    addi a0, a0, -1
823; RV32I-NEXT:    ret
824;
825; RV32IF-LABEL: select_ule_zero_negone:
826; RV32IF:       # %bb.0:
827; RV32IF-NEXT:    sltu a0, a1, a0
828; RV32IF-NEXT:    addi a0, a0, -1
829; RV32IF-NEXT:    ret
830;
831; RV32IBT-LABEL: select_ule_zero_negone:
832; RV32IBT:       # %bb.0:
833; RV32IBT-NEXT:    sltu a0, a1, a0
834; RV32IBT-NEXT:    addi a0, a0, -1
835; RV32IBT-NEXT:    ret
836;
837; RV32IFBT-LABEL: select_ule_zero_negone:
838; RV32IFBT:       # %bb.0:
839; RV32IFBT-NEXT:    sltu a0, a1, a0
840; RV32IFBT-NEXT:    addi a0, a0, -1
841; RV32IFBT-NEXT:    ret
842;
843; RV64I-LABEL: select_ule_zero_negone:
844; RV64I:       # %bb.0:
845; RV64I-NEXT:    sltu a0, a1, a0
846; RV64I-NEXT:    addi a0, a0, -1
847; RV64I-NEXT:    ret
848;
849; RV64IFD-LABEL: select_ule_zero_negone:
850; RV64IFD:       # %bb.0:
851; RV64IFD-NEXT:    sltu a0, a1, a0
852; RV64IFD-NEXT:    addi a0, a0, -1
853; RV64IFD-NEXT:    ret
854;
855; RV64IBT-LABEL: select_ule_zero_negone:
856; RV64IBT:       # %bb.0:
857; RV64IBT-NEXT:    sltu a0, a1, a0
858; RV64IBT-NEXT:    addi a0, a0, -1
859; RV64IBT-NEXT:    ret
860;
861; RV64IFDBT-LABEL: select_ule_zero_negone:
862; RV64IFDBT:       # %bb.0:
863; RV64IFDBT-NEXT:    sltu a0, a1, a0
864; RV64IFDBT-NEXT:    addi a0, a0, -1
865; RV64IFDBT-NEXT:    ret
866  %1 = icmp ule i32 %a, %b
867  %2 = select i1 %1, i32 -1, i32 0
868  ret i32 %2
869}
870