1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
4
5define <vscale x 1 x i64> @vwsub_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
6; CHECK-LABEL: vwsub_vv_nxv1i64:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
9; CHECK-NEXT:    vwsub.vv v10, v8, v9
10; CHECK-NEXT:    vmv1r.v v8, v10
11; CHECK-NEXT:    ret
12  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
13  %vd = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
14  %ve = sub <vscale x 1 x i64> %vc, %vd
15  ret <vscale x 1 x i64> %ve
16}
17
18define <vscale x 1 x i64> @vwsubu_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
19; CHECK-LABEL: vwsubu_vv_nxv1i64:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
22; CHECK-NEXT:    vwsubu.vv v10, v8, v9
23; CHECK-NEXT:    vmv1r.v v8, v10
24; CHECK-NEXT:    ret
25  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
26  %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
27  %ve = sub <vscale x 1 x i64> %vc, %vd
28  ret <vscale x 1 x i64> %ve
29}
30
31define <vscale x 1 x i64> @vwsub_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
32; CHECK-LABEL: vwsub_vx_nxv1i64:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
35; CHECK-NEXT:    vwsub.vx v9, v8, a0
36; CHECK-NEXT:    vmv1r.v v8, v9
37; CHECK-NEXT:    ret
38  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
39  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
40  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
41  %vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
42  %ve = sub <vscale x 1 x i64> %vc, %vd
43  ret <vscale x 1 x i64> %ve
44}
45
46define <vscale x 1 x i64> @vwsubu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
47; CHECK-LABEL: vwsubu_vx_nxv1i64:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
50; CHECK-NEXT:    vwsubu.vx v9, v8, a0
51; CHECK-NEXT:    vmv1r.v v8, v9
52; CHECK-NEXT:    ret
53  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
54  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
55  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
56  %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
57  %ve = sub <vscale x 1 x i64> %vc, %vd
58  ret <vscale x 1 x i64> %ve
59}
60
61define <vscale x 1 x i64> @vwsub_wv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
62; CHECK-LABEL: vwsub_wv_nxv1i64:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
65; CHECK-NEXT:    vwsub.wv v10, v8, v9
66; CHECK-NEXT:    vmv1r.v v8, v10
67; CHECK-NEXT:    ret
68  %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
69  %vd = sub <vscale x 1 x i64> %va, %vc
70  ret <vscale x 1 x i64> %vd
71}
72
73define <vscale x 1 x i64> @vwsubu_wv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
74; CHECK-LABEL: vwsubu_wv_nxv1i64:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
77; CHECK-NEXT:    vwsubu.wv v10, v8, v9
78; CHECK-NEXT:    vmv1r.v v8, v10
79; CHECK-NEXT:    ret
80  %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
81  %vd = sub <vscale x 1 x i64> %va, %vc
82  ret <vscale x 1 x i64> %vd
83}
84
85define <vscale x 1 x i64> @vwsub_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
86; CHECK-LABEL: vwsub_wx_nxv1i64:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
89; CHECK-NEXT:    vwsub.wx v8, v8, a0
90; CHECK-NEXT:    ret
91  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
92  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
93  %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
94  %vc = sub <vscale x 1 x i64> %va, %vb
95  ret <vscale x 1 x i64> %vc
96}
97
98define <vscale x 1 x i64> @vwsubu_wx_nxv1i64(<vscale x 1 x i64> %va, i32 %b) {
99; CHECK-LABEL: vwsubu_wx_nxv1i64:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
102; CHECK-NEXT:    vwsubu.wx v8, v8, a0
103; CHECK-NEXT:    ret
104  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
105  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
106  %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
107  %vc = sub <vscale x 1 x i64> %va, %vb
108  ret <vscale x 1 x i64> %vc
109}
110
111define <vscale x 2 x i64> @vwsub_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
112; CHECK-LABEL: vwsub_vv_nxv2i64:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
115; CHECK-NEXT:    vwsub.vv v10, v8, v9
116; CHECK-NEXT:    vmv2r.v v8, v10
117; CHECK-NEXT:    ret
118  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
119  %vd = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
120  %ve = sub <vscale x 2 x i64> %vc, %vd
121  ret <vscale x 2 x i64> %ve
122}
123
124define <vscale x 2 x i64> @vwsubu_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
125; CHECK-LABEL: vwsubu_vv_nxv2i64:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
128; CHECK-NEXT:    vwsubu.vv v10, v8, v9
129; CHECK-NEXT:    vmv2r.v v8, v10
130; CHECK-NEXT:    ret
131  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
132  %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
133  %ve = sub <vscale x 2 x i64> %vc, %vd
134  ret <vscale x 2 x i64> %ve
135}
136
137define <vscale x 2 x i64> @vwsub_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
138; CHECK-LABEL: vwsub_vx_nxv2i64:
139; CHECK:       # %bb.0:
140; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
141; CHECK-NEXT:    vwsub.vx v10, v8, a0
142; CHECK-NEXT:    vmv2r.v v8, v10
143; CHECK-NEXT:    ret
144  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
145  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
146  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
147  %vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
148  %ve = sub <vscale x 2 x i64> %vc, %vd
149  ret <vscale x 2 x i64> %ve
150}
151
152define <vscale x 2 x i64> @vwsubu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
153; CHECK-LABEL: vwsubu_vx_nxv2i64:
154; CHECK:       # %bb.0:
155; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
156; CHECK-NEXT:    vwsubu.vx v10, v8, a0
157; CHECK-NEXT:    vmv2r.v v8, v10
158; CHECK-NEXT:    ret
159  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
160  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
161  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
162  %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
163  %ve = sub <vscale x 2 x i64> %vc, %vd
164  ret <vscale x 2 x i64> %ve
165}
166
167define <vscale x 2 x i64> @vwsub_wv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
168; CHECK-LABEL: vwsub_wv_nxv2i64:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
171; CHECK-NEXT:    vwsub.wv v12, v8, v10
172; CHECK-NEXT:    vmv2r.v v8, v12
173; CHECK-NEXT:    ret
174  %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
175  %vd = sub <vscale x 2 x i64> %va, %vc
176  ret <vscale x 2 x i64> %vd
177}
178
179define <vscale x 2 x i64> @vwsubu_wv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
180; CHECK-LABEL: vwsubu_wv_nxv2i64:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
183; CHECK-NEXT:    vwsubu.wv v12, v8, v10
184; CHECK-NEXT:    vmv2r.v v8, v12
185; CHECK-NEXT:    ret
186  %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
187  %vd = sub <vscale x 2 x i64> %va, %vc
188  ret <vscale x 2 x i64> %vd
189}
190
191define <vscale x 2 x i64> @vwsub_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
192; CHECK-LABEL: vwsub_wx_nxv2i64:
193; CHECK:       # %bb.0:
194; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
195; CHECK-NEXT:    vwsub.wx v8, v8, a0
196; CHECK-NEXT:    ret
197  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
198  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
199  %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
200  %vc = sub <vscale x 2 x i64> %va, %vb
201  ret <vscale x 2 x i64> %vc
202}
203
204define <vscale x 2 x i64> @vwsubu_wx_nxv2i64(<vscale x 2 x i64> %va, i32 %b) {
205; CHECK-LABEL: vwsubu_wx_nxv2i64:
206; CHECK:       # %bb.0:
207; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
208; CHECK-NEXT:    vwsubu.wx v8, v8, a0
209; CHECK-NEXT:    ret
210  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
211  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
212  %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
213  %vc = sub <vscale x 2 x i64> %va, %vb
214  ret <vscale x 2 x i64> %vc
215}
216
217define <vscale x 4 x i64> @vwsub_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
218; CHECK-LABEL: vwsub_vv_nxv4i64:
219; CHECK:       # %bb.0:
220; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
221; CHECK-NEXT:    vwsub.vv v12, v8, v10
222; CHECK-NEXT:    vmv4r.v v8, v12
223; CHECK-NEXT:    ret
224  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
225  %vd = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
226  %ve = sub <vscale x 4 x i64> %vc, %vd
227  ret <vscale x 4 x i64> %ve
228}
229
230define <vscale x 4 x i64> @vwsubu_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
231; CHECK-LABEL: vwsubu_vv_nxv4i64:
232; CHECK:       # %bb.0:
233; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
234; CHECK-NEXT:    vwsubu.vv v12, v8, v10
235; CHECK-NEXT:    vmv4r.v v8, v12
236; CHECK-NEXT:    ret
237  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
238  %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
239  %ve = sub <vscale x 4 x i64> %vc, %vd
240  ret <vscale x 4 x i64> %ve
241}
242
243define <vscale x 4 x i64> @vwsub_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
244; CHECK-LABEL: vwsub_vx_nxv4i64:
245; CHECK:       # %bb.0:
246; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
247; CHECK-NEXT:    vwsub.vx v12, v8, a0
248; CHECK-NEXT:    vmv4r.v v8, v12
249; CHECK-NEXT:    ret
250  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
251  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
252  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
253  %vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
254  %ve = sub <vscale x 4 x i64> %vc, %vd
255  ret <vscale x 4 x i64> %ve
256}
257
258define <vscale x 4 x i64> @vwsubu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
259; CHECK-LABEL: vwsubu_vx_nxv4i64:
260; CHECK:       # %bb.0:
261; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
262; CHECK-NEXT:    vwsubu.vx v12, v8, a0
263; CHECK-NEXT:    vmv4r.v v8, v12
264; CHECK-NEXT:    ret
265  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
266  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
267  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
268  %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
269  %ve = sub <vscale x 4 x i64> %vc, %vd
270  ret <vscale x 4 x i64> %ve
271}
272
273define <vscale x 4 x i64> @vwsub_wv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
274; CHECK-LABEL: vwsub_wv_nxv4i64:
275; CHECK:       # %bb.0:
276; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
277; CHECK-NEXT:    vwsub.wv v16, v8, v12
278; CHECK-NEXT:    vmv4r.v v8, v16
279; CHECK-NEXT:    ret
280  %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
281  %vd = sub <vscale x 4 x i64> %va, %vc
282  ret <vscale x 4 x i64> %vd
283}
284
285define <vscale x 4 x i64> @vwsubu_wv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
286; CHECK-LABEL: vwsubu_wv_nxv4i64:
287; CHECK:       # %bb.0:
288; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
289; CHECK-NEXT:    vwsubu.wv v16, v8, v12
290; CHECK-NEXT:    vmv4r.v v8, v16
291; CHECK-NEXT:    ret
292  %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
293  %vd = sub <vscale x 4 x i64> %va, %vc
294  ret <vscale x 4 x i64> %vd
295}
296
297define <vscale x 4 x i64> @vwsub_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
298; CHECK-LABEL: vwsub_wx_nxv4i64:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
301; CHECK-NEXT:    vwsub.wx v8, v8, a0
302; CHECK-NEXT:    ret
303  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
304  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
305  %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
306  %vc = sub <vscale x 4 x i64> %va, %vb
307  ret <vscale x 4 x i64> %vc
308}
309
310define <vscale x 4 x i64> @vwsubu_wx_nxv4i64(<vscale x 4 x i64> %va, i32 %b) {
311; CHECK-LABEL: vwsubu_wx_nxv4i64:
312; CHECK:       # %bb.0:
313; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
314; CHECK-NEXT:    vwsubu.wx v8, v8, a0
315; CHECK-NEXT:    ret
316  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
317  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
318  %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
319  %vc = sub <vscale x 4 x i64> %va, %vb
320  ret <vscale x 4 x i64> %vc
321}
322
323define <vscale x 8 x i64> @vwsub_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
324; CHECK-LABEL: vwsub_vv_nxv8i64:
325; CHECK:       # %bb.0:
326; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
327; CHECK-NEXT:    vwsub.vv v16, v8, v12
328; CHECK-NEXT:    vmv8r.v v8, v16
329; CHECK-NEXT:    ret
330  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
331  %vd = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
332  %ve = sub <vscale x 8 x i64> %vc, %vd
333  ret <vscale x 8 x i64> %ve
334}
335
336define <vscale x 8 x i64> @vwsubu_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
337; CHECK-LABEL: vwsubu_vv_nxv8i64:
338; CHECK:       # %bb.0:
339; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
340; CHECK-NEXT:    vwsubu.vv v16, v8, v12
341; CHECK-NEXT:    vmv8r.v v8, v16
342; CHECK-NEXT:    ret
343  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
344  %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
345  %ve = sub <vscale x 8 x i64> %vc, %vd
346  ret <vscale x 8 x i64> %ve
347}
348
349define <vscale x 8 x i64> @vwsub_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
350; CHECK-LABEL: vwsub_vx_nxv8i64:
351; CHECK:       # %bb.0:
352; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
353; CHECK-NEXT:    vwsub.vx v16, v8, a0
354; CHECK-NEXT:    vmv8r.v v8, v16
355; CHECK-NEXT:    ret
356  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
357  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
358  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
359  %vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
360  %ve = sub <vscale x 8 x i64> %vc, %vd
361  ret <vscale x 8 x i64> %ve
362}
363
364define <vscale x 8 x i64> @vwsubu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
365; CHECK-LABEL: vwsubu_vx_nxv8i64:
366; CHECK:       # %bb.0:
367; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
368; CHECK-NEXT:    vwsubu.vx v16, v8, a0
369; CHECK-NEXT:    vmv8r.v v8, v16
370; CHECK-NEXT:    ret
371  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
372  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
373  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
374  %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
375  %ve = sub <vscale x 8 x i64> %vc, %vd
376  ret <vscale x 8 x i64> %ve
377}
378
379define <vscale x 8 x i64> @vwsub_wv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
380; CHECK-LABEL: vwsub_wv_nxv8i64:
381; CHECK:       # %bb.0:
382; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
383; CHECK-NEXT:    vwsub.wv v24, v8, v16
384; CHECK-NEXT:    vmv8r.v v8, v24
385; CHECK-NEXT:    ret
386  %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
387  %vd = sub <vscale x 8 x i64> %va, %vc
388  ret <vscale x 8 x i64> %vd
389}
390
391define <vscale x 8 x i64> @vwsubu_wv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
392; CHECK-LABEL: vwsubu_wv_nxv8i64:
393; CHECK:       # %bb.0:
394; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
395; CHECK-NEXT:    vwsubu.wv v24, v8, v16
396; CHECK-NEXT:    vmv8r.v v8, v24
397; CHECK-NEXT:    ret
398  %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
399  %vd = sub <vscale x 8 x i64> %va, %vc
400  ret <vscale x 8 x i64> %vd
401}
402
403define <vscale x 8 x i64> @vwsub_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
404; CHECK-LABEL: vwsub_wx_nxv8i64:
405; CHECK:       # %bb.0:
406; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
407; CHECK-NEXT:    vwsub.wx v8, v8, a0
408; CHECK-NEXT:    ret
409  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
410  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
411  %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
412  %vc = sub <vscale x 8 x i64> %va, %vb
413  ret <vscale x 8 x i64> %vc
414}
415
416define <vscale x 8 x i64> @vwsubu_wx_nxv8i64(<vscale x 8 x i64> %va, i32 %b) {
417; CHECK-LABEL: vwsubu_wx_nxv8i64:
418; CHECK:       # %bb.0:
419; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
420; CHECK-NEXT:    vwsubu.wx v8, v8, a0
421; CHECK-NEXT:    ret
422  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
423  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
424  %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
425  %vc = sub <vscale x 8 x i64> %va, %vb
426  ret <vscale x 8 x i64> %vc
427}
428