1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
4
5define <vscale x 1 x i64> @vwmul_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
6; CHECK-LABEL: vwmul_vv_nxv1i64:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
9; CHECK-NEXT:    vwmul.vv v10, v8, v9
10; CHECK-NEXT:    vmv1r.v v8, v10
11; CHECK-NEXT:    ret
12  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
13  %vd = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
14  %ve = mul <vscale x 1 x i64> %vc, %vd
15  ret <vscale x 1 x i64> %ve
16}
17
18define <vscale x 1 x i64> @vwmulu_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
19; CHECK-LABEL: vwmulu_vv_nxv1i64:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
22; CHECK-NEXT:    vwmulu.vv v10, v8, v9
23; CHECK-NEXT:    vmv1r.v v8, v10
24; CHECK-NEXT:    ret
25  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
26  %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
27  %ve = mul <vscale x 1 x i64> %vc, %vd
28  ret <vscale x 1 x i64> %ve
29}
30
31define <vscale x 1 x i64> @vwmulsu_vv_nxv1i64(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
32; CHECK-LABEL: vwmulsu_vv_nxv1i64:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
35; CHECK-NEXT:    vwmulsu.vv v10, v8, v9
36; CHECK-NEXT:    vmv1r.v v8, v10
37; CHECK-NEXT:    ret
38  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
39  %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
40  %ve = mul <vscale x 1 x i64> %vc, %vd
41  ret <vscale x 1 x i64> %ve
42}
43
44define <vscale x 1 x i64> @vwmul_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
45; CHECK-LABEL: vwmul_vx_nxv1i64:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
48; CHECK-NEXT:    vwmul.vx v9, v8, a0
49; CHECK-NEXT:    vmv1r.v v8, v9
50; CHECK-NEXT:    ret
51  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
52  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
53  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
54  %vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
55  %ve = mul <vscale x 1 x i64> %vc, %vd
56  ret <vscale x 1 x i64> %ve
57}
58
59define <vscale x 1 x i64> @vwmulu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
60; CHECK-LABEL: vwmulu_vx_nxv1i64:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
63; CHECK-NEXT:    vwmulu.vx v9, v8, a0
64; CHECK-NEXT:    vmv1r.v v8, v9
65; CHECK-NEXT:    ret
66  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
67  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
68  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
69  %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
70  %ve = mul <vscale x 1 x i64> %vc, %vd
71  ret <vscale x 1 x i64> %ve
72}
73
74define <vscale x 1 x i64> @vwmulsu_vx_nxv1i64(<vscale x 1 x i32> %va, i32 %b) {
75; CHECK-LABEL: vwmulsu_vx_nxv1i64:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
78; CHECK-NEXT:    vwmulsu.vx v9, v8, a0
79; CHECK-NEXT:    vmv1r.v v8, v9
80; CHECK-NEXT:    ret
81  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
82  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
83  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
84  %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
85  %ve = mul <vscale x 1 x i64> %vc, %vd
86  ret <vscale x 1 x i64> %ve
87}
88
89define <vscale x 2 x i64> @vwmul_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
90; CHECK-LABEL: vwmul_vv_nxv2i64:
91; CHECK:       # %bb.0:
92; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
93; CHECK-NEXT:    vwmul.vv v10, v8, v9
94; CHECK-NEXT:    vmv2r.v v8, v10
95; CHECK-NEXT:    ret
96  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
97  %vd = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
98  %ve = mul <vscale x 2 x i64> %vc, %vd
99  ret <vscale x 2 x i64> %ve
100}
101
102define <vscale x 2 x i64> @vwmulu_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
103; CHECK-LABEL: vwmulu_vv_nxv2i64:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
106; CHECK-NEXT:    vwmulu.vv v10, v8, v9
107; CHECK-NEXT:    vmv2r.v v8, v10
108; CHECK-NEXT:    ret
109  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
110  %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
111  %ve = mul <vscale x 2 x i64> %vc, %vd
112  ret <vscale x 2 x i64> %ve
113}
114
115define <vscale x 2 x i64> @vwmulsu_vv_nxv2i64(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
116; CHECK-LABEL: vwmulsu_vv_nxv2i64:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
119; CHECK-NEXT:    vwmulsu.vv v10, v8, v9
120; CHECK-NEXT:    vmv2r.v v8, v10
121; CHECK-NEXT:    ret
122  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
123  %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
124  %ve = mul <vscale x 2 x i64> %vc, %vd
125  ret <vscale x 2 x i64> %ve
126}
127
128define <vscale x 2 x i64> @vwmul_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
129; CHECK-LABEL: vwmul_vx_nxv2i64:
130; CHECK:       # %bb.0:
131; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
132; CHECK-NEXT:    vwmul.vx v10, v8, a0
133; CHECK-NEXT:    vmv2r.v v8, v10
134; CHECK-NEXT:    ret
135  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
136  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
137  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
138  %vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
139  %ve = mul <vscale x 2 x i64> %vc, %vd
140  ret <vscale x 2 x i64> %ve
141}
142
143define <vscale x 2 x i64> @vwmulu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
144; CHECK-LABEL: vwmulu_vx_nxv2i64:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
147; CHECK-NEXT:    vwmulu.vx v10, v8, a0
148; CHECK-NEXT:    vmv2r.v v8, v10
149; CHECK-NEXT:    ret
150  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
151  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
152  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
153  %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
154  %ve = mul <vscale x 2 x i64> %vc, %vd
155  ret <vscale x 2 x i64> %ve
156}
157
158define <vscale x 2 x i64> @vwmulsu_vx_nxv2i64(<vscale x 2 x i32> %va, i32 %b) {
159; CHECK-LABEL: vwmulsu_vx_nxv2i64:
160; CHECK:       # %bb.0:
161; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
162; CHECK-NEXT:    vwmulsu.vx v10, v8, a0
163; CHECK-NEXT:    vmv2r.v v8, v10
164; CHECK-NEXT:    ret
165  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
166  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
167  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
168  %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
169  %ve = mul <vscale x 2 x i64> %vc, %vd
170  ret <vscale x 2 x i64> %ve
171}
172
173define <vscale x 4 x i64> @vwmul_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
174; CHECK-LABEL: vwmul_vv_nxv4i64:
175; CHECK:       # %bb.0:
176; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
177; CHECK-NEXT:    vwmul.vv v12, v8, v10
178; CHECK-NEXT:    vmv4r.v v8, v12
179; CHECK-NEXT:    ret
180  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
181  %vd = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
182  %ve = mul <vscale x 4 x i64> %vc, %vd
183  ret <vscale x 4 x i64> %ve
184}
185
186define <vscale x 4 x i64> @vwmulu_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
187; CHECK-LABEL: vwmulu_vv_nxv4i64:
188; CHECK:       # %bb.0:
189; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
190; CHECK-NEXT:    vwmulu.vv v12, v8, v10
191; CHECK-NEXT:    vmv4r.v v8, v12
192; CHECK-NEXT:    ret
193  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
194  %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
195  %ve = mul <vscale x 4 x i64> %vc, %vd
196  ret <vscale x 4 x i64> %ve
197}
198
199define <vscale x 4 x i64> @vwmulsu_vv_nxv4i64(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
200; CHECK-LABEL: vwmulsu_vv_nxv4i64:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
203; CHECK-NEXT:    vwmulsu.vv v12, v8, v10
204; CHECK-NEXT:    vmv4r.v v8, v12
205; CHECK-NEXT:    ret
206  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
207  %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
208  %ve = mul <vscale x 4 x i64> %vc, %vd
209  ret <vscale x 4 x i64> %ve
210}
211
212define <vscale x 4 x i64> @vwmul_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
213; CHECK-LABEL: vwmul_vx_nxv4i64:
214; CHECK:       # %bb.0:
215; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
216; CHECK-NEXT:    vwmul.vx v12, v8, a0
217; CHECK-NEXT:    vmv4r.v v8, v12
218; CHECK-NEXT:    ret
219  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
220  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
221  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
222  %vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
223  %ve = mul <vscale x 4 x i64> %vc, %vd
224  ret <vscale x 4 x i64> %ve
225}
226
227define <vscale x 4 x i64> @vwmulu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
228; CHECK-LABEL: vwmulu_vx_nxv4i64:
229; CHECK:       # %bb.0:
230; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
231; CHECK-NEXT:    vwmulu.vx v12, v8, a0
232; CHECK-NEXT:    vmv4r.v v8, v12
233; CHECK-NEXT:    ret
234  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
235  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
236  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
237  %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
238  %ve = mul <vscale x 4 x i64> %vc, %vd
239  ret <vscale x 4 x i64> %ve
240}
241
242define <vscale x 4 x i64> @vwmulsu_vx_nxv4i64(<vscale x 4 x i32> %va, i32 %b) {
243; CHECK-LABEL: vwmulsu_vx_nxv4i64:
244; CHECK:       # %bb.0:
245; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
246; CHECK-NEXT:    vwmulsu.vx v12, v8, a0
247; CHECK-NEXT:    vmv4r.v v8, v12
248; CHECK-NEXT:    ret
249  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
250  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
251  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
252  %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
253  %ve = mul <vscale x 4 x i64> %vc, %vd
254  ret <vscale x 4 x i64> %ve
255}
256
257define <vscale x 8 x i64> @vwmul_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
258; CHECK-LABEL: vwmul_vv_nxv8i64:
259; CHECK:       # %bb.0:
260; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
261; CHECK-NEXT:    vwmul.vv v16, v8, v12
262; CHECK-NEXT:    vmv8r.v v8, v16
263; CHECK-NEXT:    ret
264  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
265  %vd = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
266  %ve = mul <vscale x 8 x i64> %vc, %vd
267  ret <vscale x 8 x i64> %ve
268}
269
270define <vscale x 8 x i64> @vwmulu_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
271; CHECK-LABEL: vwmulu_vv_nxv8i64:
272; CHECK:       # %bb.0:
273; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
274; CHECK-NEXT:    vwmulu.vv v16, v8, v12
275; CHECK-NEXT:    vmv8r.v v8, v16
276; CHECK-NEXT:    ret
277  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
278  %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
279  %ve = mul <vscale x 8 x i64> %vc, %vd
280  ret <vscale x 8 x i64> %ve
281}
282
283define <vscale x 8 x i64> @vwmulsu_vv_nxv8i64(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
284; CHECK-LABEL: vwmulsu_vv_nxv8i64:
285; CHECK:       # %bb.0:
286; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
287; CHECK-NEXT:    vwmulsu.vv v16, v8, v12
288; CHECK-NEXT:    vmv8r.v v8, v16
289; CHECK-NEXT:    ret
290  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
291  %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
292  %ve = mul <vscale x 8 x i64> %vc, %vd
293  ret <vscale x 8 x i64> %ve
294}
295
296define <vscale x 8 x i64> @vwmul_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
297; CHECK-LABEL: vwmul_vx_nxv8i64:
298; CHECK:       # %bb.0:
299; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
300; CHECK-NEXT:    vwmul.vx v16, v8, a0
301; CHECK-NEXT:    vmv8r.v v8, v16
302; CHECK-NEXT:    ret
303  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
304  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
305  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
306  %vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
307  %ve = mul <vscale x 8 x i64> %vc, %vd
308  ret <vscale x 8 x i64> %ve
309}
310
311define <vscale x 8 x i64> @vwmulu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
312; CHECK-LABEL: vwmulu_vx_nxv8i64:
313; CHECK:       # %bb.0:
314; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
315; CHECK-NEXT:    vwmulu.vx v16, v8, a0
316; CHECK-NEXT:    vmv8r.v v8, v16
317; CHECK-NEXT:    ret
318  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
319  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
320  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
321  %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
322  %ve = mul <vscale x 8 x i64> %vc, %vd
323  ret <vscale x 8 x i64> %ve
324}
325
326define <vscale x 8 x i64> @vwmulsu_vx_nxv8i64(<vscale x 8 x i32> %va, i32 %b) {
327; CHECK-LABEL: vwmulsu_vx_nxv8i64:
328; CHECK:       # %bb.0:
329; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
330; CHECK-NEXT:    vwmulsu.vx v16, v8, a0
331; CHECK-NEXT:    vmv8r.v v8, v16
332; CHECK-NEXT:    ret
333  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
334  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
335  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
336  %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
337  %ve = mul <vscale x 8 x i64> %vc, %vd
338  ret <vscale x 8 x i64> %ve
339}
340