1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 4 5define <vscale x 1 x i8> @vremu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) { 6; CHECK-LABEL: vremu_vv_nxv1i8: 7; CHECK: # %bb.0: 8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 9; CHECK-NEXT: vremu.vv v8, v8, v9 10; CHECK-NEXT: ret 11 %vc = urem <vscale x 1 x i8> %va, %vb 12 ret <vscale x 1 x i8> %vc 13} 14 15define <vscale x 1 x i8> @vremu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) { 16; CHECK-LABEL: vremu_vx_nxv1i8: 17; CHECK: # %bb.0: 18; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 19; CHECK-NEXT: vremu.vx v8, v8, a0 20; CHECK-NEXT: ret 21 %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0 22 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer 23 %vc = urem <vscale x 1 x i8> %va, %splat 24 ret <vscale x 1 x i8> %vc 25} 26 27define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) { 28; CHECK-LABEL: vremu_vi_nxv1i8_0: 29; CHECK: # %bb.0: 30; CHECK-NEXT: addi a0, zero, 33 31; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 32; CHECK-NEXT: vmulhu.vx v9, v8, a0 33; CHECK-NEXT: vsrl.vi v9, v9, 5 34; CHECK-NEXT: addi a0, zero, -7 35; CHECK-NEXT: vnmsac.vx v8, a0, v9 36; CHECK-NEXT: ret 37 %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0 38 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer 39 %vc = urem <vscale x 1 x i8> %va, %splat 40 ret <vscale x 1 x i8> %vc 41} 42 43define <vscale x 2 x i8> @vremu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) { 44; CHECK-LABEL: vremu_vv_nxv2i8: 45; CHECK: # %bb.0: 46; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu 47; CHECK-NEXT: vremu.vv v8, v8, v9 48; CHECK-NEXT: ret 49 %vc = urem <vscale x 2 x i8> %va, %vb 50 ret <vscale x 2 x i8> %vc 51} 52 53define <vscale x 2 x i8> @vremu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) { 54; CHECK-LABEL: vremu_vx_nxv2i8: 55; CHECK: # %bb.0: 56; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 57; CHECK-NEXT: vremu.vx v8, v8, a0 58; CHECK-NEXT: ret 59 %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0 60 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer 61 %vc = urem <vscale x 2 x i8> %va, %splat 62 ret <vscale x 2 x i8> %vc 63} 64 65define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) { 66; CHECK-LABEL: vremu_vi_nxv2i8_0: 67; CHECK: # %bb.0: 68; CHECK-NEXT: addi a0, zero, 33 69; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 70; CHECK-NEXT: vmulhu.vx v9, v8, a0 71; CHECK-NEXT: vsrl.vi v9, v9, 5 72; CHECK-NEXT: addi a0, zero, -7 73; CHECK-NEXT: vnmsac.vx v8, a0, v9 74; CHECK-NEXT: ret 75 %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0 76 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer 77 %vc = urem <vscale x 2 x i8> %va, %splat 78 ret <vscale x 2 x i8> %vc 79} 80 81define <vscale x 4 x i8> @vremu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) { 82; CHECK-LABEL: vremu_vv_nxv4i8: 83; CHECK: # %bb.0: 84; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 85; CHECK-NEXT: vremu.vv v8, v8, v9 86; CHECK-NEXT: ret 87 %vc = urem <vscale x 4 x i8> %va, %vb 88 ret <vscale x 4 x i8> %vc 89} 90 91define <vscale x 4 x i8> @vremu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) { 92; CHECK-LABEL: vremu_vx_nxv4i8: 93; CHECK: # %bb.0: 94; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 95; CHECK-NEXT: vremu.vx v8, v8, a0 96; CHECK-NEXT: ret 97 %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0 98 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer 99 %vc = urem <vscale x 4 x i8> %va, %splat 100 ret <vscale x 4 x i8> %vc 101} 102 103define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) { 104; CHECK-LABEL: vremu_vi_nxv4i8_0: 105; CHECK: # %bb.0: 106; CHECK-NEXT: addi a0, zero, 33 107; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 108; CHECK-NEXT: vmulhu.vx v9, v8, a0 109; CHECK-NEXT: vsrl.vi v9, v9, 5 110; CHECK-NEXT: addi a0, zero, -7 111; CHECK-NEXT: vnmsac.vx v8, a0, v9 112; CHECK-NEXT: ret 113 %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0 114 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer 115 %vc = urem <vscale x 4 x i8> %va, %splat 116 ret <vscale x 4 x i8> %vc 117} 118 119define <vscale x 8 x i8> @vremu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 120; CHECK-LABEL: vremu_vv_nxv8i8: 121; CHECK: # %bb.0: 122; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 123; CHECK-NEXT: vremu.vv v8, v8, v9 124; CHECK-NEXT: ret 125 %vc = urem <vscale x 8 x i8> %va, %vb 126 ret <vscale x 8 x i8> %vc 127} 128 129define <vscale x 8 x i8> @vremu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) { 130; CHECK-LABEL: vremu_vx_nxv8i8: 131; CHECK: # %bb.0: 132; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 133; CHECK-NEXT: vremu.vx v8, v8, a0 134; CHECK-NEXT: ret 135 %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0 136 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer 137 %vc = urem <vscale x 8 x i8> %va, %splat 138 ret <vscale x 8 x i8> %vc 139} 140 141define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 142; CHECK-LABEL: vremu_vi_nxv8i8_0: 143; CHECK: # %bb.0: 144; CHECK-NEXT: addi a0, zero, 33 145; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 146; CHECK-NEXT: vmulhu.vx v9, v8, a0 147; CHECK-NEXT: vsrl.vi v9, v9, 5 148; CHECK-NEXT: addi a0, zero, -7 149; CHECK-NEXT: vnmsac.vx v8, a0, v9 150; CHECK-NEXT: ret 151 %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0 152 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer 153 %vc = urem <vscale x 8 x i8> %va, %splat 154 ret <vscale x 8 x i8> %vc 155} 156 157define <vscale x 16 x i8> @vremu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) { 158; CHECK-LABEL: vremu_vv_nxv16i8: 159; CHECK: # %bb.0: 160; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu 161; CHECK-NEXT: vremu.vv v8, v8, v10 162; CHECK-NEXT: ret 163 %vc = urem <vscale x 16 x i8> %va, %vb 164 ret <vscale x 16 x i8> %vc 165} 166 167define <vscale x 16 x i8> @vremu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) { 168; CHECK-LABEL: vremu_vx_nxv16i8: 169; CHECK: # %bb.0: 170; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 171; CHECK-NEXT: vremu.vx v8, v8, a0 172; CHECK-NEXT: ret 173 %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0 174 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 175 %vc = urem <vscale x 16 x i8> %va, %splat 176 ret <vscale x 16 x i8> %vc 177} 178 179define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) { 180; CHECK-LABEL: vremu_vi_nxv16i8_0: 181; CHECK: # %bb.0: 182; CHECK-NEXT: addi a0, zero, 33 183; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 184; CHECK-NEXT: vmulhu.vx v10, v8, a0 185; CHECK-NEXT: vsrl.vi v10, v10, 5 186; CHECK-NEXT: addi a0, zero, -7 187; CHECK-NEXT: vnmsac.vx v8, a0, v10 188; CHECK-NEXT: ret 189 %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0 190 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 191 %vc = urem <vscale x 16 x i8> %va, %splat 192 ret <vscale x 16 x i8> %vc 193} 194 195define <vscale x 32 x i8> @vremu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) { 196; CHECK-LABEL: vremu_vv_nxv32i8: 197; CHECK: # %bb.0: 198; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu 199; CHECK-NEXT: vremu.vv v8, v8, v12 200; CHECK-NEXT: ret 201 %vc = urem <vscale x 32 x i8> %va, %vb 202 ret <vscale x 32 x i8> %vc 203} 204 205define <vscale x 32 x i8> @vremu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) { 206; CHECK-LABEL: vremu_vx_nxv32i8: 207; CHECK: # %bb.0: 208; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 209; CHECK-NEXT: vremu.vx v8, v8, a0 210; CHECK-NEXT: ret 211 %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0 212 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer 213 %vc = urem <vscale x 32 x i8> %va, %splat 214 ret <vscale x 32 x i8> %vc 215} 216 217define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) { 218; CHECK-LABEL: vremu_vi_nxv32i8_0: 219; CHECK: # %bb.0: 220; CHECK-NEXT: addi a0, zero, 33 221; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 222; CHECK-NEXT: vmulhu.vx v12, v8, a0 223; CHECK-NEXT: vsrl.vi v12, v12, 5 224; CHECK-NEXT: addi a0, zero, -7 225; CHECK-NEXT: vnmsac.vx v8, a0, v12 226; CHECK-NEXT: ret 227 %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0 228 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer 229 %vc = urem <vscale x 32 x i8> %va, %splat 230 ret <vscale x 32 x i8> %vc 231} 232 233define <vscale x 64 x i8> @vremu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) { 234; CHECK-LABEL: vremu_vv_nxv64i8: 235; CHECK: # %bb.0: 236; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu 237; CHECK-NEXT: vremu.vv v8, v8, v16 238; CHECK-NEXT: ret 239 %vc = urem <vscale x 64 x i8> %va, %vb 240 ret <vscale x 64 x i8> %vc 241} 242 243define <vscale x 64 x i8> @vremu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) { 244; CHECK-LABEL: vremu_vx_nxv64i8: 245; CHECK: # %bb.0: 246; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 247; CHECK-NEXT: vremu.vx v8, v8, a0 248; CHECK-NEXT: ret 249 %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0 250 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer 251 %vc = urem <vscale x 64 x i8> %va, %splat 252 ret <vscale x 64 x i8> %vc 253} 254 255define <vscale x 64 x i8> @vremu_vi_nxv64i8_0(<vscale x 64 x i8> %va) { 256; CHECK-LABEL: vremu_vi_nxv64i8_0: 257; CHECK: # %bb.0: 258; CHECK-NEXT: addi a0, zero, 33 259; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 260; CHECK-NEXT: vmulhu.vx v16, v8, a0 261; CHECK-NEXT: vsrl.vi v16, v16, 5 262; CHECK-NEXT: addi a0, zero, -7 263; CHECK-NEXT: vnmsac.vx v8, a0, v16 264; CHECK-NEXT: ret 265 %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0 266 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer 267 %vc = urem <vscale x 64 x i8> %va, %splat 268 ret <vscale x 64 x i8> %vc 269} 270 271define <vscale x 1 x i16> @vremu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) { 272; CHECK-LABEL: vremu_vv_nxv1i16: 273; CHECK: # %bb.0: 274; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu 275; CHECK-NEXT: vremu.vv v8, v8, v9 276; CHECK-NEXT: ret 277 %vc = urem <vscale x 1 x i16> %va, %vb 278 ret <vscale x 1 x i16> %vc 279} 280 281define <vscale x 1 x i16> @vremu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) { 282; CHECK-LABEL: vremu_vx_nxv1i16: 283; CHECK: # %bb.0: 284; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 285; CHECK-NEXT: vremu.vx v8, v8, a0 286; CHECK-NEXT: ret 287 %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0 288 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer 289 %vc = urem <vscale x 1 x i16> %va, %splat 290 ret <vscale x 1 x i16> %vc 291} 292 293define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) { 294; RV32-LABEL: vremu_vi_nxv1i16_0: 295; RV32: # %bb.0: 296; RV32-NEXT: lui a0, 2 297; RV32-NEXT: addi a0, a0, 1 298; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 299; RV32-NEXT: vmulhu.vx v9, v8, a0 300; RV32-NEXT: vsrl.vi v9, v9, 13 301; RV32-NEXT: addi a0, zero, -7 302; RV32-NEXT: vnmsac.vx v8, a0, v9 303; RV32-NEXT: ret 304; 305; RV64-LABEL: vremu_vi_nxv1i16_0: 306; RV64: # %bb.0: 307; RV64-NEXT: lui a0, 2 308; RV64-NEXT: addiw a0, a0, 1 309; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 310; RV64-NEXT: vmulhu.vx v9, v8, a0 311; RV64-NEXT: vsrl.vi v9, v9, 13 312; RV64-NEXT: addi a0, zero, -7 313; RV64-NEXT: vnmsac.vx v8, a0, v9 314; RV64-NEXT: ret 315 %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0 316 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer 317 %vc = urem <vscale x 1 x i16> %va, %splat 318 ret <vscale x 1 x i16> %vc 319} 320 321define <vscale x 2 x i16> @vremu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) { 322; CHECK-LABEL: vremu_vv_nxv2i16: 323; CHECK: # %bb.0: 324; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu 325; CHECK-NEXT: vremu.vv v8, v8, v9 326; CHECK-NEXT: ret 327 %vc = urem <vscale x 2 x i16> %va, %vb 328 ret <vscale x 2 x i16> %vc 329} 330 331define <vscale x 2 x i16> @vremu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) { 332; CHECK-LABEL: vremu_vx_nxv2i16: 333; CHECK: # %bb.0: 334; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 335; CHECK-NEXT: vremu.vx v8, v8, a0 336; CHECK-NEXT: ret 337 %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0 338 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer 339 %vc = urem <vscale x 2 x i16> %va, %splat 340 ret <vscale x 2 x i16> %vc 341} 342 343define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) { 344; RV32-LABEL: vremu_vi_nxv2i16_0: 345; RV32: # %bb.0: 346; RV32-NEXT: lui a0, 2 347; RV32-NEXT: addi a0, a0, 1 348; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 349; RV32-NEXT: vmulhu.vx v9, v8, a0 350; RV32-NEXT: vsrl.vi v9, v9, 13 351; RV32-NEXT: addi a0, zero, -7 352; RV32-NEXT: vnmsac.vx v8, a0, v9 353; RV32-NEXT: ret 354; 355; RV64-LABEL: vremu_vi_nxv2i16_0: 356; RV64: # %bb.0: 357; RV64-NEXT: lui a0, 2 358; RV64-NEXT: addiw a0, a0, 1 359; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 360; RV64-NEXT: vmulhu.vx v9, v8, a0 361; RV64-NEXT: vsrl.vi v9, v9, 13 362; RV64-NEXT: addi a0, zero, -7 363; RV64-NEXT: vnmsac.vx v8, a0, v9 364; RV64-NEXT: ret 365 %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0 366 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer 367 %vc = urem <vscale x 2 x i16> %va, %splat 368 ret <vscale x 2 x i16> %vc 369} 370 371define <vscale x 4 x i16> @vremu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) { 372; CHECK-LABEL: vremu_vv_nxv4i16: 373; CHECK: # %bb.0: 374; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu 375; CHECK-NEXT: vremu.vv v8, v8, v9 376; CHECK-NEXT: ret 377 %vc = urem <vscale x 4 x i16> %va, %vb 378 ret <vscale x 4 x i16> %vc 379} 380 381define <vscale x 4 x i16> @vremu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) { 382; CHECK-LABEL: vremu_vx_nxv4i16: 383; CHECK: # %bb.0: 384; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu 385; CHECK-NEXT: vremu.vx v8, v8, a0 386; CHECK-NEXT: ret 387 %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0 388 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer 389 %vc = urem <vscale x 4 x i16> %va, %splat 390 ret <vscale x 4 x i16> %vc 391} 392 393define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) { 394; RV32-LABEL: vremu_vi_nxv4i16_0: 395; RV32: # %bb.0: 396; RV32-NEXT: lui a0, 2 397; RV32-NEXT: addi a0, a0, 1 398; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu 399; RV32-NEXT: vmulhu.vx v9, v8, a0 400; RV32-NEXT: vsrl.vi v9, v9, 13 401; RV32-NEXT: addi a0, zero, -7 402; RV32-NEXT: vnmsac.vx v8, a0, v9 403; RV32-NEXT: ret 404; 405; RV64-LABEL: vremu_vi_nxv4i16_0: 406; RV64: # %bb.0: 407; RV64-NEXT: lui a0, 2 408; RV64-NEXT: addiw a0, a0, 1 409; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu 410; RV64-NEXT: vmulhu.vx v9, v8, a0 411; RV64-NEXT: vsrl.vi v9, v9, 13 412; RV64-NEXT: addi a0, zero, -7 413; RV64-NEXT: vnmsac.vx v8, a0, v9 414; RV64-NEXT: ret 415 %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0 416 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer 417 %vc = urem <vscale x 4 x i16> %va, %splat 418 ret <vscale x 4 x i16> %vc 419} 420 421define <vscale x 8 x i16> @vremu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 422; CHECK-LABEL: vremu_vv_nxv8i16: 423; CHECK: # %bb.0: 424; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu 425; CHECK-NEXT: vremu.vv v8, v8, v10 426; CHECK-NEXT: ret 427 %vc = urem <vscale x 8 x i16> %va, %vb 428 ret <vscale x 8 x i16> %vc 429} 430 431define <vscale x 8 x i16> @vremu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) { 432; CHECK-LABEL: vremu_vx_nxv8i16: 433; CHECK: # %bb.0: 434; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu 435; CHECK-NEXT: vremu.vx v8, v8, a0 436; CHECK-NEXT: ret 437 %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0 438 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 439 %vc = urem <vscale x 8 x i16> %va, %splat 440 ret <vscale x 8 x i16> %vc 441} 442 443define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 444; RV32-LABEL: vremu_vi_nxv8i16_0: 445; RV32: # %bb.0: 446; RV32-NEXT: lui a0, 2 447; RV32-NEXT: addi a0, a0, 1 448; RV32-NEXT: vsetvli a1, zero, e16, m2, ta, mu 449; RV32-NEXT: vmulhu.vx v10, v8, a0 450; RV32-NEXT: vsrl.vi v10, v10, 13 451; RV32-NEXT: addi a0, zero, -7 452; RV32-NEXT: vnmsac.vx v8, a0, v10 453; RV32-NEXT: ret 454; 455; RV64-LABEL: vremu_vi_nxv8i16_0: 456; RV64: # %bb.0: 457; RV64-NEXT: lui a0, 2 458; RV64-NEXT: addiw a0, a0, 1 459; RV64-NEXT: vsetvli a1, zero, e16, m2, ta, mu 460; RV64-NEXT: vmulhu.vx v10, v8, a0 461; RV64-NEXT: vsrl.vi v10, v10, 13 462; RV64-NEXT: addi a0, zero, -7 463; RV64-NEXT: vnmsac.vx v8, a0, v10 464; RV64-NEXT: ret 465 %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0 466 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 467 %vc = urem <vscale x 8 x i16> %va, %splat 468 ret <vscale x 8 x i16> %vc 469} 470 471define <vscale x 16 x i16> @vremu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) { 472; CHECK-LABEL: vremu_vv_nxv16i16: 473; CHECK: # %bb.0: 474; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 475; CHECK-NEXT: vremu.vv v8, v8, v12 476; CHECK-NEXT: ret 477 %vc = urem <vscale x 16 x i16> %va, %vb 478 ret <vscale x 16 x i16> %vc 479} 480 481define <vscale x 16 x i16> @vremu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) { 482; CHECK-LABEL: vremu_vx_nxv16i16: 483; CHECK: # %bb.0: 484; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu 485; CHECK-NEXT: vremu.vx v8, v8, a0 486; CHECK-NEXT: ret 487 %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0 488 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer 489 %vc = urem <vscale x 16 x i16> %va, %splat 490 ret <vscale x 16 x i16> %vc 491} 492 493define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) { 494; RV32-LABEL: vremu_vi_nxv16i16_0: 495; RV32: # %bb.0: 496; RV32-NEXT: lui a0, 2 497; RV32-NEXT: addi a0, a0, 1 498; RV32-NEXT: vsetvli a1, zero, e16, m4, ta, mu 499; RV32-NEXT: vmulhu.vx v12, v8, a0 500; RV32-NEXT: vsrl.vi v12, v12, 13 501; RV32-NEXT: addi a0, zero, -7 502; RV32-NEXT: vnmsac.vx v8, a0, v12 503; RV32-NEXT: ret 504; 505; RV64-LABEL: vremu_vi_nxv16i16_0: 506; RV64: # %bb.0: 507; RV64-NEXT: lui a0, 2 508; RV64-NEXT: addiw a0, a0, 1 509; RV64-NEXT: vsetvli a1, zero, e16, m4, ta, mu 510; RV64-NEXT: vmulhu.vx v12, v8, a0 511; RV64-NEXT: vsrl.vi v12, v12, 13 512; RV64-NEXT: addi a0, zero, -7 513; RV64-NEXT: vnmsac.vx v8, a0, v12 514; RV64-NEXT: ret 515 %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0 516 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer 517 %vc = urem <vscale x 16 x i16> %va, %splat 518 ret <vscale x 16 x i16> %vc 519} 520 521define <vscale x 32 x i16> @vremu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) { 522; CHECK-LABEL: vremu_vv_nxv32i16: 523; CHECK: # %bb.0: 524; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu 525; CHECK-NEXT: vremu.vv v8, v8, v16 526; CHECK-NEXT: ret 527 %vc = urem <vscale x 32 x i16> %va, %vb 528 ret <vscale x 32 x i16> %vc 529} 530 531define <vscale x 32 x i16> @vremu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) { 532; CHECK-LABEL: vremu_vx_nxv32i16: 533; CHECK: # %bb.0: 534; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu 535; CHECK-NEXT: vremu.vx v8, v8, a0 536; CHECK-NEXT: ret 537 %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0 538 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer 539 %vc = urem <vscale x 32 x i16> %va, %splat 540 ret <vscale x 32 x i16> %vc 541} 542 543define <vscale x 32 x i16> @vremu_vi_nxv32i16_0(<vscale x 32 x i16> %va) { 544; RV32-LABEL: vremu_vi_nxv32i16_0: 545; RV32: # %bb.0: 546; RV32-NEXT: lui a0, 2 547; RV32-NEXT: addi a0, a0, 1 548; RV32-NEXT: vsetvli a1, zero, e16, m8, ta, mu 549; RV32-NEXT: vmulhu.vx v16, v8, a0 550; RV32-NEXT: vsrl.vi v16, v16, 13 551; RV32-NEXT: addi a0, zero, -7 552; RV32-NEXT: vnmsac.vx v8, a0, v16 553; RV32-NEXT: ret 554; 555; RV64-LABEL: vremu_vi_nxv32i16_0: 556; RV64: # %bb.0: 557; RV64-NEXT: lui a0, 2 558; RV64-NEXT: addiw a0, a0, 1 559; RV64-NEXT: vsetvli a1, zero, e16, m8, ta, mu 560; RV64-NEXT: vmulhu.vx v16, v8, a0 561; RV64-NEXT: vsrl.vi v16, v16, 13 562; RV64-NEXT: addi a0, zero, -7 563; RV64-NEXT: vnmsac.vx v8, a0, v16 564; RV64-NEXT: ret 565 %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0 566 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer 567 %vc = urem <vscale x 32 x i16> %va, %splat 568 ret <vscale x 32 x i16> %vc 569} 570 571define <vscale x 1 x i32> @vremu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) { 572; CHECK-LABEL: vremu_vv_nxv1i32: 573; CHECK: # %bb.0: 574; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu 575; CHECK-NEXT: vremu.vv v8, v8, v9 576; CHECK-NEXT: ret 577 %vc = urem <vscale x 1 x i32> %va, %vb 578 ret <vscale x 1 x i32> %vc 579} 580 581define <vscale x 1 x i32> @vremu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) { 582; CHECK-LABEL: vremu_vx_nxv1i32: 583; CHECK: # %bb.0: 584; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 585; CHECK-NEXT: vremu.vx v8, v8, a0 586; CHECK-NEXT: ret 587 %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0 588 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer 589 %vc = urem <vscale x 1 x i32> %va, %splat 590 ret <vscale x 1 x i32> %vc 591} 592 593define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) { 594; RV32-LABEL: vremu_vi_nxv1i32_0: 595; RV32: # %bb.0: 596; RV32-NEXT: lui a0, 131072 597; RV32-NEXT: addi a0, a0, 1 598; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 599; RV32-NEXT: vmulhu.vx v9, v8, a0 600; RV32-NEXT: vsrl.vi v9, v9, 29 601; RV32-NEXT: addi a0, zero, -7 602; RV32-NEXT: vnmsac.vx v8, a0, v9 603; RV32-NEXT: ret 604; 605; RV64-LABEL: vremu_vi_nxv1i32_0: 606; RV64: # %bb.0: 607; RV64-NEXT: lui a0, 131072 608; RV64-NEXT: addiw a0, a0, 1 609; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 610; RV64-NEXT: vmulhu.vx v9, v8, a0 611; RV64-NEXT: vsrl.vi v9, v9, 29 612; RV64-NEXT: addi a0, zero, -7 613; RV64-NEXT: vnmsac.vx v8, a0, v9 614; RV64-NEXT: ret 615 %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0 616 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer 617 %vc = urem <vscale x 1 x i32> %va, %splat 618 ret <vscale x 1 x i32> %vc 619} 620 621define <vscale x 2 x i32> @vremu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) { 622; CHECK-LABEL: vremu_vv_nxv2i32: 623; CHECK: # %bb.0: 624; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu 625; CHECK-NEXT: vremu.vv v8, v8, v9 626; CHECK-NEXT: ret 627 %vc = urem <vscale x 2 x i32> %va, %vb 628 ret <vscale x 2 x i32> %vc 629} 630 631define <vscale x 2 x i32> @vremu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) { 632; CHECK-LABEL: vremu_vx_nxv2i32: 633; CHECK: # %bb.0: 634; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu 635; CHECK-NEXT: vremu.vx v8, v8, a0 636; CHECK-NEXT: ret 637 %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0 638 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer 639 %vc = urem <vscale x 2 x i32> %va, %splat 640 ret <vscale x 2 x i32> %vc 641} 642 643define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) { 644; RV32-LABEL: vremu_vi_nxv2i32_0: 645; RV32: # %bb.0: 646; RV32-NEXT: lui a0, 131072 647; RV32-NEXT: addi a0, a0, 1 648; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu 649; RV32-NEXT: vmulhu.vx v9, v8, a0 650; RV32-NEXT: vsrl.vi v9, v9, 29 651; RV32-NEXT: addi a0, zero, -7 652; RV32-NEXT: vnmsac.vx v8, a0, v9 653; RV32-NEXT: ret 654; 655; RV64-LABEL: vremu_vi_nxv2i32_0: 656; RV64: # %bb.0: 657; RV64-NEXT: lui a0, 131072 658; RV64-NEXT: addiw a0, a0, 1 659; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu 660; RV64-NEXT: vmulhu.vx v9, v8, a0 661; RV64-NEXT: vsrl.vi v9, v9, 29 662; RV64-NEXT: addi a0, zero, -7 663; RV64-NEXT: vnmsac.vx v8, a0, v9 664; RV64-NEXT: ret 665 %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0 666 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer 667 %vc = urem <vscale x 2 x i32> %va, %splat 668 ret <vscale x 2 x i32> %vc 669} 670 671define <vscale x 4 x i32> @vremu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) { 672; CHECK-LABEL: vremu_vv_nxv4i32: 673; CHECK: # %bb.0: 674; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu 675; CHECK-NEXT: vremu.vv v8, v8, v10 676; CHECK-NEXT: ret 677 %vc = urem <vscale x 4 x i32> %va, %vb 678 ret <vscale x 4 x i32> %vc 679} 680 681define <vscale x 4 x i32> @vremu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) { 682; CHECK-LABEL: vremu_vx_nxv4i32: 683; CHECK: # %bb.0: 684; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu 685; CHECK-NEXT: vremu.vx v8, v8, a0 686; CHECK-NEXT: ret 687 %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0 688 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 689 %vc = urem <vscale x 4 x i32> %va, %splat 690 ret <vscale x 4 x i32> %vc 691} 692 693define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) { 694; RV32-LABEL: vremu_vi_nxv4i32_0: 695; RV32: # %bb.0: 696; RV32-NEXT: lui a0, 131072 697; RV32-NEXT: addi a0, a0, 1 698; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu 699; RV32-NEXT: vmulhu.vx v10, v8, a0 700; RV32-NEXT: vsrl.vi v10, v10, 29 701; RV32-NEXT: addi a0, zero, -7 702; RV32-NEXT: vnmsac.vx v8, a0, v10 703; RV32-NEXT: ret 704; 705; RV64-LABEL: vremu_vi_nxv4i32_0: 706; RV64: # %bb.0: 707; RV64-NEXT: lui a0, 131072 708; RV64-NEXT: addiw a0, a0, 1 709; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, mu 710; RV64-NEXT: vmulhu.vx v10, v8, a0 711; RV64-NEXT: vsrl.vi v10, v10, 29 712; RV64-NEXT: addi a0, zero, -7 713; RV64-NEXT: vnmsac.vx v8, a0, v10 714; RV64-NEXT: ret 715 %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0 716 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 717 %vc = urem <vscale x 4 x i32> %va, %splat 718 ret <vscale x 4 x i32> %vc 719} 720 721define <vscale x 8 x i32> @vremu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 722; CHECK-LABEL: vremu_vv_nxv8i32: 723; CHECK: # %bb.0: 724; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu 725; CHECK-NEXT: vremu.vv v8, v8, v12 726; CHECK-NEXT: ret 727 %vc = urem <vscale x 8 x i32> %va, %vb 728 ret <vscale x 8 x i32> %vc 729} 730 731define <vscale x 8 x i32> @vremu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) { 732; CHECK-LABEL: vremu_vx_nxv8i32: 733; CHECK: # %bb.0: 734; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu 735; CHECK-NEXT: vremu.vx v8, v8, a0 736; CHECK-NEXT: ret 737 %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0 738 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer 739 %vc = urem <vscale x 8 x i32> %va, %splat 740 ret <vscale x 8 x i32> %vc 741} 742 743define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 744; RV32-LABEL: vremu_vi_nxv8i32_0: 745; RV32: # %bb.0: 746; RV32-NEXT: lui a0, 131072 747; RV32-NEXT: addi a0, a0, 1 748; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu 749; RV32-NEXT: vmulhu.vx v12, v8, a0 750; RV32-NEXT: vsrl.vi v12, v12, 29 751; RV32-NEXT: addi a0, zero, -7 752; RV32-NEXT: vnmsac.vx v8, a0, v12 753; RV32-NEXT: ret 754; 755; RV64-LABEL: vremu_vi_nxv8i32_0: 756; RV64: # %bb.0: 757; RV64-NEXT: lui a0, 131072 758; RV64-NEXT: addiw a0, a0, 1 759; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, mu 760; RV64-NEXT: vmulhu.vx v12, v8, a0 761; RV64-NEXT: vsrl.vi v12, v12, 29 762; RV64-NEXT: addi a0, zero, -7 763; RV64-NEXT: vnmsac.vx v8, a0, v12 764; RV64-NEXT: ret 765 %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0 766 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer 767 %vc = urem <vscale x 8 x i32> %va, %splat 768 ret <vscale x 8 x i32> %vc 769} 770 771define <vscale x 16 x i32> @vremu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) { 772; CHECK-LABEL: vremu_vv_nxv16i32: 773; CHECK: # %bb.0: 774; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 775; CHECK-NEXT: vremu.vv v8, v8, v16 776; CHECK-NEXT: ret 777 %vc = urem <vscale x 16 x i32> %va, %vb 778 ret <vscale x 16 x i32> %vc 779} 780 781define <vscale x 16 x i32> @vremu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) { 782; CHECK-LABEL: vremu_vx_nxv16i32: 783; CHECK: # %bb.0: 784; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu 785; CHECK-NEXT: vremu.vx v8, v8, a0 786; CHECK-NEXT: ret 787 %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0 788 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer 789 %vc = urem <vscale x 16 x i32> %va, %splat 790 ret <vscale x 16 x i32> %vc 791} 792 793define <vscale x 16 x i32> @vremu_vi_nxv16i32_0(<vscale x 16 x i32> %va) { 794; RV32-LABEL: vremu_vi_nxv16i32_0: 795; RV32: # %bb.0: 796; RV32-NEXT: lui a0, 131072 797; RV32-NEXT: addi a0, a0, 1 798; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, mu 799; RV32-NEXT: vmulhu.vx v16, v8, a0 800; RV32-NEXT: vsrl.vi v16, v16, 29 801; RV32-NEXT: addi a0, zero, -7 802; RV32-NEXT: vnmsac.vx v8, a0, v16 803; RV32-NEXT: ret 804; 805; RV64-LABEL: vremu_vi_nxv16i32_0: 806; RV64: # %bb.0: 807; RV64-NEXT: lui a0, 131072 808; RV64-NEXT: addiw a0, a0, 1 809; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, mu 810; RV64-NEXT: vmulhu.vx v16, v8, a0 811; RV64-NEXT: vsrl.vi v16, v16, 29 812; RV64-NEXT: addi a0, zero, -7 813; RV64-NEXT: vnmsac.vx v8, a0, v16 814; RV64-NEXT: ret 815 %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0 816 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer 817 %vc = urem <vscale x 16 x i32> %va, %splat 818 ret <vscale x 16 x i32> %vc 819} 820 821define <vscale x 1 x i64> @vremu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) { 822; CHECK-LABEL: vremu_vv_nxv1i64: 823; CHECK: # %bb.0: 824; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 825; CHECK-NEXT: vremu.vv v8, v8, v9 826; CHECK-NEXT: ret 827 %vc = urem <vscale x 1 x i64> %va, %vb 828 ret <vscale x 1 x i64> %vc 829} 830 831define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { 832; RV32-LABEL: vremu_vx_nxv1i64: 833; RV32: # %bb.0: 834; RV32-NEXT: addi sp, sp, -16 835; RV32-NEXT: .cfi_def_cfa_offset 16 836; RV32-NEXT: sw a1, 12(sp) 837; RV32-NEXT: sw a0, 8(sp) 838; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu 839; RV32-NEXT: addi a0, sp, 8 840; RV32-NEXT: vlse64.v v9, (a0), zero 841; RV32-NEXT: vremu.vv v8, v8, v9 842; RV32-NEXT: addi sp, sp, 16 843; RV32-NEXT: ret 844; 845; RV64-LABEL: vremu_vx_nxv1i64: 846; RV64: # %bb.0: 847; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu 848; RV64-NEXT: vremu.vx v8, v8, a0 849; RV64-NEXT: ret 850 %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0 851 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 852 %vc = urem <vscale x 1 x i64> %va, %splat 853 ret <vscale x 1 x i64> %vc 854} 855 856define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) { 857; RV32-LABEL: vremu_vi_nxv1i64_0: 858; RV32: # %bb.0: 859; RV32-NEXT: addi sp, sp, -16 860; RV32-NEXT: .cfi_def_cfa_offset 16 861; RV32-NEXT: lui a0, 131072 862; RV32-NEXT: sw a0, 12(sp) 863; RV32-NEXT: addi a0, zero, 1 864; RV32-NEXT: sw a0, 8(sp) 865; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu 866; RV32-NEXT: addi a0, sp, 8 867; RV32-NEXT: vlse64.v v9, (a0), zero 868; RV32-NEXT: vmulhu.vv v9, v8, v9 869; RV32-NEXT: addi a0, zero, 61 870; RV32-NEXT: vsrl.vx v9, v9, a0 871; RV32-NEXT: addi a0, zero, -7 872; RV32-NEXT: vnmsac.vx v8, a0, v9 873; RV32-NEXT: addi sp, sp, 16 874; RV32-NEXT: ret 875; 876; RV64-LABEL: vremu_vi_nxv1i64_0: 877; RV64: # %bb.0: 878; RV64-NEXT: addi a0, zero, 1 879; RV64-NEXT: slli a0, a0, 61 880; RV64-NEXT: addi a0, a0, 1 881; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu 882; RV64-NEXT: vmulhu.vx v9, v8, a0 883; RV64-NEXT: addi a0, zero, 61 884; RV64-NEXT: vsrl.vx v9, v9, a0 885; RV64-NEXT: addi a0, zero, -7 886; RV64-NEXT: vnmsac.vx v8, a0, v9 887; RV64-NEXT: ret 888 %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0 889 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 890 %vc = urem <vscale x 1 x i64> %va, %splat 891 ret <vscale x 1 x i64> %vc 892} 893 894; fold (urem x, pow2) -> (and x, pow2-1) 895define <vscale x 1 x i64> @vremu_vi_nxv1i64_1(<vscale x 1 x i64> %va) { 896; CHECK-LABEL: vremu_vi_nxv1i64_1: 897; CHECK: # %bb.0: 898; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 899; CHECK-NEXT: vand.vi v8, v8, 15 900; CHECK-NEXT: ret 901 %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0 902 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 903 %vc = urem <vscale x 1 x i64> %va, %splat 904 ret <vscale x 1 x i64> %vc 905} 906 907; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 908define <vscale x 1 x i64> @vremu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) { 909; CHECK-LABEL: vremu_vi_nxv1i64_2: 910; CHECK: # %bb.0: 911; CHECK-NEXT: addi a0, zero, 16 912; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu 913; CHECK-NEXT: vmv.v.x v10, a0 914; CHECK-NEXT: vsll.vv v9, v10, v9 915; CHECK-NEXT: vadd.vi v9, v9, -1 916; CHECK-NEXT: vand.vv v8, v8, v9 917; CHECK-NEXT: ret 918 %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0 919 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 920 %vc = shl <vscale x 1 x i64> %splat, %vb 921 %vd = urem <vscale x 1 x i64> %va, %vc 922 ret <vscale x 1 x i64> %vd 923} 924 925define <vscale x 2 x i64> @vremu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) { 926; CHECK-LABEL: vremu_vv_nxv2i64: 927; CHECK: # %bb.0: 928; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 929; CHECK-NEXT: vremu.vv v8, v8, v10 930; CHECK-NEXT: ret 931 %vc = urem <vscale x 2 x i64> %va, %vb 932 ret <vscale x 2 x i64> %vc 933} 934 935define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { 936; RV32-LABEL: vremu_vx_nxv2i64: 937; RV32: # %bb.0: 938; RV32-NEXT: addi sp, sp, -16 939; RV32-NEXT: .cfi_def_cfa_offset 16 940; RV32-NEXT: sw a1, 12(sp) 941; RV32-NEXT: sw a0, 8(sp) 942; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu 943; RV32-NEXT: addi a0, sp, 8 944; RV32-NEXT: vlse64.v v10, (a0), zero 945; RV32-NEXT: vremu.vv v8, v8, v10 946; RV32-NEXT: addi sp, sp, 16 947; RV32-NEXT: ret 948; 949; RV64-LABEL: vremu_vx_nxv2i64: 950; RV64: # %bb.0: 951; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu 952; RV64-NEXT: vremu.vx v8, v8, a0 953; RV64-NEXT: ret 954 %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0 955 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 956 %vc = urem <vscale x 2 x i64> %va, %splat 957 ret <vscale x 2 x i64> %vc 958} 959 960define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) { 961; RV32-LABEL: vremu_vi_nxv2i64_0: 962; RV32: # %bb.0: 963; RV32-NEXT: addi sp, sp, -16 964; RV32-NEXT: .cfi_def_cfa_offset 16 965; RV32-NEXT: lui a0, 131072 966; RV32-NEXT: sw a0, 12(sp) 967; RV32-NEXT: addi a0, zero, 1 968; RV32-NEXT: sw a0, 8(sp) 969; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu 970; RV32-NEXT: addi a0, sp, 8 971; RV32-NEXT: vlse64.v v10, (a0), zero 972; RV32-NEXT: vmulhu.vv v10, v8, v10 973; RV32-NEXT: addi a0, zero, 61 974; RV32-NEXT: vsrl.vx v10, v10, a0 975; RV32-NEXT: addi a0, zero, -7 976; RV32-NEXT: vnmsac.vx v8, a0, v10 977; RV32-NEXT: addi sp, sp, 16 978; RV32-NEXT: ret 979; 980; RV64-LABEL: vremu_vi_nxv2i64_0: 981; RV64: # %bb.0: 982; RV64-NEXT: addi a0, zero, 1 983; RV64-NEXT: slli a0, a0, 61 984; RV64-NEXT: addi a0, a0, 1 985; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu 986; RV64-NEXT: vmulhu.vx v10, v8, a0 987; RV64-NEXT: addi a0, zero, 61 988; RV64-NEXT: vsrl.vx v10, v10, a0 989; RV64-NEXT: addi a0, zero, -7 990; RV64-NEXT: vnmsac.vx v8, a0, v10 991; RV64-NEXT: ret 992 %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0 993 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 994 %vc = urem <vscale x 2 x i64> %va, %splat 995 ret <vscale x 2 x i64> %vc 996} 997 998; fold (urem x, pow2) -> (and x, pow2-1) 999define <vscale x 2 x i64> @vremu_vi_nxv2i64_1(<vscale x 2 x i64> %va) { 1000; CHECK-LABEL: vremu_vi_nxv2i64_1: 1001; CHECK: # %bb.0: 1002; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 1003; CHECK-NEXT: vand.vi v8, v8, 15 1004; CHECK-NEXT: ret 1005 %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0 1006 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 1007 %vc = urem <vscale x 2 x i64> %va, %splat 1008 ret <vscale x 2 x i64> %vc 1009} 1010 1011; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1012define <vscale x 2 x i64> @vremu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) { 1013; CHECK-LABEL: vremu_vi_nxv2i64_2: 1014; CHECK: # %bb.0: 1015; CHECK-NEXT: addi a0, zero, 16 1016; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu 1017; CHECK-NEXT: vmv.v.x v12, a0 1018; CHECK-NEXT: vsll.vv v10, v12, v10 1019; CHECK-NEXT: vadd.vi v10, v10, -1 1020; CHECK-NEXT: vand.vv v8, v8, v10 1021; CHECK-NEXT: ret 1022 %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0 1023 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 1024 %vc = shl <vscale x 2 x i64> %splat, %vb 1025 %vd = urem <vscale x 2 x i64> %va, %vc 1026 ret <vscale x 2 x i64> %vd 1027} 1028 1029define <vscale x 4 x i64> @vremu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) { 1030; CHECK-LABEL: vremu_vv_nxv4i64: 1031; CHECK: # %bb.0: 1032; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1033; CHECK-NEXT: vremu.vv v8, v8, v12 1034; CHECK-NEXT: ret 1035 %vc = urem <vscale x 4 x i64> %va, %vb 1036 ret <vscale x 4 x i64> %vc 1037} 1038 1039define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { 1040; RV32-LABEL: vremu_vx_nxv4i64: 1041; RV32: # %bb.0: 1042; RV32-NEXT: addi sp, sp, -16 1043; RV32-NEXT: .cfi_def_cfa_offset 16 1044; RV32-NEXT: sw a1, 12(sp) 1045; RV32-NEXT: sw a0, 8(sp) 1046; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1047; RV32-NEXT: addi a0, sp, 8 1048; RV32-NEXT: vlse64.v v12, (a0), zero 1049; RV32-NEXT: vremu.vv v8, v8, v12 1050; RV32-NEXT: addi sp, sp, 16 1051; RV32-NEXT: ret 1052; 1053; RV64-LABEL: vremu_vx_nxv4i64: 1054; RV64: # %bb.0: 1055; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1056; RV64-NEXT: vremu.vx v8, v8, a0 1057; RV64-NEXT: ret 1058 %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0 1059 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 1060 %vc = urem <vscale x 4 x i64> %va, %splat 1061 ret <vscale x 4 x i64> %vc 1062} 1063 1064define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) { 1065; RV32-LABEL: vremu_vi_nxv4i64_0: 1066; RV32: # %bb.0: 1067; RV32-NEXT: addi sp, sp, -16 1068; RV32-NEXT: .cfi_def_cfa_offset 16 1069; RV32-NEXT: lui a0, 131072 1070; RV32-NEXT: sw a0, 12(sp) 1071; RV32-NEXT: addi a0, zero, 1 1072; RV32-NEXT: sw a0, 8(sp) 1073; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1074; RV32-NEXT: addi a0, sp, 8 1075; RV32-NEXT: vlse64.v v12, (a0), zero 1076; RV32-NEXT: vmulhu.vv v12, v8, v12 1077; RV32-NEXT: addi a0, zero, 61 1078; RV32-NEXT: vsrl.vx v12, v12, a0 1079; RV32-NEXT: addi a0, zero, -7 1080; RV32-NEXT: vnmsac.vx v8, a0, v12 1081; RV32-NEXT: addi sp, sp, 16 1082; RV32-NEXT: ret 1083; 1084; RV64-LABEL: vremu_vi_nxv4i64_0: 1085; RV64: # %bb.0: 1086; RV64-NEXT: addi a0, zero, 1 1087; RV64-NEXT: slli a0, a0, 61 1088; RV64-NEXT: addi a0, a0, 1 1089; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1090; RV64-NEXT: vmulhu.vx v12, v8, a0 1091; RV64-NEXT: addi a0, zero, 61 1092; RV64-NEXT: vsrl.vx v12, v12, a0 1093; RV64-NEXT: addi a0, zero, -7 1094; RV64-NEXT: vnmsac.vx v8, a0, v12 1095; RV64-NEXT: ret 1096 %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0 1097 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 1098 %vc = urem <vscale x 4 x i64> %va, %splat 1099 ret <vscale x 4 x i64> %vc 1100} 1101 1102; fold (urem x, pow2) -> (and x, pow2-1) 1103define <vscale x 4 x i64> @vremu_vi_nxv4i64_1(<vscale x 4 x i64> %va) { 1104; CHECK-LABEL: vremu_vi_nxv4i64_1: 1105; CHECK: # %bb.0: 1106; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1107; CHECK-NEXT: vand.vi v8, v8, 15 1108; CHECK-NEXT: ret 1109 %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0 1110 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 1111 %vc = urem <vscale x 4 x i64> %va, %splat 1112 ret <vscale x 4 x i64> %vc 1113} 1114 1115;fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1116define <vscale x 4 x i64> @vremu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) { 1117; CHECK-LABEL: vremu_vi_nxv4i64_2: 1118; CHECK: # %bb.0: 1119; CHECK-NEXT: addi a0, zero, 16 1120; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1121; CHECK-NEXT: vmv.v.x v16, a0 1122; CHECK-NEXT: vsll.vv v12, v16, v12 1123; CHECK-NEXT: vadd.vi v12, v12, -1 1124; CHECK-NEXT: vand.vv v8, v8, v12 1125; CHECK-NEXT: ret 1126 %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0 1127 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 1128 %vc = shl <vscale x 4 x i64> %splat, %vb 1129 %vd = urem <vscale x 4 x i64> %va, %vc 1130 ret <vscale x 4 x i64> %vd 1131} 1132 1133define <vscale x 8 x i64> @vremu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 1134; CHECK-LABEL: vremu_vv_nxv8i64: 1135; CHECK: # %bb.0: 1136; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1137; CHECK-NEXT: vremu.vv v8, v8, v16 1138; CHECK-NEXT: ret 1139 %vc = urem <vscale x 8 x i64> %va, %vb 1140 ret <vscale x 8 x i64> %vc 1141} 1142 1143define <vscale x 8 x i64> @vremu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 1144; RV32-LABEL: vremu_vx_nxv8i64: 1145; RV32: # %bb.0: 1146; RV32-NEXT: addi sp, sp, -16 1147; RV32-NEXT: .cfi_def_cfa_offset 16 1148; RV32-NEXT: sw a1, 12(sp) 1149; RV32-NEXT: sw a0, 8(sp) 1150; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1151; RV32-NEXT: addi a0, sp, 8 1152; RV32-NEXT: vlse64.v v16, (a0), zero 1153; RV32-NEXT: vremu.vv v8, v8, v16 1154; RV32-NEXT: addi sp, sp, 16 1155; RV32-NEXT: ret 1156; 1157; RV64-LABEL: vremu_vx_nxv8i64: 1158; RV64: # %bb.0: 1159; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1160; RV64-NEXT: vremu.vx v8, v8, a0 1161; RV64-NEXT: ret 1162 %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0 1163 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 1164 %vc = urem <vscale x 8 x i64> %va, %splat 1165 ret <vscale x 8 x i64> %vc 1166} 1167 1168define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 1169; RV32-LABEL: vremu_vi_nxv8i64_0: 1170; RV32: # %bb.0: 1171; RV32-NEXT: addi sp, sp, -16 1172; RV32-NEXT: .cfi_def_cfa_offset 16 1173; RV32-NEXT: lui a0, 131072 1174; RV32-NEXT: sw a0, 12(sp) 1175; RV32-NEXT: addi a0, zero, 1 1176; RV32-NEXT: sw a0, 8(sp) 1177; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1178; RV32-NEXT: addi a0, sp, 8 1179; RV32-NEXT: vlse64.v v16, (a0), zero 1180; RV32-NEXT: vmulhu.vv v16, v8, v16 1181; RV32-NEXT: addi a0, zero, 61 1182; RV32-NEXT: vsrl.vx v16, v16, a0 1183; RV32-NEXT: addi a0, zero, -7 1184; RV32-NEXT: vnmsac.vx v8, a0, v16 1185; RV32-NEXT: addi sp, sp, 16 1186; RV32-NEXT: ret 1187; 1188; RV64-LABEL: vremu_vi_nxv8i64_0: 1189; RV64: # %bb.0: 1190; RV64-NEXT: addi a0, zero, 1 1191; RV64-NEXT: slli a0, a0, 61 1192; RV64-NEXT: addi a0, a0, 1 1193; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1194; RV64-NEXT: vmulhu.vx v16, v8, a0 1195; RV64-NEXT: addi a0, zero, 61 1196; RV64-NEXT: vsrl.vx v16, v16, a0 1197; RV64-NEXT: addi a0, zero, -7 1198; RV64-NEXT: vnmsac.vx v8, a0, v16 1199; RV64-NEXT: ret 1200 %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0 1201 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 1202 %vc = urem <vscale x 8 x i64> %va, %splat 1203 ret <vscale x 8 x i64> %vc 1204} 1205 1206; fold (urem x, pow2) -> (and x, pow2-1) 1207define <vscale x 8 x i64> @vremu_vi_nxv8i64_1(<vscale x 8 x i64> %va) { 1208; CHECK-LABEL: vremu_vi_nxv8i64_1: 1209; CHECK: # %bb.0: 1210; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1211; CHECK-NEXT: vand.vi v8, v8, 15 1212; CHECK-NEXT: ret 1213 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 1214 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 1215 %vc = urem <vscale x 8 x i64> %va, %splat 1216 ret <vscale x 8 x i64> %vc 1217} 1218 1219; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1220define <vscale x 8 x i64> @vremu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 1221; CHECK-LABEL: vremu_vi_nxv8i64_2: 1222; CHECK: # %bb.0: 1223; CHECK-NEXT: addi a0, zero, 16 1224; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1225; CHECK-NEXT: vmv.v.x v24, a0 1226; CHECK-NEXT: vsll.vv v16, v24, v16 1227; CHECK-NEXT: vadd.vi v16, v16, -1 1228; CHECK-NEXT: vand.vv v8, v8, v16 1229; CHECK-NEXT: ret 1230 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 1231 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 1232 %vc = shl <vscale x 8 x i64> %splat, %vb 1233 %vd = urem <vscale x 8 x i64> %va, %vc 1234 ret <vscale x 8 x i64> %vd 1235} 1236