1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-V
3; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVE64X
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-V
5; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVE64X
6
7define <vscale x 1 x i8> @vremu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
8; CHECK-LABEL: vremu_vv_nxv1i8:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
11; CHECK-NEXT:    vremu.vv v8, v8, v9
12; CHECK-NEXT:    ret
13  %vc = urem <vscale x 1 x i8> %va, %vb
14  ret <vscale x 1 x i8> %vc
15}
16
17define <vscale x 1 x i8> @vremu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
18; CHECK-LABEL: vremu_vx_nxv1i8:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
21; CHECK-NEXT:    vremu.vx v8, v8, a0
22; CHECK-NEXT:    ret
23  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
24  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
25  %vc = urem <vscale x 1 x i8> %va, %splat
26  ret <vscale x 1 x i8> %vc
27}
28
29define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
30; CHECK-LABEL: vremu_vi_nxv1i8_0:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    li a0, 33
33; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
34; CHECK-NEXT:    vmulhu.vx v9, v8, a0
35; CHECK-NEXT:    vsrl.vi v9, v9, 5
36; CHECK-NEXT:    li a0, -7
37; CHECK-NEXT:    vnmsac.vx v8, a0, v9
38; CHECK-NEXT:    ret
39  %head = insertelement <vscale x 1 x i8> poison, i8 -7, i32 0
40  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
41  %vc = urem <vscale x 1 x i8> %va, %splat
42  ret <vscale x 1 x i8> %vc
43}
44
45define <vscale x 2 x i8> @vremu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
46; CHECK-LABEL: vremu_vv_nxv2i8:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
49; CHECK-NEXT:    vremu.vv v8, v8, v9
50; CHECK-NEXT:    ret
51  %vc = urem <vscale x 2 x i8> %va, %vb
52  ret <vscale x 2 x i8> %vc
53}
54
55define <vscale x 2 x i8> @vremu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
56; CHECK-LABEL: vremu_vx_nxv2i8:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
59; CHECK-NEXT:    vremu.vx v8, v8, a0
60; CHECK-NEXT:    ret
61  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
62  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
63  %vc = urem <vscale x 2 x i8> %va, %splat
64  ret <vscale x 2 x i8> %vc
65}
66
67define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
68; CHECK-LABEL: vremu_vi_nxv2i8_0:
69; CHECK:       # %bb.0:
70; CHECK-NEXT:    li a0, 33
71; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
72; CHECK-NEXT:    vmulhu.vx v9, v8, a0
73; CHECK-NEXT:    vsrl.vi v9, v9, 5
74; CHECK-NEXT:    li a0, -7
75; CHECK-NEXT:    vnmsac.vx v8, a0, v9
76; CHECK-NEXT:    ret
77  %head = insertelement <vscale x 2 x i8> poison, i8 -7, i32 0
78  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
79  %vc = urem <vscale x 2 x i8> %va, %splat
80  ret <vscale x 2 x i8> %vc
81}
82
83define <vscale x 4 x i8> @vremu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
84; CHECK-LABEL: vremu_vv_nxv4i8:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
87; CHECK-NEXT:    vremu.vv v8, v8, v9
88; CHECK-NEXT:    ret
89  %vc = urem <vscale x 4 x i8> %va, %vb
90  ret <vscale x 4 x i8> %vc
91}
92
93define <vscale x 4 x i8> @vremu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
94; CHECK-LABEL: vremu_vx_nxv4i8:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
97; CHECK-NEXT:    vremu.vx v8, v8, a0
98; CHECK-NEXT:    ret
99  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
100  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
101  %vc = urem <vscale x 4 x i8> %va, %splat
102  ret <vscale x 4 x i8> %vc
103}
104
105define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
106; CHECK-LABEL: vremu_vi_nxv4i8_0:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    li a0, 33
109; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
110; CHECK-NEXT:    vmulhu.vx v9, v8, a0
111; CHECK-NEXT:    vsrl.vi v9, v9, 5
112; CHECK-NEXT:    li a0, -7
113; CHECK-NEXT:    vnmsac.vx v8, a0, v9
114; CHECK-NEXT:    ret
115  %head = insertelement <vscale x 4 x i8> poison, i8 -7, i32 0
116  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
117  %vc = urem <vscale x 4 x i8> %va, %splat
118  ret <vscale x 4 x i8> %vc
119}
120
121define <vscale x 8 x i8> @vremu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
122; CHECK-LABEL: vremu_vv_nxv8i8:
123; CHECK:       # %bb.0:
124; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
125; CHECK-NEXT:    vremu.vv v8, v8, v9
126; CHECK-NEXT:    ret
127  %vc = urem <vscale x 8 x i8> %va, %vb
128  ret <vscale x 8 x i8> %vc
129}
130
131define <vscale x 8 x i8> @vremu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
132; CHECK-LABEL: vremu_vx_nxv8i8:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
135; CHECK-NEXT:    vremu.vx v8, v8, a0
136; CHECK-NEXT:    ret
137  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
138  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
139  %vc = urem <vscale x 8 x i8> %va, %splat
140  ret <vscale x 8 x i8> %vc
141}
142
143define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
144; CHECK-LABEL: vremu_vi_nxv8i8_0:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    li a0, 33
147; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
148; CHECK-NEXT:    vmulhu.vx v9, v8, a0
149; CHECK-NEXT:    vsrl.vi v9, v9, 5
150; CHECK-NEXT:    li a0, -7
151; CHECK-NEXT:    vnmsac.vx v8, a0, v9
152; CHECK-NEXT:    ret
153  %head = insertelement <vscale x 8 x i8> poison, i8 -7, i32 0
154  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
155  %vc = urem <vscale x 8 x i8> %va, %splat
156  ret <vscale x 8 x i8> %vc
157}
158
159define <vscale x 16 x i8> @vremu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
160; CHECK-LABEL: vremu_vv_nxv16i8:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
163; CHECK-NEXT:    vremu.vv v8, v8, v10
164; CHECK-NEXT:    ret
165  %vc = urem <vscale x 16 x i8> %va, %vb
166  ret <vscale x 16 x i8> %vc
167}
168
169define <vscale x 16 x i8> @vremu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
170; CHECK-LABEL: vremu_vx_nxv16i8:
171; CHECK:       # %bb.0:
172; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
173; CHECK-NEXT:    vremu.vx v8, v8, a0
174; CHECK-NEXT:    ret
175  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
176  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
177  %vc = urem <vscale x 16 x i8> %va, %splat
178  ret <vscale x 16 x i8> %vc
179}
180
181define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
182; CHECK-LABEL: vremu_vi_nxv16i8_0:
183; CHECK:       # %bb.0:
184; CHECK-NEXT:    li a0, 33
185; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
186; CHECK-NEXT:    vmulhu.vx v10, v8, a0
187; CHECK-NEXT:    vsrl.vi v10, v10, 5
188; CHECK-NEXT:    li a0, -7
189; CHECK-NEXT:    vnmsac.vx v8, a0, v10
190; CHECK-NEXT:    ret
191  %head = insertelement <vscale x 16 x i8> poison, i8 -7, i32 0
192  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
193  %vc = urem <vscale x 16 x i8> %va, %splat
194  ret <vscale x 16 x i8> %vc
195}
196
197define <vscale x 32 x i8> @vremu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
198; CHECK-LABEL: vremu_vv_nxv32i8:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
201; CHECK-NEXT:    vremu.vv v8, v8, v12
202; CHECK-NEXT:    ret
203  %vc = urem <vscale x 32 x i8> %va, %vb
204  ret <vscale x 32 x i8> %vc
205}
206
207define <vscale x 32 x i8> @vremu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
208; CHECK-LABEL: vremu_vx_nxv32i8:
209; CHECK:       # %bb.0:
210; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
211; CHECK-NEXT:    vremu.vx v8, v8, a0
212; CHECK-NEXT:    ret
213  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
214  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
215  %vc = urem <vscale x 32 x i8> %va, %splat
216  ret <vscale x 32 x i8> %vc
217}
218
219define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
220; CHECK-LABEL: vremu_vi_nxv32i8_0:
221; CHECK:       # %bb.0:
222; CHECK-NEXT:    li a0, 33
223; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
224; CHECK-NEXT:    vmulhu.vx v12, v8, a0
225; CHECK-NEXT:    vsrl.vi v12, v12, 5
226; CHECK-NEXT:    li a0, -7
227; CHECK-NEXT:    vnmsac.vx v8, a0, v12
228; CHECK-NEXT:    ret
229  %head = insertelement <vscale x 32 x i8> poison, i8 -7, i32 0
230  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
231  %vc = urem <vscale x 32 x i8> %va, %splat
232  ret <vscale x 32 x i8> %vc
233}
234
235define <vscale x 64 x i8> @vremu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
236; CHECK-LABEL: vremu_vv_nxv64i8:
237; CHECK:       # %bb.0:
238; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
239; CHECK-NEXT:    vremu.vv v8, v8, v16
240; CHECK-NEXT:    ret
241  %vc = urem <vscale x 64 x i8> %va, %vb
242  ret <vscale x 64 x i8> %vc
243}
244
245define <vscale x 64 x i8> @vremu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
246; CHECK-LABEL: vremu_vx_nxv64i8:
247; CHECK:       # %bb.0:
248; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
249; CHECK-NEXT:    vremu.vx v8, v8, a0
250; CHECK-NEXT:    ret
251  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
252  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
253  %vc = urem <vscale x 64 x i8> %va, %splat
254  ret <vscale x 64 x i8> %vc
255}
256
257define <vscale x 64 x i8> @vremu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
258; CHECK-LABEL: vremu_vi_nxv64i8_0:
259; CHECK:       # %bb.0:
260; CHECK-NEXT:    li a0, 33
261; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
262; CHECK-NEXT:    vmulhu.vx v16, v8, a0
263; CHECK-NEXT:    vsrl.vi v16, v16, 5
264; CHECK-NEXT:    li a0, -7
265; CHECK-NEXT:    vnmsac.vx v8, a0, v16
266; CHECK-NEXT:    ret
267  %head = insertelement <vscale x 64 x i8> poison, i8 -7, i32 0
268  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
269  %vc = urem <vscale x 64 x i8> %va, %splat
270  ret <vscale x 64 x i8> %vc
271}
272
273define <vscale x 1 x i16> @vremu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
274; CHECK-LABEL: vremu_vv_nxv1i16:
275; CHECK:       # %bb.0:
276; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
277; CHECK-NEXT:    vremu.vv v8, v8, v9
278; CHECK-NEXT:    ret
279  %vc = urem <vscale x 1 x i16> %va, %vb
280  ret <vscale x 1 x i16> %vc
281}
282
283define <vscale x 1 x i16> @vremu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
284; CHECK-LABEL: vremu_vx_nxv1i16:
285; CHECK:       # %bb.0:
286; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
287; CHECK-NEXT:    vremu.vx v8, v8, a0
288; CHECK-NEXT:    ret
289  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
290  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
291  %vc = urem <vscale x 1 x i16> %va, %splat
292  ret <vscale x 1 x i16> %vc
293}
294
295define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
296; RV32-LABEL: vremu_vi_nxv1i16_0:
297; RV32:       # %bb.0:
298; RV32-NEXT:    lui a0, 2
299; RV32-NEXT:    addi a0, a0, 1
300; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
301; RV32-NEXT:    vmulhu.vx v9, v8, a0
302; RV32-NEXT:    vsrl.vi v9, v9, 13
303; RV32-NEXT:    li a0, -7
304; RV32-NEXT:    vnmsac.vx v8, a0, v9
305; RV32-NEXT:    ret
306;
307; RV64-LABEL: vremu_vi_nxv1i16_0:
308; RV64:       # %bb.0:
309; RV64-NEXT:    lui a0, 2
310; RV64-NEXT:    addiw a0, a0, 1
311; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
312; RV64-NEXT:    vmulhu.vx v9, v8, a0
313; RV64-NEXT:    vsrl.vi v9, v9, 13
314; RV64-NEXT:    li a0, -7
315; RV64-NEXT:    vnmsac.vx v8, a0, v9
316; RV64-NEXT:    ret
317  %head = insertelement <vscale x 1 x i16> poison, i16 -7, i32 0
318  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
319  %vc = urem <vscale x 1 x i16> %va, %splat
320  ret <vscale x 1 x i16> %vc
321}
322
323define <vscale x 2 x i16> @vremu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
324; CHECK-LABEL: vremu_vv_nxv2i16:
325; CHECK:       # %bb.0:
326; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
327; CHECK-NEXT:    vremu.vv v8, v8, v9
328; CHECK-NEXT:    ret
329  %vc = urem <vscale x 2 x i16> %va, %vb
330  ret <vscale x 2 x i16> %vc
331}
332
333define <vscale x 2 x i16> @vremu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
334; CHECK-LABEL: vremu_vx_nxv2i16:
335; CHECK:       # %bb.0:
336; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
337; CHECK-NEXT:    vremu.vx v8, v8, a0
338; CHECK-NEXT:    ret
339  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
340  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
341  %vc = urem <vscale x 2 x i16> %va, %splat
342  ret <vscale x 2 x i16> %vc
343}
344
345define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
346; RV32-LABEL: vremu_vi_nxv2i16_0:
347; RV32:       # %bb.0:
348; RV32-NEXT:    lui a0, 2
349; RV32-NEXT:    addi a0, a0, 1
350; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
351; RV32-NEXT:    vmulhu.vx v9, v8, a0
352; RV32-NEXT:    vsrl.vi v9, v9, 13
353; RV32-NEXT:    li a0, -7
354; RV32-NEXT:    vnmsac.vx v8, a0, v9
355; RV32-NEXT:    ret
356;
357; RV64-LABEL: vremu_vi_nxv2i16_0:
358; RV64:       # %bb.0:
359; RV64-NEXT:    lui a0, 2
360; RV64-NEXT:    addiw a0, a0, 1
361; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
362; RV64-NEXT:    vmulhu.vx v9, v8, a0
363; RV64-NEXT:    vsrl.vi v9, v9, 13
364; RV64-NEXT:    li a0, -7
365; RV64-NEXT:    vnmsac.vx v8, a0, v9
366; RV64-NEXT:    ret
367  %head = insertelement <vscale x 2 x i16> poison, i16 -7, i32 0
368  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
369  %vc = urem <vscale x 2 x i16> %va, %splat
370  ret <vscale x 2 x i16> %vc
371}
372
373define <vscale x 4 x i16> @vremu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
374; CHECK-LABEL: vremu_vv_nxv4i16:
375; CHECK:       # %bb.0:
376; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
377; CHECK-NEXT:    vremu.vv v8, v8, v9
378; CHECK-NEXT:    ret
379  %vc = urem <vscale x 4 x i16> %va, %vb
380  ret <vscale x 4 x i16> %vc
381}
382
383define <vscale x 4 x i16> @vremu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
384; CHECK-LABEL: vremu_vx_nxv4i16:
385; CHECK:       # %bb.0:
386; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
387; CHECK-NEXT:    vremu.vx v8, v8, a0
388; CHECK-NEXT:    ret
389  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
390  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
391  %vc = urem <vscale x 4 x i16> %va, %splat
392  ret <vscale x 4 x i16> %vc
393}
394
395define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
396; RV32-LABEL: vremu_vi_nxv4i16_0:
397; RV32:       # %bb.0:
398; RV32-NEXT:    lui a0, 2
399; RV32-NEXT:    addi a0, a0, 1
400; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
401; RV32-NEXT:    vmulhu.vx v9, v8, a0
402; RV32-NEXT:    vsrl.vi v9, v9, 13
403; RV32-NEXT:    li a0, -7
404; RV32-NEXT:    vnmsac.vx v8, a0, v9
405; RV32-NEXT:    ret
406;
407; RV64-LABEL: vremu_vi_nxv4i16_0:
408; RV64:       # %bb.0:
409; RV64-NEXT:    lui a0, 2
410; RV64-NEXT:    addiw a0, a0, 1
411; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
412; RV64-NEXT:    vmulhu.vx v9, v8, a0
413; RV64-NEXT:    vsrl.vi v9, v9, 13
414; RV64-NEXT:    li a0, -7
415; RV64-NEXT:    vnmsac.vx v8, a0, v9
416; RV64-NEXT:    ret
417  %head = insertelement <vscale x 4 x i16> poison, i16 -7, i32 0
418  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
419  %vc = urem <vscale x 4 x i16> %va, %splat
420  ret <vscale x 4 x i16> %vc
421}
422
423define <vscale x 8 x i16> @vremu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
424; CHECK-LABEL: vremu_vv_nxv8i16:
425; CHECK:       # %bb.0:
426; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
427; CHECK-NEXT:    vremu.vv v8, v8, v10
428; CHECK-NEXT:    ret
429  %vc = urem <vscale x 8 x i16> %va, %vb
430  ret <vscale x 8 x i16> %vc
431}
432
433define <vscale x 8 x i16> @vremu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
434; CHECK-LABEL: vremu_vx_nxv8i16:
435; CHECK:       # %bb.0:
436; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
437; CHECK-NEXT:    vremu.vx v8, v8, a0
438; CHECK-NEXT:    ret
439  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
440  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
441  %vc = urem <vscale x 8 x i16> %va, %splat
442  ret <vscale x 8 x i16> %vc
443}
444
445define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
446; RV32-LABEL: vremu_vi_nxv8i16_0:
447; RV32:       # %bb.0:
448; RV32-NEXT:    lui a0, 2
449; RV32-NEXT:    addi a0, a0, 1
450; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
451; RV32-NEXT:    vmulhu.vx v10, v8, a0
452; RV32-NEXT:    vsrl.vi v10, v10, 13
453; RV32-NEXT:    li a0, -7
454; RV32-NEXT:    vnmsac.vx v8, a0, v10
455; RV32-NEXT:    ret
456;
457; RV64-LABEL: vremu_vi_nxv8i16_0:
458; RV64:       # %bb.0:
459; RV64-NEXT:    lui a0, 2
460; RV64-NEXT:    addiw a0, a0, 1
461; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
462; RV64-NEXT:    vmulhu.vx v10, v8, a0
463; RV64-NEXT:    vsrl.vi v10, v10, 13
464; RV64-NEXT:    li a0, -7
465; RV64-NEXT:    vnmsac.vx v8, a0, v10
466; RV64-NEXT:    ret
467  %head = insertelement <vscale x 8 x i16> poison, i16 -7, i32 0
468  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
469  %vc = urem <vscale x 8 x i16> %va, %splat
470  ret <vscale x 8 x i16> %vc
471}
472
473define <vscale x 16 x i16> @vremu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
474; CHECK-LABEL: vremu_vv_nxv16i16:
475; CHECK:       # %bb.0:
476; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
477; CHECK-NEXT:    vremu.vv v8, v8, v12
478; CHECK-NEXT:    ret
479  %vc = urem <vscale x 16 x i16> %va, %vb
480  ret <vscale x 16 x i16> %vc
481}
482
483define <vscale x 16 x i16> @vremu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
484; CHECK-LABEL: vremu_vx_nxv16i16:
485; CHECK:       # %bb.0:
486; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
487; CHECK-NEXT:    vremu.vx v8, v8, a0
488; CHECK-NEXT:    ret
489  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
490  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
491  %vc = urem <vscale x 16 x i16> %va, %splat
492  ret <vscale x 16 x i16> %vc
493}
494
495define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
496; RV32-LABEL: vremu_vi_nxv16i16_0:
497; RV32:       # %bb.0:
498; RV32-NEXT:    lui a0, 2
499; RV32-NEXT:    addi a0, a0, 1
500; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
501; RV32-NEXT:    vmulhu.vx v12, v8, a0
502; RV32-NEXT:    vsrl.vi v12, v12, 13
503; RV32-NEXT:    li a0, -7
504; RV32-NEXT:    vnmsac.vx v8, a0, v12
505; RV32-NEXT:    ret
506;
507; RV64-LABEL: vremu_vi_nxv16i16_0:
508; RV64:       # %bb.0:
509; RV64-NEXT:    lui a0, 2
510; RV64-NEXT:    addiw a0, a0, 1
511; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
512; RV64-NEXT:    vmulhu.vx v12, v8, a0
513; RV64-NEXT:    vsrl.vi v12, v12, 13
514; RV64-NEXT:    li a0, -7
515; RV64-NEXT:    vnmsac.vx v8, a0, v12
516; RV64-NEXT:    ret
517  %head = insertelement <vscale x 16 x i16> poison, i16 -7, i32 0
518  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
519  %vc = urem <vscale x 16 x i16> %va, %splat
520  ret <vscale x 16 x i16> %vc
521}
522
523define <vscale x 32 x i16> @vremu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
524; CHECK-LABEL: vremu_vv_nxv32i16:
525; CHECK:       # %bb.0:
526; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
527; CHECK-NEXT:    vremu.vv v8, v8, v16
528; CHECK-NEXT:    ret
529  %vc = urem <vscale x 32 x i16> %va, %vb
530  ret <vscale x 32 x i16> %vc
531}
532
533define <vscale x 32 x i16> @vremu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
534; CHECK-LABEL: vremu_vx_nxv32i16:
535; CHECK:       # %bb.0:
536; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
537; CHECK-NEXT:    vremu.vx v8, v8, a0
538; CHECK-NEXT:    ret
539  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
540  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
541  %vc = urem <vscale x 32 x i16> %va, %splat
542  ret <vscale x 32 x i16> %vc
543}
544
545define <vscale x 32 x i16> @vremu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
546; RV32-LABEL: vremu_vi_nxv32i16_0:
547; RV32:       # %bb.0:
548; RV32-NEXT:    lui a0, 2
549; RV32-NEXT:    addi a0, a0, 1
550; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
551; RV32-NEXT:    vmulhu.vx v16, v8, a0
552; RV32-NEXT:    vsrl.vi v16, v16, 13
553; RV32-NEXT:    li a0, -7
554; RV32-NEXT:    vnmsac.vx v8, a0, v16
555; RV32-NEXT:    ret
556;
557; RV64-LABEL: vremu_vi_nxv32i16_0:
558; RV64:       # %bb.0:
559; RV64-NEXT:    lui a0, 2
560; RV64-NEXT:    addiw a0, a0, 1
561; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
562; RV64-NEXT:    vmulhu.vx v16, v8, a0
563; RV64-NEXT:    vsrl.vi v16, v16, 13
564; RV64-NEXT:    li a0, -7
565; RV64-NEXT:    vnmsac.vx v8, a0, v16
566; RV64-NEXT:    ret
567  %head = insertelement <vscale x 32 x i16> poison, i16 -7, i32 0
568  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
569  %vc = urem <vscale x 32 x i16> %va, %splat
570  ret <vscale x 32 x i16> %vc
571}
572
573define <vscale x 1 x i32> @vremu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
574; CHECK-LABEL: vremu_vv_nxv1i32:
575; CHECK:       # %bb.0:
576; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
577; CHECK-NEXT:    vremu.vv v8, v8, v9
578; CHECK-NEXT:    ret
579  %vc = urem <vscale x 1 x i32> %va, %vb
580  ret <vscale x 1 x i32> %vc
581}
582
583define <vscale x 1 x i32> @vremu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
584; CHECK-LABEL: vremu_vx_nxv1i32:
585; CHECK:       # %bb.0:
586; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
587; CHECK-NEXT:    vremu.vx v8, v8, a0
588; CHECK-NEXT:    ret
589  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
590  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
591  %vc = urem <vscale x 1 x i32> %va, %splat
592  ret <vscale x 1 x i32> %vc
593}
594
595define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
596; RV32-LABEL: vremu_vi_nxv1i32_0:
597; RV32:       # %bb.0:
598; RV32-NEXT:    lui a0, 131072
599; RV32-NEXT:    addi a0, a0, 1
600; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
601; RV32-NEXT:    vmulhu.vx v9, v8, a0
602; RV32-NEXT:    vsrl.vi v9, v9, 29
603; RV32-NEXT:    li a0, -7
604; RV32-NEXT:    vnmsac.vx v8, a0, v9
605; RV32-NEXT:    ret
606;
607; RV64-LABEL: vremu_vi_nxv1i32_0:
608; RV64:       # %bb.0:
609; RV64-NEXT:    lui a0, 131072
610; RV64-NEXT:    addiw a0, a0, 1
611; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
612; RV64-NEXT:    vmulhu.vx v9, v8, a0
613; RV64-NEXT:    vsrl.vi v9, v9, 29
614; RV64-NEXT:    li a0, -7
615; RV64-NEXT:    vnmsac.vx v8, a0, v9
616; RV64-NEXT:    ret
617  %head = insertelement <vscale x 1 x i32> poison, i32 -7, i32 0
618  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
619  %vc = urem <vscale x 1 x i32> %va, %splat
620  ret <vscale x 1 x i32> %vc
621}
622
623define <vscale x 2 x i32> @vremu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
624; CHECK-LABEL: vremu_vv_nxv2i32:
625; CHECK:       # %bb.0:
626; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
627; CHECK-NEXT:    vremu.vv v8, v8, v9
628; CHECK-NEXT:    ret
629  %vc = urem <vscale x 2 x i32> %va, %vb
630  ret <vscale x 2 x i32> %vc
631}
632
633define <vscale x 2 x i32> @vremu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
634; CHECK-LABEL: vremu_vx_nxv2i32:
635; CHECK:       # %bb.0:
636; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
637; CHECK-NEXT:    vremu.vx v8, v8, a0
638; CHECK-NEXT:    ret
639  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
640  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
641  %vc = urem <vscale x 2 x i32> %va, %splat
642  ret <vscale x 2 x i32> %vc
643}
644
645define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
646; RV32-LABEL: vremu_vi_nxv2i32_0:
647; RV32:       # %bb.0:
648; RV32-NEXT:    lui a0, 131072
649; RV32-NEXT:    addi a0, a0, 1
650; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
651; RV32-NEXT:    vmulhu.vx v9, v8, a0
652; RV32-NEXT:    vsrl.vi v9, v9, 29
653; RV32-NEXT:    li a0, -7
654; RV32-NEXT:    vnmsac.vx v8, a0, v9
655; RV32-NEXT:    ret
656;
657; RV64-LABEL: vremu_vi_nxv2i32_0:
658; RV64:       # %bb.0:
659; RV64-NEXT:    lui a0, 131072
660; RV64-NEXT:    addiw a0, a0, 1
661; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
662; RV64-NEXT:    vmulhu.vx v9, v8, a0
663; RV64-NEXT:    vsrl.vi v9, v9, 29
664; RV64-NEXT:    li a0, -7
665; RV64-NEXT:    vnmsac.vx v8, a0, v9
666; RV64-NEXT:    ret
667  %head = insertelement <vscale x 2 x i32> poison, i32 -7, i32 0
668  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
669  %vc = urem <vscale x 2 x i32> %va, %splat
670  ret <vscale x 2 x i32> %vc
671}
672
673define <vscale x 4 x i32> @vremu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
674; CHECK-LABEL: vremu_vv_nxv4i32:
675; CHECK:       # %bb.0:
676; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
677; CHECK-NEXT:    vremu.vv v8, v8, v10
678; CHECK-NEXT:    ret
679  %vc = urem <vscale x 4 x i32> %va, %vb
680  ret <vscale x 4 x i32> %vc
681}
682
683define <vscale x 4 x i32> @vremu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
684; CHECK-LABEL: vremu_vx_nxv4i32:
685; CHECK:       # %bb.0:
686; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
687; CHECK-NEXT:    vremu.vx v8, v8, a0
688; CHECK-NEXT:    ret
689  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
690  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
691  %vc = urem <vscale x 4 x i32> %va, %splat
692  ret <vscale x 4 x i32> %vc
693}
694
695define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
696; RV32-LABEL: vremu_vi_nxv4i32_0:
697; RV32:       # %bb.0:
698; RV32-NEXT:    lui a0, 131072
699; RV32-NEXT:    addi a0, a0, 1
700; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
701; RV32-NEXT:    vmulhu.vx v10, v8, a0
702; RV32-NEXT:    vsrl.vi v10, v10, 29
703; RV32-NEXT:    li a0, -7
704; RV32-NEXT:    vnmsac.vx v8, a0, v10
705; RV32-NEXT:    ret
706;
707; RV64-LABEL: vremu_vi_nxv4i32_0:
708; RV64:       # %bb.0:
709; RV64-NEXT:    lui a0, 131072
710; RV64-NEXT:    addiw a0, a0, 1
711; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
712; RV64-NEXT:    vmulhu.vx v10, v8, a0
713; RV64-NEXT:    vsrl.vi v10, v10, 29
714; RV64-NEXT:    li a0, -7
715; RV64-NEXT:    vnmsac.vx v8, a0, v10
716; RV64-NEXT:    ret
717  %head = insertelement <vscale x 4 x i32> poison, i32 -7, i32 0
718  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
719  %vc = urem <vscale x 4 x i32> %va, %splat
720  ret <vscale x 4 x i32> %vc
721}
722
723define <vscale x 8 x i32> @vremu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
724; CHECK-LABEL: vremu_vv_nxv8i32:
725; CHECK:       # %bb.0:
726; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
727; CHECK-NEXT:    vremu.vv v8, v8, v12
728; CHECK-NEXT:    ret
729  %vc = urem <vscale x 8 x i32> %va, %vb
730  ret <vscale x 8 x i32> %vc
731}
732
733define <vscale x 8 x i32> @vremu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
734; CHECK-LABEL: vremu_vx_nxv8i32:
735; CHECK:       # %bb.0:
736; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
737; CHECK-NEXT:    vremu.vx v8, v8, a0
738; CHECK-NEXT:    ret
739  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
740  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
741  %vc = urem <vscale x 8 x i32> %va, %splat
742  ret <vscale x 8 x i32> %vc
743}
744
745define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
746; RV32-LABEL: vremu_vi_nxv8i32_0:
747; RV32:       # %bb.0:
748; RV32-NEXT:    lui a0, 131072
749; RV32-NEXT:    addi a0, a0, 1
750; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
751; RV32-NEXT:    vmulhu.vx v12, v8, a0
752; RV32-NEXT:    vsrl.vi v12, v12, 29
753; RV32-NEXT:    li a0, -7
754; RV32-NEXT:    vnmsac.vx v8, a0, v12
755; RV32-NEXT:    ret
756;
757; RV64-LABEL: vremu_vi_nxv8i32_0:
758; RV64:       # %bb.0:
759; RV64-NEXT:    lui a0, 131072
760; RV64-NEXT:    addiw a0, a0, 1
761; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
762; RV64-NEXT:    vmulhu.vx v12, v8, a0
763; RV64-NEXT:    vsrl.vi v12, v12, 29
764; RV64-NEXT:    li a0, -7
765; RV64-NEXT:    vnmsac.vx v8, a0, v12
766; RV64-NEXT:    ret
767  %head = insertelement <vscale x 8 x i32> poison, i32 -7, i32 0
768  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
769  %vc = urem <vscale x 8 x i32> %va, %splat
770  ret <vscale x 8 x i32> %vc
771}
772
773define <vscale x 16 x i32> @vremu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
774; CHECK-LABEL: vremu_vv_nxv16i32:
775; CHECK:       # %bb.0:
776; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
777; CHECK-NEXT:    vremu.vv v8, v8, v16
778; CHECK-NEXT:    ret
779  %vc = urem <vscale x 16 x i32> %va, %vb
780  ret <vscale x 16 x i32> %vc
781}
782
783define <vscale x 16 x i32> @vremu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
784; CHECK-LABEL: vremu_vx_nxv16i32:
785; CHECK:       # %bb.0:
786; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
787; CHECK-NEXT:    vremu.vx v8, v8, a0
788; CHECK-NEXT:    ret
789  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
790  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
791  %vc = urem <vscale x 16 x i32> %va, %splat
792  ret <vscale x 16 x i32> %vc
793}
794
795define <vscale x 16 x i32> @vremu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
796; RV32-LABEL: vremu_vi_nxv16i32_0:
797; RV32:       # %bb.0:
798; RV32-NEXT:    lui a0, 131072
799; RV32-NEXT:    addi a0, a0, 1
800; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
801; RV32-NEXT:    vmulhu.vx v16, v8, a0
802; RV32-NEXT:    vsrl.vi v16, v16, 29
803; RV32-NEXT:    li a0, -7
804; RV32-NEXT:    vnmsac.vx v8, a0, v16
805; RV32-NEXT:    ret
806;
807; RV64-LABEL: vremu_vi_nxv16i32_0:
808; RV64:       # %bb.0:
809; RV64-NEXT:    lui a0, 131072
810; RV64-NEXT:    addiw a0, a0, 1
811; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
812; RV64-NEXT:    vmulhu.vx v16, v8, a0
813; RV64-NEXT:    vsrl.vi v16, v16, 29
814; RV64-NEXT:    li a0, -7
815; RV64-NEXT:    vnmsac.vx v8, a0, v16
816; RV64-NEXT:    ret
817  %head = insertelement <vscale x 16 x i32> poison, i32 -7, i32 0
818  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
819  %vc = urem <vscale x 16 x i32> %va, %splat
820  ret <vscale x 16 x i32> %vc
821}
822
823define <vscale x 1 x i64> @vremu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
824; CHECK-LABEL: vremu_vv_nxv1i64:
825; CHECK:       # %bb.0:
826; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
827; CHECK-NEXT:    vremu.vv v8, v8, v9
828; CHECK-NEXT:    ret
829  %vc = urem <vscale x 1 x i64> %va, %vb
830  ret <vscale x 1 x i64> %vc
831}
832
833define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
834; RV32-LABEL: vremu_vx_nxv1i64:
835; RV32:       # %bb.0:
836; RV32-NEXT:    addi sp, sp, -16
837; RV32-NEXT:    .cfi_def_cfa_offset 16
838; RV32-NEXT:    sw a1, 12(sp)
839; RV32-NEXT:    sw a0, 8(sp)
840; RV32-NEXT:    addi a0, sp, 8
841; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
842; RV32-NEXT:    vlse64.v v9, (a0), zero
843; RV32-NEXT:    vremu.vv v8, v8, v9
844; RV32-NEXT:    addi sp, sp, 16
845; RV32-NEXT:    ret
846;
847; RV64-LABEL: vremu_vx_nxv1i64:
848; RV64:       # %bb.0:
849; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
850; RV64-NEXT:    vremu.vx v8, v8, a0
851; RV64-NEXT:    ret
852  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
853  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
854  %vc = urem <vscale x 1 x i64> %va, %splat
855  ret <vscale x 1 x i64> %vc
856}
857
858define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
859; RV32-V-LABEL: vremu_vi_nxv1i64_0:
860; RV32-V:       # %bb.0:
861; RV32-V-NEXT:    addi sp, sp, -16
862; RV32-V-NEXT:    .cfi_def_cfa_offset 16
863; RV32-V-NEXT:    lui a0, 131072
864; RV32-V-NEXT:    sw a0, 12(sp)
865; RV32-V-NEXT:    li a0, 1
866; RV32-V-NEXT:    sw a0, 8(sp)
867; RV32-V-NEXT:    addi a0, sp, 8
868; RV32-V-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
869; RV32-V-NEXT:    vlse64.v v9, (a0), zero
870; RV32-V-NEXT:    vmulhu.vv v9, v8, v9
871; RV32-V-NEXT:    li a0, 61
872; RV32-V-NEXT:    vsrl.vx v9, v9, a0
873; RV32-V-NEXT:    li a0, -7
874; RV32-V-NEXT:    vnmsac.vx v8, a0, v9
875; RV32-V-NEXT:    addi sp, sp, 16
876; RV32-V-NEXT:    ret
877;
878; ZVE64X-LABEL: vremu_vi_nxv1i64_0:
879; ZVE64X:       # %bb.0:
880; ZVE64X-NEXT:    li a0, -7
881; ZVE64X-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
882; ZVE64X-NEXT:    vremu.vx v8, v8, a0
883; ZVE64X-NEXT:    ret
884;
885; RV64-V-LABEL: vremu_vi_nxv1i64_0:
886; RV64-V:       # %bb.0:
887; RV64-V-NEXT:    li a0, 1
888; RV64-V-NEXT:    slli a0, a0, 61
889; RV64-V-NEXT:    addi a0, a0, 1
890; RV64-V-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
891; RV64-V-NEXT:    vmulhu.vx v9, v8, a0
892; RV64-V-NEXT:    li a0, 61
893; RV64-V-NEXT:    vsrl.vx v9, v9, a0
894; RV64-V-NEXT:    li a0, -7
895; RV64-V-NEXT:    vnmsac.vx v8, a0, v9
896; RV64-V-NEXT:    ret
897  %head = insertelement <vscale x 1 x i64> poison, i64 -7, i32 0
898  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
899  %vc = urem <vscale x 1 x i64> %va, %splat
900  ret <vscale x 1 x i64> %vc
901}
902
903; fold (urem x, pow2) -> (and x, pow2-1)
904define <vscale x 1 x i64> @vremu_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
905; CHECK-LABEL: vremu_vi_nxv1i64_1:
906; CHECK:       # %bb.0:
907; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
908; CHECK-NEXT:    vand.vi v8, v8, 15
909; CHECK-NEXT:    ret
910  %head = insertelement <vscale x 1 x i64> poison, i64 16, i32 0
911  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
912  %vc = urem <vscale x 1 x i64> %va, %splat
913  ret <vscale x 1 x i64> %vc
914}
915
916; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
917define <vscale x 1 x i64> @vremu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
918; CHECK-LABEL: vremu_vi_nxv1i64_2:
919; CHECK:       # %bb.0:
920; CHECK-NEXT:    li a0, 16
921; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
922; CHECK-NEXT:    vmv.v.x v10, a0
923; CHECK-NEXT:    vsll.vv v9, v10, v9
924; CHECK-NEXT:    vadd.vi v9, v9, -1
925; CHECK-NEXT:    vand.vv v8, v8, v9
926; CHECK-NEXT:    ret
927  %head = insertelement <vscale x 1 x i64> poison, i64 16, i32 0
928  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
929  %vc = shl <vscale x 1 x i64> %splat, %vb
930  %vd = urem <vscale x 1 x i64> %va, %vc
931  ret <vscale x 1 x i64> %vd
932}
933
934define <vscale x 2 x i64> @vremu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
935; CHECK-LABEL: vremu_vv_nxv2i64:
936; CHECK:       # %bb.0:
937; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
938; CHECK-NEXT:    vremu.vv v8, v8, v10
939; CHECK-NEXT:    ret
940  %vc = urem <vscale x 2 x i64> %va, %vb
941  ret <vscale x 2 x i64> %vc
942}
943
944define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
945; RV32-LABEL: vremu_vx_nxv2i64:
946; RV32:       # %bb.0:
947; RV32-NEXT:    addi sp, sp, -16
948; RV32-NEXT:    .cfi_def_cfa_offset 16
949; RV32-NEXT:    sw a1, 12(sp)
950; RV32-NEXT:    sw a0, 8(sp)
951; RV32-NEXT:    addi a0, sp, 8
952; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
953; RV32-NEXT:    vlse64.v v10, (a0), zero
954; RV32-NEXT:    vremu.vv v8, v8, v10
955; RV32-NEXT:    addi sp, sp, 16
956; RV32-NEXT:    ret
957;
958; RV64-LABEL: vremu_vx_nxv2i64:
959; RV64:       # %bb.0:
960; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
961; RV64-NEXT:    vremu.vx v8, v8, a0
962; RV64-NEXT:    ret
963  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
964  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
965  %vc = urem <vscale x 2 x i64> %va, %splat
966  ret <vscale x 2 x i64> %vc
967}
968
969define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
970; RV32-V-LABEL: vremu_vi_nxv2i64_0:
971; RV32-V:       # %bb.0:
972; RV32-V-NEXT:    addi sp, sp, -16
973; RV32-V-NEXT:    .cfi_def_cfa_offset 16
974; RV32-V-NEXT:    lui a0, 131072
975; RV32-V-NEXT:    sw a0, 12(sp)
976; RV32-V-NEXT:    li a0, 1
977; RV32-V-NEXT:    sw a0, 8(sp)
978; RV32-V-NEXT:    addi a0, sp, 8
979; RV32-V-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
980; RV32-V-NEXT:    vlse64.v v10, (a0), zero
981; RV32-V-NEXT:    vmulhu.vv v10, v8, v10
982; RV32-V-NEXT:    li a0, 61
983; RV32-V-NEXT:    vsrl.vx v10, v10, a0
984; RV32-V-NEXT:    li a0, -7
985; RV32-V-NEXT:    vnmsac.vx v8, a0, v10
986; RV32-V-NEXT:    addi sp, sp, 16
987; RV32-V-NEXT:    ret
988;
989; ZVE64X-LABEL: vremu_vi_nxv2i64_0:
990; ZVE64X:       # %bb.0:
991; ZVE64X-NEXT:    li a0, -7
992; ZVE64X-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
993; ZVE64X-NEXT:    vremu.vx v8, v8, a0
994; ZVE64X-NEXT:    ret
995;
996; RV64-V-LABEL: vremu_vi_nxv2i64_0:
997; RV64-V:       # %bb.0:
998; RV64-V-NEXT:    li a0, 1
999; RV64-V-NEXT:    slli a0, a0, 61
1000; RV64-V-NEXT:    addi a0, a0, 1
1001; RV64-V-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1002; RV64-V-NEXT:    vmulhu.vx v10, v8, a0
1003; RV64-V-NEXT:    li a0, 61
1004; RV64-V-NEXT:    vsrl.vx v10, v10, a0
1005; RV64-V-NEXT:    li a0, -7
1006; RV64-V-NEXT:    vnmsac.vx v8, a0, v10
1007; RV64-V-NEXT:    ret
1008  %head = insertelement <vscale x 2 x i64> poison, i64 -7, i32 0
1009  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1010  %vc = urem <vscale x 2 x i64> %va, %splat
1011  ret <vscale x 2 x i64> %vc
1012}
1013
1014; fold (urem x, pow2) -> (and x, pow2-1)
1015define <vscale x 2 x i64> @vremu_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
1016; CHECK-LABEL: vremu_vi_nxv2i64_1:
1017; CHECK:       # %bb.0:
1018; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
1019; CHECK-NEXT:    vand.vi v8, v8, 15
1020; CHECK-NEXT:    ret
1021  %head = insertelement <vscale x 2 x i64> poison, i64 16, i32 0
1022  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1023  %vc = urem <vscale x 2 x i64> %va, %splat
1024  ret <vscale x 2 x i64> %vc
1025}
1026
1027; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1028define <vscale x 2 x i64> @vremu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
1029; CHECK-LABEL: vremu_vi_nxv2i64_2:
1030; CHECK:       # %bb.0:
1031; CHECK-NEXT:    li a0, 16
1032; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1033; CHECK-NEXT:    vmv.v.x v12, a0
1034; CHECK-NEXT:    vsll.vv v10, v12, v10
1035; CHECK-NEXT:    vadd.vi v10, v10, -1
1036; CHECK-NEXT:    vand.vv v8, v8, v10
1037; CHECK-NEXT:    ret
1038  %head = insertelement <vscale x 2 x i64> poison, i64 16, i32 0
1039  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1040  %vc = shl <vscale x 2 x i64> %splat, %vb
1041  %vd = urem <vscale x 2 x i64> %va, %vc
1042  ret <vscale x 2 x i64> %vd
1043}
1044
1045define <vscale x 4 x i64> @vremu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
1046; CHECK-LABEL: vremu_vv_nxv4i64:
1047; CHECK:       # %bb.0:
1048; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
1049; CHECK-NEXT:    vremu.vv v8, v8, v12
1050; CHECK-NEXT:    ret
1051  %vc = urem <vscale x 4 x i64> %va, %vb
1052  ret <vscale x 4 x i64> %vc
1053}
1054
1055define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
1056; RV32-LABEL: vremu_vx_nxv4i64:
1057; RV32:       # %bb.0:
1058; RV32-NEXT:    addi sp, sp, -16
1059; RV32-NEXT:    .cfi_def_cfa_offset 16
1060; RV32-NEXT:    sw a1, 12(sp)
1061; RV32-NEXT:    sw a0, 8(sp)
1062; RV32-NEXT:    addi a0, sp, 8
1063; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1064; RV32-NEXT:    vlse64.v v12, (a0), zero
1065; RV32-NEXT:    vremu.vv v8, v8, v12
1066; RV32-NEXT:    addi sp, sp, 16
1067; RV32-NEXT:    ret
1068;
1069; RV64-LABEL: vremu_vx_nxv4i64:
1070; RV64:       # %bb.0:
1071; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1072; RV64-NEXT:    vremu.vx v8, v8, a0
1073; RV64-NEXT:    ret
1074  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
1075  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1076  %vc = urem <vscale x 4 x i64> %va, %splat
1077  ret <vscale x 4 x i64> %vc
1078}
1079
1080define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
1081; RV32-V-LABEL: vremu_vi_nxv4i64_0:
1082; RV32-V:       # %bb.0:
1083; RV32-V-NEXT:    addi sp, sp, -16
1084; RV32-V-NEXT:    .cfi_def_cfa_offset 16
1085; RV32-V-NEXT:    lui a0, 131072
1086; RV32-V-NEXT:    sw a0, 12(sp)
1087; RV32-V-NEXT:    li a0, 1
1088; RV32-V-NEXT:    sw a0, 8(sp)
1089; RV32-V-NEXT:    addi a0, sp, 8
1090; RV32-V-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1091; RV32-V-NEXT:    vlse64.v v12, (a0), zero
1092; RV32-V-NEXT:    vmulhu.vv v12, v8, v12
1093; RV32-V-NEXT:    li a0, 61
1094; RV32-V-NEXT:    vsrl.vx v12, v12, a0
1095; RV32-V-NEXT:    li a0, -7
1096; RV32-V-NEXT:    vnmsac.vx v8, a0, v12
1097; RV32-V-NEXT:    addi sp, sp, 16
1098; RV32-V-NEXT:    ret
1099;
1100; ZVE64X-LABEL: vremu_vi_nxv4i64_0:
1101; ZVE64X:       # %bb.0:
1102; ZVE64X-NEXT:    li a0, -7
1103; ZVE64X-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1104; ZVE64X-NEXT:    vremu.vx v8, v8, a0
1105; ZVE64X-NEXT:    ret
1106;
1107; RV64-V-LABEL: vremu_vi_nxv4i64_0:
1108; RV64-V:       # %bb.0:
1109; RV64-V-NEXT:    li a0, 1
1110; RV64-V-NEXT:    slli a0, a0, 61
1111; RV64-V-NEXT:    addi a0, a0, 1
1112; RV64-V-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1113; RV64-V-NEXT:    vmulhu.vx v12, v8, a0
1114; RV64-V-NEXT:    li a0, 61
1115; RV64-V-NEXT:    vsrl.vx v12, v12, a0
1116; RV64-V-NEXT:    li a0, -7
1117; RV64-V-NEXT:    vnmsac.vx v8, a0, v12
1118; RV64-V-NEXT:    ret
1119  %head = insertelement <vscale x 4 x i64> poison, i64 -7, i32 0
1120  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1121  %vc = urem <vscale x 4 x i64> %va, %splat
1122  ret <vscale x 4 x i64> %vc
1123}
1124
1125; fold (urem x, pow2) -> (and x, pow2-1)
1126define <vscale x 4 x i64> @vremu_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
1127; CHECK-LABEL: vremu_vi_nxv4i64_1:
1128; CHECK:       # %bb.0:
1129; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
1130; CHECK-NEXT:    vand.vi v8, v8, 15
1131; CHECK-NEXT:    ret
1132  %head = insertelement <vscale x 4 x i64> poison, i64 16, i32 0
1133  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1134  %vc = urem <vscale x 4 x i64> %va, %splat
1135  ret <vscale x 4 x i64> %vc
1136}
1137
1138;fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1139define <vscale x 4 x i64> @vremu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
1140; CHECK-LABEL: vremu_vi_nxv4i64_2:
1141; CHECK:       # %bb.0:
1142; CHECK-NEXT:    li a0, 16
1143; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1144; CHECK-NEXT:    vmv.v.x v16, a0
1145; CHECK-NEXT:    vsll.vv v12, v16, v12
1146; CHECK-NEXT:    vadd.vi v12, v12, -1
1147; CHECK-NEXT:    vand.vv v8, v8, v12
1148; CHECK-NEXT:    ret
1149  %head = insertelement <vscale x 4 x i64> poison, i64 16, i32 0
1150  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1151  %vc = shl <vscale x 4 x i64> %splat, %vb
1152  %vd = urem <vscale x 4 x i64> %va, %vc
1153  ret <vscale x 4 x i64> %vd
1154}
1155
1156define <vscale x 8 x i64> @vremu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
1157; CHECK-LABEL: vremu_vv_nxv8i64:
1158; CHECK:       # %bb.0:
1159; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1160; CHECK-NEXT:    vremu.vv v8, v8, v16
1161; CHECK-NEXT:    ret
1162  %vc = urem <vscale x 8 x i64> %va, %vb
1163  ret <vscale x 8 x i64> %vc
1164}
1165
1166define <vscale x 8 x i64> @vremu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
1167; RV32-LABEL: vremu_vx_nxv8i64:
1168; RV32:       # %bb.0:
1169; RV32-NEXT:    addi sp, sp, -16
1170; RV32-NEXT:    .cfi_def_cfa_offset 16
1171; RV32-NEXT:    sw a1, 12(sp)
1172; RV32-NEXT:    sw a0, 8(sp)
1173; RV32-NEXT:    addi a0, sp, 8
1174; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1175; RV32-NEXT:    vlse64.v v16, (a0), zero
1176; RV32-NEXT:    vremu.vv v8, v8, v16
1177; RV32-NEXT:    addi sp, sp, 16
1178; RV32-NEXT:    ret
1179;
1180; RV64-LABEL: vremu_vx_nxv8i64:
1181; RV64:       # %bb.0:
1182; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1183; RV64-NEXT:    vremu.vx v8, v8, a0
1184; RV64-NEXT:    ret
1185  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
1186  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1187  %vc = urem <vscale x 8 x i64> %va, %splat
1188  ret <vscale x 8 x i64> %vc
1189}
1190
1191define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
1192; RV32-V-LABEL: vremu_vi_nxv8i64_0:
1193; RV32-V:       # %bb.0:
1194; RV32-V-NEXT:    addi sp, sp, -16
1195; RV32-V-NEXT:    .cfi_def_cfa_offset 16
1196; RV32-V-NEXT:    lui a0, 131072
1197; RV32-V-NEXT:    sw a0, 12(sp)
1198; RV32-V-NEXT:    li a0, 1
1199; RV32-V-NEXT:    sw a0, 8(sp)
1200; RV32-V-NEXT:    addi a0, sp, 8
1201; RV32-V-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1202; RV32-V-NEXT:    vlse64.v v16, (a0), zero
1203; RV32-V-NEXT:    vmulhu.vv v16, v8, v16
1204; RV32-V-NEXT:    li a0, 61
1205; RV32-V-NEXT:    vsrl.vx v16, v16, a0
1206; RV32-V-NEXT:    li a0, -7
1207; RV32-V-NEXT:    vnmsac.vx v8, a0, v16
1208; RV32-V-NEXT:    addi sp, sp, 16
1209; RV32-V-NEXT:    ret
1210;
1211; ZVE64X-LABEL: vremu_vi_nxv8i64_0:
1212; ZVE64X:       # %bb.0:
1213; ZVE64X-NEXT:    li a0, -7
1214; ZVE64X-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1215; ZVE64X-NEXT:    vremu.vx v8, v8, a0
1216; ZVE64X-NEXT:    ret
1217;
1218; RV64-V-LABEL: vremu_vi_nxv8i64_0:
1219; RV64-V:       # %bb.0:
1220; RV64-V-NEXT:    li a0, 1
1221; RV64-V-NEXT:    slli a0, a0, 61
1222; RV64-V-NEXT:    addi a0, a0, 1
1223; RV64-V-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1224; RV64-V-NEXT:    vmulhu.vx v16, v8, a0
1225; RV64-V-NEXT:    li a0, 61
1226; RV64-V-NEXT:    vsrl.vx v16, v16, a0
1227; RV64-V-NEXT:    li a0, -7
1228; RV64-V-NEXT:    vnmsac.vx v8, a0, v16
1229; RV64-V-NEXT:    ret
1230  %head = insertelement <vscale x 8 x i64> poison, i64 -7, i32 0
1231  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1232  %vc = urem <vscale x 8 x i64> %va, %splat
1233  ret <vscale x 8 x i64> %vc
1234}
1235
1236; fold (urem x, pow2) -> (and x, pow2-1)
1237define <vscale x 8 x i64> @vremu_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
1238; CHECK-LABEL: vremu_vi_nxv8i64_1:
1239; CHECK:       # %bb.0:
1240; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1241; CHECK-NEXT:    vand.vi v8, v8, 15
1242; CHECK-NEXT:    ret
1243  %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
1244  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1245  %vc = urem <vscale x 8 x i64> %va, %splat
1246  ret <vscale x 8 x i64> %vc
1247}
1248
1249; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1250define <vscale x 8 x i64> @vremu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
1251; CHECK-LABEL: vremu_vi_nxv8i64_2:
1252; CHECK:       # %bb.0:
1253; CHECK-NEXT:    li a0, 16
1254; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1255; CHECK-NEXT:    vmv.v.x v24, a0
1256; CHECK-NEXT:    vsll.vv v16, v24, v16
1257; CHECK-NEXT:    vadd.vi v16, v16, -1
1258; CHECK-NEXT:    vand.vv v8, v8, v16
1259; CHECK-NEXT:    ret
1260  %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
1261  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1262  %vc = shl <vscale x 8 x i64> %splat, %vb
1263  %vd = urem <vscale x 8 x i64> %va, %vc
1264  ret <vscale x 8 x i64> %vd
1265}
1266