1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-v -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-v -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare half @llvm.vector.reduce.fadd.nxv1f16(half, <vscale x 1 x half>)
8
9define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
10; CHECK-LABEL: vreduce_fadd_nxv1f16:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    fmv.h.x ft0, zero
13; CHECK-NEXT:    fneg.h ft0, ft0
14; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
15; CHECK-NEXT:    vfmv.s.f v9, ft0
16; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
17; CHECK-NEXT:    vfredusum.vs v8, v8, v9
18; CHECK-NEXT:    vfmv.f.s ft0, v8
19; CHECK-NEXT:    fadd.h fa0, fa0, ft0
20; CHECK-NEXT:    ret
21  %red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
22  ret half %red
23}
24
25define half @vreduce_ord_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
26; CHECK-LABEL: vreduce_ord_fadd_nxv1f16:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
29; CHECK-NEXT:    vfmv.s.f v9, fa0
30; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
31; CHECK-NEXT:    vfredosum.vs v8, v8, v9
32; CHECK-NEXT:    vfmv.f.s fa0, v8
33; CHECK-NEXT:    ret
34  %red = call half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
35  ret half %red
36}
37
38declare half @llvm.vector.reduce.fadd.nxv2f16(half, <vscale x 2 x half>)
39
40define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
41; CHECK-LABEL: vreduce_fadd_nxv2f16:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    fmv.h.x ft0, zero
44; CHECK-NEXT:    fneg.h ft0, ft0
45; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
46; CHECK-NEXT:    vfmv.s.f v9, ft0
47; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
48; CHECK-NEXT:    vfredusum.vs v8, v8, v9
49; CHECK-NEXT:    vfmv.f.s ft0, v8
50; CHECK-NEXT:    fadd.h fa0, fa0, ft0
51; CHECK-NEXT:    ret
52  %red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
53  ret half %red
54}
55
56define half @vreduce_ord_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
57; CHECK-LABEL: vreduce_ord_fadd_nxv2f16:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
60; CHECK-NEXT:    vfmv.s.f v9, fa0
61; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
62; CHECK-NEXT:    vfredosum.vs v8, v8, v9
63; CHECK-NEXT:    vfmv.f.s fa0, v8
64; CHECK-NEXT:    ret
65  %red = call half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
66  ret half %red
67}
68
69declare half @llvm.vector.reduce.fadd.nxv4f16(half, <vscale x 4 x half>)
70
71define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
72; CHECK-LABEL: vreduce_fadd_nxv4f16:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    fmv.h.x ft0, zero
75; CHECK-NEXT:    fneg.h ft0, ft0
76; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
77; CHECK-NEXT:    vfmv.s.f v9, ft0
78; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
79; CHECK-NEXT:    vfredusum.vs v8, v8, v9
80; CHECK-NEXT:    vfmv.f.s ft0, v8
81; CHECK-NEXT:    fadd.h fa0, fa0, ft0
82; CHECK-NEXT:    ret
83  %red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
84  ret half %red
85}
86
87define half @vreduce_ord_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
88; CHECK-LABEL: vreduce_ord_fadd_nxv4f16:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
91; CHECK-NEXT:    vfmv.s.f v9, fa0
92; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
93; CHECK-NEXT:    vfredosum.vs v8, v8, v9
94; CHECK-NEXT:    vfmv.f.s fa0, v8
95; CHECK-NEXT:    ret
96  %red = call half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
97  ret half %red
98}
99
100declare float @llvm.vector.reduce.fadd.nxv1f32(float, <vscale x 1 x float>)
101
102define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
103; CHECK-LABEL: vreduce_fadd_nxv1f32:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    fmv.w.x ft0, zero
106; CHECK-NEXT:    fneg.s ft0, ft0
107; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
108; CHECK-NEXT:    vfmv.s.f v9, ft0
109; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
110; CHECK-NEXT:    vfredusum.vs v8, v8, v9
111; CHECK-NEXT:    vfmv.f.s ft0, v8
112; CHECK-NEXT:    fadd.s fa0, fa0, ft0
113; CHECK-NEXT:    ret
114  %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
115  ret float %red
116}
117
118define float @vreduce_ord_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
119; CHECK-LABEL: vreduce_ord_fadd_nxv1f32:
120; CHECK:       # %bb.0:
121; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
122; CHECK-NEXT:    vfmv.s.f v9, fa0
123; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
124; CHECK-NEXT:    vfredosum.vs v8, v8, v9
125; CHECK-NEXT:    vfmv.f.s fa0, v8
126; CHECK-NEXT:    ret
127  %red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
128  ret float %red
129}
130
131declare float @llvm.vector.reduce.fadd.nxv2f32(float, <vscale x 2 x float>)
132
133define float @vreduce_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
134; CHECK-LABEL: vreduce_fadd_nxv2f32:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    fmv.w.x ft0, zero
137; CHECK-NEXT:    fneg.s ft0, ft0
138; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
139; CHECK-NEXT:    vfmv.s.f v9, ft0
140; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
141; CHECK-NEXT:    vfredusum.vs v8, v8, v9
142; CHECK-NEXT:    vfmv.f.s ft0, v8
143; CHECK-NEXT:    fadd.s fa0, fa0, ft0
144; CHECK-NEXT:    ret
145  %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
146  ret float %red
147}
148
149define float @vreduce_ord_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
150; CHECK-LABEL: vreduce_ord_fadd_nxv2f32:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
153; CHECK-NEXT:    vfmv.s.f v9, fa0
154; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
155; CHECK-NEXT:    vfredosum.vs v8, v8, v9
156; CHECK-NEXT:    vfmv.f.s fa0, v8
157; CHECK-NEXT:    ret
158  %red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
159  ret float %red
160}
161
162declare float @llvm.vector.reduce.fadd.nxv4f32(float, <vscale x 4 x float>)
163
164define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
165; CHECK-LABEL: vreduce_fadd_nxv4f32:
166; CHECK:       # %bb.0:
167; CHECK-NEXT:    fmv.w.x ft0, zero
168; CHECK-NEXT:    fneg.s ft0, ft0
169; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
170; CHECK-NEXT:    vfmv.s.f v10, ft0
171; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
172; CHECK-NEXT:    vfredusum.vs v8, v8, v10
173; CHECK-NEXT:    vfmv.f.s ft0, v8
174; CHECK-NEXT:    fadd.s fa0, fa0, ft0
175; CHECK-NEXT:    ret
176  %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
177  ret float %red
178}
179
180define float @vreduce_ord_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
181; CHECK-LABEL: vreduce_ord_fadd_nxv4f32:
182; CHECK:       # %bb.0:
183; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
184; CHECK-NEXT:    vfmv.s.f v10, fa0
185; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
186; CHECK-NEXT:    vfredosum.vs v8, v8, v10
187; CHECK-NEXT:    vfmv.f.s fa0, v8
188; CHECK-NEXT:    ret
189  %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
190  ret float %red
191}
192
193declare double @llvm.vector.reduce.fadd.nxv1f64(double, <vscale x 1 x double>)
194
195define double @vreduce_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
196; RV32-LABEL: vreduce_fadd_nxv1f64:
197; RV32:       # %bb.0:
198; RV32-NEXT:    fcvt.d.w ft0, zero
199; RV32-NEXT:    fneg.d ft0, ft0
200; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
201; RV32-NEXT:    vfmv.s.f v9, ft0
202; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
203; RV32-NEXT:    vfredusum.vs v8, v8, v9
204; RV32-NEXT:    vfmv.f.s ft0, v8
205; RV32-NEXT:    fadd.d fa0, fa0, ft0
206; RV32-NEXT:    ret
207;
208; RV64-LABEL: vreduce_fadd_nxv1f64:
209; RV64:       # %bb.0:
210; RV64-NEXT:    fmv.d.x ft0, zero
211; RV64-NEXT:    fneg.d ft0, ft0
212; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
213; RV64-NEXT:    vfmv.s.f v9, ft0
214; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
215; RV64-NEXT:    vfredusum.vs v8, v8, v9
216; RV64-NEXT:    vfmv.f.s ft0, v8
217; RV64-NEXT:    fadd.d fa0, fa0, ft0
218; RV64-NEXT:    ret
219  %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
220  ret double %red
221}
222
223define double @vreduce_ord_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
224; CHECK-LABEL: vreduce_ord_fadd_nxv1f64:
225; CHECK:       # %bb.0:
226; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
227; CHECK-NEXT:    vfmv.s.f v9, fa0
228; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
229; CHECK-NEXT:    vfredosum.vs v8, v8, v9
230; CHECK-NEXT:    vfmv.f.s fa0, v8
231; CHECK-NEXT:    ret
232  %red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
233  ret double %red
234}
235
236declare double @llvm.vector.reduce.fadd.nxv2f64(double, <vscale x 2 x double>)
237
238define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
239; RV32-LABEL: vreduce_fadd_nxv2f64:
240; RV32:       # %bb.0:
241; RV32-NEXT:    fcvt.d.w ft0, zero
242; RV32-NEXT:    fneg.d ft0, ft0
243; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
244; RV32-NEXT:    vfmv.s.f v10, ft0
245; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
246; RV32-NEXT:    vfredusum.vs v8, v8, v10
247; RV32-NEXT:    vfmv.f.s ft0, v8
248; RV32-NEXT:    fadd.d fa0, fa0, ft0
249; RV32-NEXT:    ret
250;
251; RV64-LABEL: vreduce_fadd_nxv2f64:
252; RV64:       # %bb.0:
253; RV64-NEXT:    fmv.d.x ft0, zero
254; RV64-NEXT:    fneg.d ft0, ft0
255; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
256; RV64-NEXT:    vfmv.s.f v10, ft0
257; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
258; RV64-NEXT:    vfredusum.vs v8, v8, v10
259; RV64-NEXT:    vfmv.f.s ft0, v8
260; RV64-NEXT:    fadd.d fa0, fa0, ft0
261; RV64-NEXT:    ret
262  %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
263  ret double %red
264}
265
266define double @vreduce_ord_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
267; CHECK-LABEL: vreduce_ord_fadd_nxv2f64:
268; CHECK:       # %bb.0:
269; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
270; CHECK-NEXT:    vfmv.s.f v10, fa0
271; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
272; CHECK-NEXT:    vfredosum.vs v8, v8, v10
273; CHECK-NEXT:    vfmv.f.s fa0, v8
274; CHECK-NEXT:    ret
275  %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
276  ret double %red
277}
278
279declare double @llvm.vector.reduce.fadd.nxv4f64(double, <vscale x 4 x double>)
280
281define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
282; RV32-LABEL: vreduce_fadd_nxv4f64:
283; RV32:       # %bb.0:
284; RV32-NEXT:    fcvt.d.w ft0, zero
285; RV32-NEXT:    fneg.d ft0, ft0
286; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
287; RV32-NEXT:    vfmv.s.f v12, ft0
288; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
289; RV32-NEXT:    vfredusum.vs v8, v8, v12
290; RV32-NEXT:    vfmv.f.s ft0, v8
291; RV32-NEXT:    fadd.d fa0, fa0, ft0
292; RV32-NEXT:    ret
293;
294; RV64-LABEL: vreduce_fadd_nxv4f64:
295; RV64:       # %bb.0:
296; RV64-NEXT:    fmv.d.x ft0, zero
297; RV64-NEXT:    fneg.d ft0, ft0
298; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
299; RV64-NEXT:    vfmv.s.f v12, ft0
300; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
301; RV64-NEXT:    vfredusum.vs v8, v8, v12
302; RV64-NEXT:    vfmv.f.s ft0, v8
303; RV64-NEXT:    fadd.d fa0, fa0, ft0
304; RV64-NEXT:    ret
305  %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
306  ret double %red
307}
308
309define double @vreduce_ord_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
310; CHECK-LABEL: vreduce_ord_fadd_nxv4f64:
311; CHECK:       # %bb.0:
312; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
313; CHECK-NEXT:    vfmv.s.f v12, fa0
314; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
315; CHECK-NEXT:    vfredosum.vs v8, v8, v12
316; CHECK-NEXT:    vfmv.f.s fa0, v8
317; CHECK-NEXT:    ret
318  %red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
319  ret double %red
320}
321
322declare half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half>)
323
324define half @vreduce_fmin_nxv1f16(<vscale x 1 x half> %v) {
325; CHECK-LABEL: vreduce_fmin_nxv1f16:
326; CHECK:       # %bb.0:
327; CHECK-NEXT:    lui a0, %hi(.LCPI18_0)
328; CHECK-NEXT:    addi a0, a0, %lo(.LCPI18_0)
329; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
330; CHECK-NEXT:    vlse16.v v9, (a0), zero
331; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
332; CHECK-NEXT:    vfredmin.vs v8, v8, v9
333; CHECK-NEXT:    vfmv.f.s fa0, v8
334; CHECK-NEXT:    ret
335  %red = call half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
336  ret half %red
337}
338
339define half @vreduce_fmin_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
340; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans:
341; CHECK:       # %bb.0:
342; CHECK-NEXT:    lui a0, %hi(.LCPI19_0)
343; CHECK-NEXT:    addi a0, a0, %lo(.LCPI19_0)
344; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
345; CHECK-NEXT:    vlse16.v v9, (a0), zero
346; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
347; CHECK-NEXT:    vfredmin.vs v8, v8, v9
348; CHECK-NEXT:    vfmv.f.s fa0, v8
349; CHECK-NEXT:    ret
350  %red = call nnan half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
351  ret half %red
352}
353
354define half @vreduce_fmin_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
355; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans_noinfs:
356; CHECK:       # %bb.0:
357; CHECK-NEXT:    lui a0, %hi(.LCPI20_0)
358; CHECK-NEXT:    addi a0, a0, %lo(.LCPI20_0)
359; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
360; CHECK-NEXT:    vlse16.v v9, (a0), zero
361; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
362; CHECK-NEXT:    vfredmin.vs v8, v8, v9
363; CHECK-NEXT:    vfmv.f.s fa0, v8
364; CHECK-NEXT:    ret
365  %red = call nnan ninf half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
366  ret half %red
367}
368
369declare half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half>)
370
371define half @vreduce_fmin_nxv2f16(<vscale x 2 x half> %v) {
372; CHECK-LABEL: vreduce_fmin_nxv2f16:
373; CHECK:       # %bb.0:
374; CHECK-NEXT:    lui a0, %hi(.LCPI21_0)
375; CHECK-NEXT:    addi a0, a0, %lo(.LCPI21_0)
376; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
377; CHECK-NEXT:    vlse16.v v9, (a0), zero
378; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
379; CHECK-NEXT:    vfredmin.vs v8, v8, v9
380; CHECK-NEXT:    vfmv.f.s fa0, v8
381; CHECK-NEXT:    ret
382  %red = call half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half> %v)
383  ret half %red
384}
385
386declare half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half>)
387
388define half @vreduce_fmin_nxv4f16(<vscale x 4 x half> %v) {
389; CHECK-LABEL: vreduce_fmin_nxv4f16:
390; CHECK:       # %bb.0:
391; CHECK-NEXT:    lui a0, %hi(.LCPI22_0)
392; CHECK-NEXT:    addi a0, a0, %lo(.LCPI22_0)
393; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
394; CHECK-NEXT:    vlse16.v v9, (a0), zero
395; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
396; CHECK-NEXT:    vfredmin.vs v8, v8, v9
397; CHECK-NEXT:    vfmv.f.s fa0, v8
398; CHECK-NEXT:    ret
399  %red = call half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half> %v)
400  ret half %red
401}
402
403declare half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half>)
404
405define half @vreduce_fmin_nxv64f16(<vscale x 64 x half> %v) {
406; CHECK-LABEL: vreduce_fmin_nxv64f16:
407; CHECK:       # %bb.0:
408; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
409; CHECK-NEXT:    vfmin.vv v8, v8, v16
410; CHECK-NEXT:    lui a0, %hi(.LCPI23_0)
411; CHECK-NEXT:    addi a0, a0, %lo(.LCPI23_0)
412; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
413; CHECK-NEXT:    vlse16.v v16, (a0), zero
414; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
415; CHECK-NEXT:    vfredmin.vs v8, v8, v16
416; CHECK-NEXT:    vfmv.f.s fa0, v8
417; CHECK-NEXT:    ret
418  %red = call half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half> %v)
419  ret half %red
420}
421
422declare float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float>)
423
424define float @vreduce_fmin_nxv1f32(<vscale x 1 x float> %v) {
425; CHECK-LABEL: vreduce_fmin_nxv1f32:
426; CHECK:       # %bb.0:
427; CHECK-NEXT:    lui a0, %hi(.LCPI24_0)
428; CHECK-NEXT:    addi a0, a0, %lo(.LCPI24_0)
429; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
430; CHECK-NEXT:    vlse32.v v9, (a0), zero
431; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
432; CHECK-NEXT:    vfredmin.vs v8, v8, v9
433; CHECK-NEXT:    vfmv.f.s fa0, v8
434; CHECK-NEXT:    ret
435  %red = call float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
436  ret float %red
437}
438
439define float @vreduce_fmin_nxv1f32_nonans(<vscale x 1 x float> %v) {
440; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans:
441; CHECK:       # %bb.0:
442; CHECK-NEXT:    lui a0, %hi(.LCPI25_0)
443; CHECK-NEXT:    addi a0, a0, %lo(.LCPI25_0)
444; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
445; CHECK-NEXT:    vlse32.v v9, (a0), zero
446; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
447; CHECK-NEXT:    vfredmin.vs v8, v8, v9
448; CHECK-NEXT:    vfmv.f.s fa0, v8
449; CHECK-NEXT:    ret
450  %red = call nnan float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
451  ret float %red
452}
453
454define float @vreduce_fmin_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
455; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans_noinfs:
456; CHECK:       # %bb.0:
457; CHECK-NEXT:    lui a0, %hi(.LCPI26_0)
458; CHECK-NEXT:    addi a0, a0, %lo(.LCPI26_0)
459; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
460; CHECK-NEXT:    vlse32.v v9, (a0), zero
461; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
462; CHECK-NEXT:    vfredmin.vs v8, v8, v9
463; CHECK-NEXT:    vfmv.f.s fa0, v8
464; CHECK-NEXT:    ret
465  %red = call nnan ninf float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
466  ret float %red
467}
468
469declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>)
470
471define float @vreduce_fmin_nxv2f32(<vscale x 2 x float> %v) {
472; CHECK-LABEL: vreduce_fmin_nxv2f32:
473; CHECK:       # %bb.0:
474; CHECK-NEXT:    lui a0, %hi(.LCPI27_0)
475; CHECK-NEXT:    addi a0, a0, %lo(.LCPI27_0)
476; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
477; CHECK-NEXT:    vlse32.v v9, (a0), zero
478; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
479; CHECK-NEXT:    vfredmin.vs v8, v8, v9
480; CHECK-NEXT:    vfmv.f.s fa0, v8
481; CHECK-NEXT:    ret
482  %red = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %v)
483  ret float %red
484}
485
486declare float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float>)
487
488define float @vreduce_fmin_nxv4f32(<vscale x 4 x float> %v) {
489; CHECK-LABEL: vreduce_fmin_nxv4f32:
490; CHECK:       # %bb.0:
491; CHECK-NEXT:    lui a0, %hi(.LCPI28_0)
492; CHECK-NEXT:    addi a0, a0, %lo(.LCPI28_0)
493; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
494; CHECK-NEXT:    vlse32.v v10, (a0), zero
495; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
496; CHECK-NEXT:    vfredmin.vs v8, v8, v10
497; CHECK-NEXT:    vfmv.f.s fa0, v8
498; CHECK-NEXT:    ret
499  %red = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %v)
500  ret float %red
501}
502
503declare float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float>)
504
505define float @vreduce_fmin_nxv32f32(<vscale x 32 x float> %v) {
506; CHECK-LABEL: vreduce_fmin_nxv32f32:
507; CHECK:       # %bb.0:
508; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
509; CHECK-NEXT:    vfmin.vv v8, v8, v16
510; CHECK-NEXT:    lui a0, %hi(.LCPI29_0)
511; CHECK-NEXT:    addi a0, a0, %lo(.LCPI29_0)
512; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
513; CHECK-NEXT:    vlse32.v v16, (a0), zero
514; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
515; CHECK-NEXT:    vfredmin.vs v8, v8, v16
516; CHECK-NEXT:    vfmv.f.s fa0, v8
517; CHECK-NEXT:    ret
518  %red = call float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float> %v)
519  ret float %red
520}
521
522declare double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double>)
523
524define double @vreduce_fmin_nxv1f64(<vscale x 1 x double> %v) {
525; CHECK-LABEL: vreduce_fmin_nxv1f64:
526; CHECK:       # %bb.0:
527; CHECK-NEXT:    lui a0, %hi(.LCPI30_0)
528; CHECK-NEXT:    addi a0, a0, %lo(.LCPI30_0)
529; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
530; CHECK-NEXT:    vlse64.v v9, (a0), zero
531; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
532; CHECK-NEXT:    vfredmin.vs v8, v8, v9
533; CHECK-NEXT:    vfmv.f.s fa0, v8
534; CHECK-NEXT:    ret
535  %red = call double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
536  ret double %red
537}
538
539define double @vreduce_fmin_nxv1f64_nonans(<vscale x 1 x double> %v) {
540; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans:
541; CHECK:       # %bb.0:
542; CHECK-NEXT:    lui a0, %hi(.LCPI31_0)
543; CHECK-NEXT:    addi a0, a0, %lo(.LCPI31_0)
544; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
545; CHECK-NEXT:    vlse64.v v9, (a0), zero
546; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
547; CHECK-NEXT:    vfredmin.vs v8, v8, v9
548; CHECK-NEXT:    vfmv.f.s fa0, v8
549; CHECK-NEXT:    ret
550  %red = call nnan double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
551  ret double %red
552}
553
554define double @vreduce_fmin_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {
555; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans_noinfs:
556; CHECK:       # %bb.0:
557; CHECK-NEXT:    lui a0, %hi(.LCPI32_0)
558; CHECK-NEXT:    addi a0, a0, %lo(.LCPI32_0)
559; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
560; CHECK-NEXT:    vlse64.v v9, (a0), zero
561; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
562; CHECK-NEXT:    vfredmin.vs v8, v8, v9
563; CHECK-NEXT:    vfmv.f.s fa0, v8
564; CHECK-NEXT:    ret
565  %red = call nnan ninf double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
566  ret double %red
567}
568
569declare double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double>)
570
571define double @vreduce_fmin_nxv2f64(<vscale x 2 x double> %v) {
572; CHECK-LABEL: vreduce_fmin_nxv2f64:
573; CHECK:       # %bb.0:
574; CHECK-NEXT:    lui a0, %hi(.LCPI33_0)
575; CHECK-NEXT:    addi a0, a0, %lo(.LCPI33_0)
576; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
577; CHECK-NEXT:    vlse64.v v10, (a0), zero
578; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
579; CHECK-NEXT:    vfredmin.vs v8, v8, v10
580; CHECK-NEXT:    vfmv.f.s fa0, v8
581; CHECK-NEXT:    ret
582  %red = call double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double> %v)
583  ret double %red
584}
585
586declare double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double>)
587
588define double @vreduce_fmin_nxv4f64(<vscale x 4 x double> %v) {
589; CHECK-LABEL: vreduce_fmin_nxv4f64:
590; CHECK:       # %bb.0:
591; CHECK-NEXT:    lui a0, %hi(.LCPI34_0)
592; CHECK-NEXT:    addi a0, a0, %lo(.LCPI34_0)
593; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
594; CHECK-NEXT:    vlse64.v v12, (a0), zero
595; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
596; CHECK-NEXT:    vfredmin.vs v8, v8, v12
597; CHECK-NEXT:    vfmv.f.s fa0, v8
598; CHECK-NEXT:    ret
599  %red = call double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double> %v)
600  ret double %red
601}
602
603declare double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double>)
604
605define double @vreduce_fmin_nxv16f64(<vscale x 16 x double> %v) {
606; CHECK-LABEL: vreduce_fmin_nxv16f64:
607; CHECK:       # %bb.0:
608; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
609; CHECK-NEXT:    vfmin.vv v8, v8, v16
610; CHECK-NEXT:    lui a0, %hi(.LCPI35_0)
611; CHECK-NEXT:    addi a0, a0, %lo(.LCPI35_0)
612; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
613; CHECK-NEXT:    vlse64.v v16, (a0), zero
614; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
615; CHECK-NEXT:    vfredmin.vs v8, v8, v16
616; CHECK-NEXT:    vfmv.f.s fa0, v8
617; CHECK-NEXT:    ret
618  %red = call double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double> %v)
619  ret double %red
620}
621
622declare half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half>)
623
624define half @vreduce_fmax_nxv1f16(<vscale x 1 x half> %v) {
625; CHECK-LABEL: vreduce_fmax_nxv1f16:
626; CHECK:       # %bb.0:
627; CHECK-NEXT:    lui a0, %hi(.LCPI36_0)
628; CHECK-NEXT:    addi a0, a0, %lo(.LCPI36_0)
629; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
630; CHECK-NEXT:    vlse16.v v9, (a0), zero
631; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
632; CHECK-NEXT:    vfredmax.vs v8, v8, v9
633; CHECK-NEXT:    vfmv.f.s fa0, v8
634; CHECK-NEXT:    ret
635  %red = call half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
636  ret half %red
637}
638
639define half @vreduce_fmax_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
640; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans:
641; CHECK:       # %bb.0:
642; CHECK-NEXT:    lui a0, %hi(.LCPI37_0)
643; CHECK-NEXT:    addi a0, a0, %lo(.LCPI37_0)
644; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
645; CHECK-NEXT:    vlse16.v v9, (a0), zero
646; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
647; CHECK-NEXT:    vfredmax.vs v8, v8, v9
648; CHECK-NEXT:    vfmv.f.s fa0, v8
649; CHECK-NEXT:    ret
650  %red = call nnan half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
651  ret half %red
652}
653
654define half @vreduce_fmax_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
655; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans_noinfs:
656; CHECK:       # %bb.0:
657; CHECK-NEXT:    lui a0, %hi(.LCPI38_0)
658; CHECK-NEXT:    addi a0, a0, %lo(.LCPI38_0)
659; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
660; CHECK-NEXT:    vlse16.v v9, (a0), zero
661; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
662; CHECK-NEXT:    vfredmax.vs v8, v8, v9
663; CHECK-NEXT:    vfmv.f.s fa0, v8
664; CHECK-NEXT:    ret
665  %red = call nnan ninf half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
666  ret half %red
667}
668
669declare half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half>)
670
671define half @vreduce_fmax_nxv2f16(<vscale x 2 x half> %v) {
672; CHECK-LABEL: vreduce_fmax_nxv2f16:
673; CHECK:       # %bb.0:
674; CHECK-NEXT:    lui a0, %hi(.LCPI39_0)
675; CHECK-NEXT:    addi a0, a0, %lo(.LCPI39_0)
676; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
677; CHECK-NEXT:    vlse16.v v9, (a0), zero
678; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
679; CHECK-NEXT:    vfredmax.vs v8, v8, v9
680; CHECK-NEXT:    vfmv.f.s fa0, v8
681; CHECK-NEXT:    ret
682  %red = call half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half> %v)
683  ret half %red
684}
685
686declare half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half>)
687
688define half @vreduce_fmax_nxv4f16(<vscale x 4 x half> %v) {
689; CHECK-LABEL: vreduce_fmax_nxv4f16:
690; CHECK:       # %bb.0:
691; CHECK-NEXT:    lui a0, %hi(.LCPI40_0)
692; CHECK-NEXT:    addi a0, a0, %lo(.LCPI40_0)
693; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
694; CHECK-NEXT:    vlse16.v v9, (a0), zero
695; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
696; CHECK-NEXT:    vfredmax.vs v8, v8, v9
697; CHECK-NEXT:    vfmv.f.s fa0, v8
698; CHECK-NEXT:    ret
699  %red = call half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half> %v)
700  ret half %red
701}
702
703declare half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half>)
704
705define half @vreduce_fmax_nxv64f16(<vscale x 64 x half> %v) {
706; CHECK-LABEL: vreduce_fmax_nxv64f16:
707; CHECK:       # %bb.0:
708; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
709; CHECK-NEXT:    vfmax.vv v8, v8, v16
710; CHECK-NEXT:    lui a0, %hi(.LCPI41_0)
711; CHECK-NEXT:    addi a0, a0, %lo(.LCPI41_0)
712; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
713; CHECK-NEXT:    vlse16.v v16, (a0), zero
714; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
715; CHECK-NEXT:    vfredmax.vs v8, v8, v16
716; CHECK-NEXT:    vfmv.f.s fa0, v8
717; CHECK-NEXT:    ret
718  %red = call half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half> %v)
719  ret half %red
720}
721
722declare float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float>)
723
724define float @vreduce_fmax_nxv1f32(<vscale x 1 x float> %v) {
725; CHECK-LABEL: vreduce_fmax_nxv1f32:
726; CHECK:       # %bb.0:
727; CHECK-NEXT:    lui a0, %hi(.LCPI42_0)
728; CHECK-NEXT:    addi a0, a0, %lo(.LCPI42_0)
729; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
730; CHECK-NEXT:    vlse32.v v9, (a0), zero
731; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
732; CHECK-NEXT:    vfredmax.vs v8, v8, v9
733; CHECK-NEXT:    vfmv.f.s fa0, v8
734; CHECK-NEXT:    ret
735  %red = call float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
736  ret float %red
737}
738
739define float @vreduce_fmax_nxv1f32_nonans(<vscale x 1 x float> %v) {
740; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans:
741; CHECK:       # %bb.0:
742; CHECK-NEXT:    lui a0, %hi(.LCPI43_0)
743; CHECK-NEXT:    addi a0, a0, %lo(.LCPI43_0)
744; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
745; CHECK-NEXT:    vlse32.v v9, (a0), zero
746; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
747; CHECK-NEXT:    vfredmax.vs v8, v8, v9
748; CHECK-NEXT:    vfmv.f.s fa0, v8
749; CHECK-NEXT:    ret
750  %red = call nnan float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
751  ret float %red
752}
753
754define float @vreduce_fmax_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
755; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans_noinfs:
756; CHECK:       # %bb.0:
757; CHECK-NEXT:    lui a0, %hi(.LCPI44_0)
758; CHECK-NEXT:    addi a0, a0, %lo(.LCPI44_0)
759; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
760; CHECK-NEXT:    vlse32.v v9, (a0), zero
761; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
762; CHECK-NEXT:    vfredmax.vs v8, v8, v9
763; CHECK-NEXT:    vfmv.f.s fa0, v8
764; CHECK-NEXT:    ret
765  %red = call nnan ninf float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
766  ret float %red
767}
768
769declare float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float>)
770
771define float @vreduce_fmax_nxv2f32(<vscale x 2 x float> %v) {
772; CHECK-LABEL: vreduce_fmax_nxv2f32:
773; CHECK:       # %bb.0:
774; CHECK-NEXT:    lui a0, %hi(.LCPI45_0)
775; CHECK-NEXT:    addi a0, a0, %lo(.LCPI45_0)
776; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
777; CHECK-NEXT:    vlse32.v v9, (a0), zero
778; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
779; CHECK-NEXT:    vfredmax.vs v8, v8, v9
780; CHECK-NEXT:    vfmv.f.s fa0, v8
781; CHECK-NEXT:    ret
782  %red = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %v)
783  ret float %red
784}
785
786declare float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float>)
787
788define float @vreduce_fmax_nxv4f32(<vscale x 4 x float> %v) {
789; CHECK-LABEL: vreduce_fmax_nxv4f32:
790; CHECK:       # %bb.0:
791; CHECK-NEXT:    lui a0, %hi(.LCPI46_0)
792; CHECK-NEXT:    addi a0, a0, %lo(.LCPI46_0)
793; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
794; CHECK-NEXT:    vlse32.v v10, (a0), zero
795; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
796; CHECK-NEXT:    vfredmax.vs v8, v8, v10
797; CHECK-NEXT:    vfmv.f.s fa0, v8
798; CHECK-NEXT:    ret
799  %red = call float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float> %v)
800  ret float %red
801}
802
803declare float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float>)
804
805define float @vreduce_fmax_nxv32f32(<vscale x 32 x float> %v) {
806; CHECK-LABEL: vreduce_fmax_nxv32f32:
807; CHECK:       # %bb.0:
808; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
809; CHECK-NEXT:    vfmax.vv v8, v8, v16
810; CHECK-NEXT:    lui a0, %hi(.LCPI47_0)
811; CHECK-NEXT:    addi a0, a0, %lo(.LCPI47_0)
812; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
813; CHECK-NEXT:    vlse32.v v16, (a0), zero
814; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
815; CHECK-NEXT:    vfredmax.vs v8, v8, v16
816; CHECK-NEXT:    vfmv.f.s fa0, v8
817; CHECK-NEXT:    ret
818  %red = call float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float> %v)
819  ret float %red
820}
821
822declare double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double>)
823
824define double @vreduce_fmax_nxv1f64(<vscale x 1 x double> %v) {
825; CHECK-LABEL: vreduce_fmax_nxv1f64:
826; CHECK:       # %bb.0:
827; CHECK-NEXT:    lui a0, %hi(.LCPI48_0)
828; CHECK-NEXT:    addi a0, a0, %lo(.LCPI48_0)
829; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
830; CHECK-NEXT:    vlse64.v v9, (a0), zero
831; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
832; CHECK-NEXT:    vfredmax.vs v8, v8, v9
833; CHECK-NEXT:    vfmv.f.s fa0, v8
834; CHECK-NEXT:    ret
835  %red = call double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
836  ret double %red
837}
838
839define double @vreduce_fmax_nxv1f64_nonans(<vscale x 1 x double> %v) {
840; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans:
841; CHECK:       # %bb.0:
842; CHECK-NEXT:    lui a0, %hi(.LCPI49_0)
843; CHECK-NEXT:    addi a0, a0, %lo(.LCPI49_0)
844; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
845; CHECK-NEXT:    vlse64.v v9, (a0), zero
846; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
847; CHECK-NEXT:    vfredmax.vs v8, v8, v9
848; CHECK-NEXT:    vfmv.f.s fa0, v8
849; CHECK-NEXT:    ret
850  %red = call nnan double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
851  ret double %red
852}
853
854define double @vreduce_fmax_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {
855; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans_noinfs:
856; CHECK:       # %bb.0:
857; CHECK-NEXT:    lui a0, %hi(.LCPI50_0)
858; CHECK-NEXT:    addi a0, a0, %lo(.LCPI50_0)
859; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
860; CHECK-NEXT:    vlse64.v v9, (a0), zero
861; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
862; CHECK-NEXT:    vfredmax.vs v8, v8, v9
863; CHECK-NEXT:    vfmv.f.s fa0, v8
864; CHECK-NEXT:    ret
865  %red = call nnan ninf double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
866  ret double %red
867}
868
869declare double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double>)
870
871define double @vreduce_fmax_nxv2f64(<vscale x 2 x double> %v) {
872; CHECK-LABEL: vreduce_fmax_nxv2f64:
873; CHECK:       # %bb.0:
874; CHECK-NEXT:    lui a0, %hi(.LCPI51_0)
875; CHECK-NEXT:    addi a0, a0, %lo(.LCPI51_0)
876; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
877; CHECK-NEXT:    vlse64.v v10, (a0), zero
878; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
879; CHECK-NEXT:    vfredmax.vs v8, v8, v10
880; CHECK-NEXT:    vfmv.f.s fa0, v8
881; CHECK-NEXT:    ret
882  %red = call double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double> %v)
883  ret double %red
884}
885
886declare double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double>)
887
888define double @vreduce_fmax_nxv4f64(<vscale x 4 x double> %v) {
889; CHECK-LABEL: vreduce_fmax_nxv4f64:
890; CHECK:       # %bb.0:
891; CHECK-NEXT:    lui a0, %hi(.LCPI52_0)
892; CHECK-NEXT:    addi a0, a0, %lo(.LCPI52_0)
893; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
894; CHECK-NEXT:    vlse64.v v12, (a0), zero
895; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
896; CHECK-NEXT:    vfredmax.vs v8, v8, v12
897; CHECK-NEXT:    vfmv.f.s fa0, v8
898; CHECK-NEXT:    ret
899  %red = call double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double> %v)
900  ret double %red
901}
902
903declare double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double>)
904
905define double @vreduce_fmax_nxv16f64(<vscale x 16 x double> %v) {
906; CHECK-LABEL: vreduce_fmax_nxv16f64:
907; CHECK:       # %bb.0:
908; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
909; CHECK-NEXT:    vfmax.vv v8, v8, v16
910; CHECK-NEXT:    lui a0, %hi(.LCPI53_0)
911; CHECK-NEXT:    addi a0, a0, %lo(.LCPI53_0)
912; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
913; CHECK-NEXT:    vlse64.v v16, (a0), zero
914; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
915; CHECK-NEXT:    vfredmax.vs v8, v8, v16
916; CHECK-NEXT:    vfmv.f.s fa0, v8
917; CHECK-NEXT:    ret
918  %red = call double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double> %v)
919  ret double %red
920}
921
922define float @vreduce_nsz_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
923; CHECK-LABEL: vreduce_nsz_fadd_nxv1f32:
924; CHECK:       # %bb.0:
925; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
926; CHECK-NEXT:    vmv.s.x v9, zero
927; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
928; CHECK-NEXT:    vfredusum.vs v8, v8, v9
929; CHECK-NEXT:    vfmv.f.s ft0, v8
930; CHECK-NEXT:    fadd.s fa0, fa0, ft0
931; CHECK-NEXT:    ret
932  %red = call reassoc nsz float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
933  ret float %red
934}
935