1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6
7declare half @llvm.vector.reduce.fadd.nxv1f16(half, <vscale x 1 x half>)
8
9define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
10; CHECK-LABEL: vreduce_fadd_nxv1f16:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
13; CHECK-NEXT:    vfmv.s.f v9, fa0
14; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
15; CHECK-NEXT:    vfredusum.vs v8, v8, v9
16; CHECK-NEXT:    vfmv.f.s fa0, v8
17; CHECK-NEXT:    ret
18  %red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
19  ret half %red
20}
21
22define half @vreduce_ord_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
23; CHECK-LABEL: vreduce_ord_fadd_nxv1f16:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
26; CHECK-NEXT:    vfmv.s.f v9, fa0
27; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
28; CHECK-NEXT:    vfredosum.vs v8, v8, v9
29; CHECK-NEXT:    vfmv.f.s fa0, v8
30; CHECK-NEXT:    ret
31  %red = call half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
32  ret half %red
33}
34
35declare half @llvm.vector.reduce.fadd.nxv2f16(half, <vscale x 2 x half>)
36
37define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
38; CHECK-LABEL: vreduce_fadd_nxv2f16:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
41; CHECK-NEXT:    vfmv.s.f v9, fa0
42; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
43; CHECK-NEXT:    vfredusum.vs v8, v8, v9
44; CHECK-NEXT:    vfmv.f.s fa0, v8
45; CHECK-NEXT:    ret
46  %red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
47  ret half %red
48}
49
50define half @vreduce_ord_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
51; CHECK-LABEL: vreduce_ord_fadd_nxv2f16:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
54; CHECK-NEXT:    vfmv.s.f v9, fa0
55; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
56; CHECK-NEXT:    vfredosum.vs v8, v8, v9
57; CHECK-NEXT:    vfmv.f.s fa0, v8
58; CHECK-NEXT:    ret
59  %red = call half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
60  ret half %red
61}
62
63declare half @llvm.vector.reduce.fadd.nxv4f16(half, <vscale x 4 x half>)
64
65define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
66; CHECK-LABEL: vreduce_fadd_nxv4f16:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
69; CHECK-NEXT:    vfmv.s.f v9, fa0
70; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
71; CHECK-NEXT:    vfredusum.vs v8, v8, v9
72; CHECK-NEXT:    vfmv.f.s fa0, v8
73; CHECK-NEXT:    ret
74  %red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
75  ret half %red
76}
77
78define half @vreduce_ord_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
79; CHECK-LABEL: vreduce_ord_fadd_nxv4f16:
80; CHECK:       # %bb.0:
81; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
82; CHECK-NEXT:    vfmv.s.f v9, fa0
83; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
84; CHECK-NEXT:    vfredosum.vs v8, v8, v9
85; CHECK-NEXT:    vfmv.f.s fa0, v8
86; CHECK-NEXT:    ret
87  %red = call half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
88  ret half %red
89}
90
91declare float @llvm.vector.reduce.fadd.nxv1f32(float, <vscale x 1 x float>)
92
93define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
94; CHECK-LABEL: vreduce_fadd_nxv1f32:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
97; CHECK-NEXT:    vfmv.s.f v9, fa0
98; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
99; CHECK-NEXT:    vfredusum.vs v8, v8, v9
100; CHECK-NEXT:    vfmv.f.s fa0, v8
101; CHECK-NEXT:    ret
102  %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
103  ret float %red
104}
105
106define float @vreduce_ord_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
107; CHECK-LABEL: vreduce_ord_fadd_nxv1f32:
108; CHECK:       # %bb.0:
109; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
110; CHECK-NEXT:    vfmv.s.f v9, fa0
111; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
112; CHECK-NEXT:    vfredosum.vs v8, v8, v9
113; CHECK-NEXT:    vfmv.f.s fa0, v8
114; CHECK-NEXT:    ret
115  %red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
116  ret float %red
117}
118
119define float @vreduce_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
120; CHECK-LABEL: vreduce_fwadd_nxv1f32:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
123; CHECK-NEXT:    vfmv.s.f v9, fa0
124; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
125; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
126; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
127; CHECK-NEXT:    vfmv.f.s fa0, v8
128; CHECK-NEXT:    ret
129  %e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
130  %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %e)
131  ret float %red
132}
133
134define float @vreduce_ord_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
135; CHECK-LABEL: vreduce_ord_fwadd_nxv1f32:
136; CHECK:       # %bb.0:
137; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
138; CHECK-NEXT:    vfmv.s.f v9, fa0
139; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
140; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
141; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
142; CHECK-NEXT:    vfmv.f.s fa0, v8
143; CHECK-NEXT:    ret
144  %e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
145  %red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %e)
146  ret float %red
147}
148
149declare float @llvm.vector.reduce.fadd.nxv2f32(float, <vscale x 2 x float>)
150
151define float @vreduce_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
152; CHECK-LABEL: vreduce_fadd_nxv2f32:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
155; CHECK-NEXT:    vfmv.s.f v9, fa0
156; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
157; CHECK-NEXT:    vfredusum.vs v8, v8, v9
158; CHECK-NEXT:    vfmv.f.s fa0, v8
159; CHECK-NEXT:    ret
160  %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
161  ret float %red
162}
163
164define float @vreduce_ord_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
165; CHECK-LABEL: vreduce_ord_fadd_nxv2f32:
166; CHECK:       # %bb.0:
167; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
168; CHECK-NEXT:    vfmv.s.f v9, fa0
169; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
170; CHECK-NEXT:    vfredosum.vs v8, v8, v9
171; CHECK-NEXT:    vfmv.f.s fa0, v8
172; CHECK-NEXT:    ret
173  %red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
174  ret float %red
175}
176
177define float @vreduce_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) {
178; CHECK-LABEL: vreduce_fwadd_nxv2f32:
179; CHECK:       # %bb.0:
180; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
181; CHECK-NEXT:    vfmv.s.f v9, fa0
182; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
183; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
184; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
185; CHECK-NEXT:    vfmv.f.s fa0, v8
186; CHECK-NEXT:    ret
187  %e = fpext <vscale x 2 x half> %v to <vscale x 2 x float>
188  %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %e)
189  ret float %red
190}
191
192define float @vreduce_ord_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) {
193; CHECK-LABEL: vreduce_ord_fwadd_nxv2f32:
194; CHECK:       # %bb.0:
195; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
196; CHECK-NEXT:    vfmv.s.f v9, fa0
197; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
198; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
199; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
200; CHECK-NEXT:    vfmv.f.s fa0, v8
201; CHECK-NEXT:    ret
202  %e = fpext <vscale x 2 x half> %v to <vscale x 2 x float>
203  %red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %e)
204  ret float %red
205}
206
207declare float @llvm.vector.reduce.fadd.nxv4f32(float, <vscale x 4 x float>)
208
209define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
210; CHECK-LABEL: vreduce_fadd_nxv4f32:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
213; CHECK-NEXT:    vfmv.s.f v10, fa0
214; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
215; CHECK-NEXT:    vfredusum.vs v8, v8, v10
216; CHECK-NEXT:    vfmv.f.s fa0, v8
217; CHECK-NEXT:    ret
218  %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
219  ret float %red
220}
221
222define float @vreduce_ord_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
223; CHECK-LABEL: vreduce_ord_fadd_nxv4f32:
224; CHECK:       # %bb.0:
225; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
226; CHECK-NEXT:    vfmv.s.f v10, fa0
227; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
228; CHECK-NEXT:    vfredosum.vs v8, v8, v10
229; CHECK-NEXT:    vfmv.f.s fa0, v8
230; CHECK-NEXT:    ret
231  %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
232  ret float %red
233}
234
235define float @vreduce_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
236; CHECK-LABEL: vreduce_fwadd_nxv4f32:
237; CHECK:       # %bb.0:
238; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
239; CHECK-NEXT:    vfmv.s.f v9, fa0
240; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
241; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
242; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
243; CHECK-NEXT:    vfmv.f.s fa0, v8
244; CHECK-NEXT:    ret
245  %e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
246  %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %e)
247  ret float %red
248}
249
250define float @vreduce_ord_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
251; CHECK-LABEL: vreduce_ord_fwadd_nxv4f32:
252; CHECK:       # %bb.0:
253; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
254; CHECK-NEXT:    vfmv.s.f v9, fa0
255; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
256; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
257; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
258; CHECK-NEXT:    vfmv.f.s fa0, v8
259; CHECK-NEXT:    ret
260  %e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
261  %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %e)
262  ret float %red
263}
264
265declare double @llvm.vector.reduce.fadd.nxv1f64(double, <vscale x 1 x double>)
266
267define double @vreduce_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
268; CHECK-LABEL: vreduce_fadd_nxv1f64:
269; CHECK:       # %bb.0:
270; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
271; CHECK-NEXT:    vfmv.s.f v9, fa0
272; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
273; CHECK-NEXT:    vfredusum.vs v8, v8, v9
274; CHECK-NEXT:    vfmv.f.s fa0, v8
275; CHECK-NEXT:    ret
276  %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
277  ret double %red
278}
279
280define double @vreduce_ord_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
281; CHECK-LABEL: vreduce_ord_fadd_nxv1f64:
282; CHECK:       # %bb.0:
283; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
284; CHECK-NEXT:    vfmv.s.f v9, fa0
285; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
286; CHECK-NEXT:    vfredosum.vs v8, v8, v9
287; CHECK-NEXT:    vfmv.f.s fa0, v8
288; CHECK-NEXT:    ret
289  %red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
290  ret double %red
291}
292
293define double @vreduce_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) {
294; CHECK-LABEL: vreduce_fwadd_nxv1f64:
295; CHECK:       # %bb.0:
296; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
297; CHECK-NEXT:    vfmv.s.f v9, fa0
298; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
299; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
300; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
301; CHECK-NEXT:    vfmv.f.s fa0, v8
302; CHECK-NEXT:    ret
303  %e = fpext <vscale x 1 x float> %v to <vscale x 1 x double>
304  %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %e)
305  ret double %red
306}
307
308define double @vreduce_ord_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) {
309; CHECK-LABEL: vreduce_ord_fwadd_nxv1f64:
310; CHECK:       # %bb.0:
311; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
312; CHECK-NEXT:    vfmv.s.f v9, fa0
313; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
314; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
315; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
316; CHECK-NEXT:    vfmv.f.s fa0, v8
317; CHECK-NEXT:    ret
318  %e = fpext <vscale x 1 x float> %v to <vscale x 1 x double>
319  %red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %e)
320  ret double %red
321}
322
323declare double @llvm.vector.reduce.fadd.nxv2f64(double, <vscale x 2 x double>)
324
325define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
326; CHECK-LABEL: vreduce_fadd_nxv2f64:
327; CHECK:       # %bb.0:
328; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
329; CHECK-NEXT:    vfmv.s.f v10, fa0
330; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
331; CHECK-NEXT:    vfredusum.vs v8, v8, v10
332; CHECK-NEXT:    vfmv.f.s fa0, v8
333; CHECK-NEXT:    ret
334  %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
335  ret double %red
336}
337
338define double @vreduce_ord_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
339; CHECK-LABEL: vreduce_ord_fadd_nxv2f64:
340; CHECK:       # %bb.0:
341; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
342; CHECK-NEXT:    vfmv.s.f v10, fa0
343; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
344; CHECK-NEXT:    vfredosum.vs v8, v8, v10
345; CHECK-NEXT:    vfmv.f.s fa0, v8
346; CHECK-NEXT:    ret
347  %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
348  ret double %red
349}
350
351define double @vreduce_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
352; CHECK-LABEL: vreduce_fwadd_nxv2f64:
353; CHECK:       # %bb.0:
354; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
355; CHECK-NEXT:    vfmv.s.f v9, fa0
356; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
357; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
358; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
359; CHECK-NEXT:    vfmv.f.s fa0, v8
360; CHECK-NEXT:    ret
361  %e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
362  %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %e)
363  ret double %red
364}
365
366define double @vreduce_ord_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
367; CHECK-LABEL: vreduce_ord_fwadd_nxv2f64:
368; CHECK:       # %bb.0:
369; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
370; CHECK-NEXT:    vfmv.s.f v9, fa0
371; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
372; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
373; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
374; CHECK-NEXT:    vfmv.f.s fa0, v8
375; CHECK-NEXT:    ret
376  %e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
377  %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %e)
378  ret double %red
379}
380
381declare double @llvm.vector.reduce.fadd.nxv4f64(double, <vscale x 4 x double>)
382
383define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
384; CHECK-LABEL: vreduce_fadd_nxv4f64:
385; CHECK:       # %bb.0:
386; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
387; CHECK-NEXT:    vfmv.s.f v12, fa0
388; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
389; CHECK-NEXT:    vfredusum.vs v8, v8, v12
390; CHECK-NEXT:    vfmv.f.s fa0, v8
391; CHECK-NEXT:    ret
392  %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
393  ret double %red
394}
395
396define double @vreduce_ord_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
397; CHECK-LABEL: vreduce_ord_fadd_nxv4f64:
398; CHECK:       # %bb.0:
399; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
400; CHECK-NEXT:    vfmv.s.f v12, fa0
401; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
402; CHECK-NEXT:    vfredosum.vs v8, v8, v12
403; CHECK-NEXT:    vfmv.f.s fa0, v8
404; CHECK-NEXT:    ret
405  %red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
406  ret double %red
407}
408
409define double @vreduce_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
410; CHECK-LABEL: vreduce_fwadd_nxv4f64:
411; CHECK:       # %bb.0:
412; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
413; CHECK-NEXT:    vfmv.s.f v10, fa0
414; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
415; CHECK-NEXT:    vfwredusum.vs v8, v8, v10
416; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
417; CHECK-NEXT:    vfmv.f.s fa0, v8
418; CHECK-NEXT:    ret
419  %e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>
420  %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %e)
421  ret double %red
422}
423
424define double @vreduce_ord_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
425; CHECK-LABEL: vreduce_ord_fwadd_nxv4f64:
426; CHECK:       # %bb.0:
427; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
428; CHECK-NEXT:    vfmv.s.f v10, fa0
429; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
430; CHECK-NEXT:    vfwredosum.vs v8, v8, v10
431; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
432; CHECK-NEXT:    vfmv.f.s fa0, v8
433; CHECK-NEXT:    ret
434  %e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>
435  %red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %e)
436  ret double %red
437}
438
439declare half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half>)
440
441define half @vreduce_fmin_nxv1f16(<vscale x 1 x half> %v) {
442; CHECK-LABEL: vreduce_fmin_nxv1f16:
443; CHECK:       # %bb.0:
444; CHECK-NEXT:    lui a0, %hi(.LCPI30_0)
445; CHECK-NEXT:    addi a0, a0, %lo(.LCPI30_0)
446; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
447; CHECK-NEXT:    vlse16.v v9, (a0), zero
448; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
449; CHECK-NEXT:    vfredmin.vs v8, v8, v9
450; CHECK-NEXT:    vfmv.f.s fa0, v8
451; CHECK-NEXT:    ret
452  %red = call half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
453  ret half %red
454}
455
456define half @vreduce_fmin_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
457; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans:
458; CHECK:       # %bb.0:
459; CHECK-NEXT:    lui a0, %hi(.LCPI31_0)
460; CHECK-NEXT:    addi a0, a0, %lo(.LCPI31_0)
461; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
462; CHECK-NEXT:    vlse16.v v9, (a0), zero
463; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
464; CHECK-NEXT:    vfredmin.vs v8, v8, v9
465; CHECK-NEXT:    vfmv.f.s fa0, v8
466; CHECK-NEXT:    ret
467  %red = call nnan half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
468  ret half %red
469}
470
471define half @vreduce_fmin_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
472; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans_noinfs:
473; CHECK:       # %bb.0:
474; CHECK-NEXT:    lui a0, %hi(.LCPI32_0)
475; CHECK-NEXT:    addi a0, a0, %lo(.LCPI32_0)
476; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
477; CHECK-NEXT:    vlse16.v v9, (a0), zero
478; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
479; CHECK-NEXT:    vfredmin.vs v8, v8, v9
480; CHECK-NEXT:    vfmv.f.s fa0, v8
481; CHECK-NEXT:    ret
482  %red = call nnan ninf half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
483  ret half %red
484}
485
486declare half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half>)
487
488define half @vreduce_fmin_nxv2f16(<vscale x 2 x half> %v) {
489; CHECK-LABEL: vreduce_fmin_nxv2f16:
490; CHECK:       # %bb.0:
491; CHECK-NEXT:    lui a0, %hi(.LCPI33_0)
492; CHECK-NEXT:    addi a0, a0, %lo(.LCPI33_0)
493; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
494; CHECK-NEXT:    vlse16.v v9, (a0), zero
495; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
496; CHECK-NEXT:    vfredmin.vs v8, v8, v9
497; CHECK-NEXT:    vfmv.f.s fa0, v8
498; CHECK-NEXT:    ret
499  %red = call half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half> %v)
500  ret half %red
501}
502
503declare half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half>)
504
505define half @vreduce_fmin_nxv4f16(<vscale x 4 x half> %v) {
506; CHECK-LABEL: vreduce_fmin_nxv4f16:
507; CHECK:       # %bb.0:
508; CHECK-NEXT:    lui a0, %hi(.LCPI34_0)
509; CHECK-NEXT:    addi a0, a0, %lo(.LCPI34_0)
510; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
511; CHECK-NEXT:    vlse16.v v9, (a0), zero
512; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
513; CHECK-NEXT:    vfredmin.vs v8, v8, v9
514; CHECK-NEXT:    vfmv.f.s fa0, v8
515; CHECK-NEXT:    ret
516  %red = call half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half> %v)
517  ret half %red
518}
519
520declare half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half>)
521
522define half @vreduce_fmin_nxv64f16(<vscale x 64 x half> %v) {
523; CHECK-LABEL: vreduce_fmin_nxv64f16:
524; CHECK:       # %bb.0:
525; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
526; CHECK-NEXT:    vfmin.vv v8, v8, v16
527; CHECK-NEXT:    lui a0, %hi(.LCPI35_0)
528; CHECK-NEXT:    addi a0, a0, %lo(.LCPI35_0)
529; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
530; CHECK-NEXT:    vlse16.v v16, (a0), zero
531; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
532; CHECK-NEXT:    vfredmin.vs v8, v8, v16
533; CHECK-NEXT:    vfmv.f.s fa0, v8
534; CHECK-NEXT:    ret
535  %red = call half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half> %v)
536  ret half %red
537}
538
539declare float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float>)
540
541define float @vreduce_fmin_nxv1f32(<vscale x 1 x float> %v) {
542; CHECK-LABEL: vreduce_fmin_nxv1f32:
543; CHECK:       # %bb.0:
544; CHECK-NEXT:    lui a0, %hi(.LCPI36_0)
545; CHECK-NEXT:    addi a0, a0, %lo(.LCPI36_0)
546; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
547; CHECK-NEXT:    vlse32.v v9, (a0), zero
548; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
549; CHECK-NEXT:    vfredmin.vs v8, v8, v9
550; CHECK-NEXT:    vfmv.f.s fa0, v8
551; CHECK-NEXT:    ret
552  %red = call float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
553  ret float %red
554}
555
556define float @vreduce_fmin_nxv1f32_nonans(<vscale x 1 x float> %v) {
557; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans:
558; CHECK:       # %bb.0:
559; CHECK-NEXT:    lui a0, %hi(.LCPI37_0)
560; CHECK-NEXT:    addi a0, a0, %lo(.LCPI37_0)
561; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
562; CHECK-NEXT:    vlse32.v v9, (a0), zero
563; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
564; CHECK-NEXT:    vfredmin.vs v8, v8, v9
565; CHECK-NEXT:    vfmv.f.s fa0, v8
566; CHECK-NEXT:    ret
567  %red = call nnan float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
568  ret float %red
569}
570
571define float @vreduce_fmin_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
572; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans_noinfs:
573; CHECK:       # %bb.0:
574; CHECK-NEXT:    lui a0, %hi(.LCPI38_0)
575; CHECK-NEXT:    addi a0, a0, %lo(.LCPI38_0)
576; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
577; CHECK-NEXT:    vlse32.v v9, (a0), zero
578; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
579; CHECK-NEXT:    vfredmin.vs v8, v8, v9
580; CHECK-NEXT:    vfmv.f.s fa0, v8
581; CHECK-NEXT:    ret
582  %red = call nnan ninf float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
583  ret float %red
584}
585
586declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>)
587
588define float @vreduce_fmin_nxv2f32(<vscale x 2 x float> %v) {
589; CHECK-LABEL: vreduce_fmin_nxv2f32:
590; CHECK:       # %bb.0:
591; CHECK-NEXT:    lui a0, %hi(.LCPI39_0)
592; CHECK-NEXT:    addi a0, a0, %lo(.LCPI39_0)
593; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
594; CHECK-NEXT:    vlse32.v v9, (a0), zero
595; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
596; CHECK-NEXT:    vfredmin.vs v8, v8, v9
597; CHECK-NEXT:    vfmv.f.s fa0, v8
598; CHECK-NEXT:    ret
599  %red = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %v)
600  ret float %red
601}
602
603declare float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float>)
604
605define float @vreduce_fmin_nxv4f32(<vscale x 4 x float> %v) {
606; CHECK-LABEL: vreduce_fmin_nxv4f32:
607; CHECK:       # %bb.0:
608; CHECK-NEXT:    lui a0, %hi(.LCPI40_0)
609; CHECK-NEXT:    addi a0, a0, %lo(.LCPI40_0)
610; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
611; CHECK-NEXT:    vlse32.v v10, (a0), zero
612; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
613; CHECK-NEXT:    vfredmin.vs v8, v8, v10
614; CHECK-NEXT:    vfmv.f.s fa0, v8
615; CHECK-NEXT:    ret
616  %red = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %v)
617  ret float %red
618}
619
620declare float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float>)
621
622define float @vreduce_fmin_nxv32f32(<vscale x 32 x float> %v) {
623; CHECK-LABEL: vreduce_fmin_nxv32f32:
624; CHECK:       # %bb.0:
625; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
626; CHECK-NEXT:    vfmin.vv v8, v8, v16
627; CHECK-NEXT:    lui a0, %hi(.LCPI41_0)
628; CHECK-NEXT:    addi a0, a0, %lo(.LCPI41_0)
629; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
630; CHECK-NEXT:    vlse32.v v16, (a0), zero
631; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
632; CHECK-NEXT:    vfredmin.vs v8, v8, v16
633; CHECK-NEXT:    vfmv.f.s fa0, v8
634; CHECK-NEXT:    ret
635  %red = call float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float> %v)
636  ret float %red
637}
638
639declare double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double>)
640
641define double @vreduce_fmin_nxv1f64(<vscale x 1 x double> %v) {
642; CHECK-LABEL: vreduce_fmin_nxv1f64:
643; CHECK:       # %bb.0:
644; CHECK-NEXT:    lui a0, %hi(.LCPI42_0)
645; CHECK-NEXT:    addi a0, a0, %lo(.LCPI42_0)
646; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
647; CHECK-NEXT:    vlse64.v v9, (a0), zero
648; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
649; CHECK-NEXT:    vfredmin.vs v8, v8, v9
650; CHECK-NEXT:    vfmv.f.s fa0, v8
651; CHECK-NEXT:    ret
652  %red = call double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
653  ret double %red
654}
655
656define double @vreduce_fmin_nxv1f64_nonans(<vscale x 1 x double> %v) {
657; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans:
658; CHECK:       # %bb.0:
659; CHECK-NEXT:    lui a0, %hi(.LCPI43_0)
660; CHECK-NEXT:    addi a0, a0, %lo(.LCPI43_0)
661; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
662; CHECK-NEXT:    vlse64.v v9, (a0), zero
663; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
664; CHECK-NEXT:    vfredmin.vs v8, v8, v9
665; CHECK-NEXT:    vfmv.f.s fa0, v8
666; CHECK-NEXT:    ret
667  %red = call nnan double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
668  ret double %red
669}
670
671define double @vreduce_fmin_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {
672; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans_noinfs:
673; CHECK:       # %bb.0:
674; CHECK-NEXT:    lui a0, %hi(.LCPI44_0)
675; CHECK-NEXT:    addi a0, a0, %lo(.LCPI44_0)
676; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
677; CHECK-NEXT:    vlse64.v v9, (a0), zero
678; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
679; CHECK-NEXT:    vfredmin.vs v8, v8, v9
680; CHECK-NEXT:    vfmv.f.s fa0, v8
681; CHECK-NEXT:    ret
682  %red = call nnan ninf double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
683  ret double %red
684}
685
686declare double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double>)
687
688define double @vreduce_fmin_nxv2f64(<vscale x 2 x double> %v) {
689; CHECK-LABEL: vreduce_fmin_nxv2f64:
690; CHECK:       # %bb.0:
691; CHECK-NEXT:    lui a0, %hi(.LCPI45_0)
692; CHECK-NEXT:    addi a0, a0, %lo(.LCPI45_0)
693; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
694; CHECK-NEXT:    vlse64.v v10, (a0), zero
695; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
696; CHECK-NEXT:    vfredmin.vs v8, v8, v10
697; CHECK-NEXT:    vfmv.f.s fa0, v8
698; CHECK-NEXT:    ret
699  %red = call double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double> %v)
700  ret double %red
701}
702
703declare double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double>)
704
705define double @vreduce_fmin_nxv4f64(<vscale x 4 x double> %v) {
706; CHECK-LABEL: vreduce_fmin_nxv4f64:
707; CHECK:       # %bb.0:
708; CHECK-NEXT:    lui a0, %hi(.LCPI46_0)
709; CHECK-NEXT:    addi a0, a0, %lo(.LCPI46_0)
710; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
711; CHECK-NEXT:    vlse64.v v12, (a0), zero
712; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
713; CHECK-NEXT:    vfredmin.vs v8, v8, v12
714; CHECK-NEXT:    vfmv.f.s fa0, v8
715; CHECK-NEXT:    ret
716  %red = call double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double> %v)
717  ret double %red
718}
719
720declare double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double>)
721
722define double @vreduce_fmin_nxv16f64(<vscale x 16 x double> %v) {
723; CHECK-LABEL: vreduce_fmin_nxv16f64:
724; CHECK:       # %bb.0:
725; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
726; CHECK-NEXT:    vfmin.vv v8, v8, v16
727; CHECK-NEXT:    lui a0, %hi(.LCPI47_0)
728; CHECK-NEXT:    addi a0, a0, %lo(.LCPI47_0)
729; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
730; CHECK-NEXT:    vlse64.v v16, (a0), zero
731; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
732; CHECK-NEXT:    vfredmin.vs v8, v8, v16
733; CHECK-NEXT:    vfmv.f.s fa0, v8
734; CHECK-NEXT:    ret
735  %red = call double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double> %v)
736  ret double %red
737}
738
739declare half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half>)
740
741define half @vreduce_fmax_nxv1f16(<vscale x 1 x half> %v) {
742; CHECK-LABEL: vreduce_fmax_nxv1f16:
743; CHECK:       # %bb.0:
744; CHECK-NEXT:    lui a0, %hi(.LCPI48_0)
745; CHECK-NEXT:    addi a0, a0, %lo(.LCPI48_0)
746; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
747; CHECK-NEXT:    vlse16.v v9, (a0), zero
748; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
749; CHECK-NEXT:    vfredmax.vs v8, v8, v9
750; CHECK-NEXT:    vfmv.f.s fa0, v8
751; CHECK-NEXT:    ret
752  %red = call half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
753  ret half %red
754}
755
756define half @vreduce_fmax_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
757; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans:
758; CHECK:       # %bb.0:
759; CHECK-NEXT:    lui a0, %hi(.LCPI49_0)
760; CHECK-NEXT:    addi a0, a0, %lo(.LCPI49_0)
761; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
762; CHECK-NEXT:    vlse16.v v9, (a0), zero
763; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
764; CHECK-NEXT:    vfredmax.vs v8, v8, v9
765; CHECK-NEXT:    vfmv.f.s fa0, v8
766; CHECK-NEXT:    ret
767  %red = call nnan half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
768  ret half %red
769}
770
771define half @vreduce_fmax_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
772; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans_noinfs:
773; CHECK:       # %bb.0:
774; CHECK-NEXT:    lui a0, %hi(.LCPI50_0)
775; CHECK-NEXT:    addi a0, a0, %lo(.LCPI50_0)
776; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
777; CHECK-NEXT:    vlse16.v v9, (a0), zero
778; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
779; CHECK-NEXT:    vfredmax.vs v8, v8, v9
780; CHECK-NEXT:    vfmv.f.s fa0, v8
781; CHECK-NEXT:    ret
782  %red = call nnan ninf half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
783  ret half %red
784}
785
786declare half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half>)
787
788define half @vreduce_fmax_nxv2f16(<vscale x 2 x half> %v) {
789; CHECK-LABEL: vreduce_fmax_nxv2f16:
790; CHECK:       # %bb.0:
791; CHECK-NEXT:    lui a0, %hi(.LCPI51_0)
792; CHECK-NEXT:    addi a0, a0, %lo(.LCPI51_0)
793; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
794; CHECK-NEXT:    vlse16.v v9, (a0), zero
795; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
796; CHECK-NEXT:    vfredmax.vs v8, v8, v9
797; CHECK-NEXT:    vfmv.f.s fa0, v8
798; CHECK-NEXT:    ret
799  %red = call half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half> %v)
800  ret half %red
801}
802
803declare half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half>)
804
805define half @vreduce_fmax_nxv4f16(<vscale x 4 x half> %v) {
806; CHECK-LABEL: vreduce_fmax_nxv4f16:
807; CHECK:       # %bb.0:
808; CHECK-NEXT:    lui a0, %hi(.LCPI52_0)
809; CHECK-NEXT:    addi a0, a0, %lo(.LCPI52_0)
810; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
811; CHECK-NEXT:    vlse16.v v9, (a0), zero
812; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
813; CHECK-NEXT:    vfredmax.vs v8, v8, v9
814; CHECK-NEXT:    vfmv.f.s fa0, v8
815; CHECK-NEXT:    ret
816  %red = call half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half> %v)
817  ret half %red
818}
819
820declare half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half>)
821
822define half @vreduce_fmax_nxv64f16(<vscale x 64 x half> %v) {
823; CHECK-LABEL: vreduce_fmax_nxv64f16:
824; CHECK:       # %bb.0:
825; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
826; CHECK-NEXT:    vfmax.vv v8, v8, v16
827; CHECK-NEXT:    lui a0, %hi(.LCPI53_0)
828; CHECK-NEXT:    addi a0, a0, %lo(.LCPI53_0)
829; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
830; CHECK-NEXT:    vlse16.v v16, (a0), zero
831; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
832; CHECK-NEXT:    vfredmax.vs v8, v8, v16
833; CHECK-NEXT:    vfmv.f.s fa0, v8
834; CHECK-NEXT:    ret
835  %red = call half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half> %v)
836  ret half %red
837}
838
839declare float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float>)
840
841define float @vreduce_fmax_nxv1f32(<vscale x 1 x float> %v) {
842; CHECK-LABEL: vreduce_fmax_nxv1f32:
843; CHECK:       # %bb.0:
844; CHECK-NEXT:    lui a0, %hi(.LCPI54_0)
845; CHECK-NEXT:    addi a0, a0, %lo(.LCPI54_0)
846; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
847; CHECK-NEXT:    vlse32.v v9, (a0), zero
848; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
849; CHECK-NEXT:    vfredmax.vs v8, v8, v9
850; CHECK-NEXT:    vfmv.f.s fa0, v8
851; CHECK-NEXT:    ret
852  %red = call float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
853  ret float %red
854}
855
856define float @vreduce_fmax_nxv1f32_nonans(<vscale x 1 x float> %v) {
857; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans:
858; CHECK:       # %bb.0:
859; CHECK-NEXT:    lui a0, %hi(.LCPI55_0)
860; CHECK-NEXT:    addi a0, a0, %lo(.LCPI55_0)
861; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
862; CHECK-NEXT:    vlse32.v v9, (a0), zero
863; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
864; CHECK-NEXT:    vfredmax.vs v8, v8, v9
865; CHECK-NEXT:    vfmv.f.s fa0, v8
866; CHECK-NEXT:    ret
867  %red = call nnan float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
868  ret float %red
869}
870
871define float @vreduce_fmax_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
872; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans_noinfs:
873; CHECK:       # %bb.0:
874; CHECK-NEXT:    lui a0, %hi(.LCPI56_0)
875; CHECK-NEXT:    addi a0, a0, %lo(.LCPI56_0)
876; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
877; CHECK-NEXT:    vlse32.v v9, (a0), zero
878; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
879; CHECK-NEXT:    vfredmax.vs v8, v8, v9
880; CHECK-NEXT:    vfmv.f.s fa0, v8
881; CHECK-NEXT:    ret
882  %red = call nnan ninf float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
883  ret float %red
884}
885
886declare float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float>)
887
888define float @vreduce_fmax_nxv2f32(<vscale x 2 x float> %v) {
889; CHECK-LABEL: vreduce_fmax_nxv2f32:
890; CHECK:       # %bb.0:
891; CHECK-NEXT:    lui a0, %hi(.LCPI57_0)
892; CHECK-NEXT:    addi a0, a0, %lo(.LCPI57_0)
893; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
894; CHECK-NEXT:    vlse32.v v9, (a0), zero
895; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
896; CHECK-NEXT:    vfredmax.vs v8, v8, v9
897; CHECK-NEXT:    vfmv.f.s fa0, v8
898; CHECK-NEXT:    ret
899  %red = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %v)
900  ret float %red
901}
902
903declare float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float>)
904
905define float @vreduce_fmax_nxv4f32(<vscale x 4 x float> %v) {
906; CHECK-LABEL: vreduce_fmax_nxv4f32:
907; CHECK:       # %bb.0:
908; CHECK-NEXT:    lui a0, %hi(.LCPI58_0)
909; CHECK-NEXT:    addi a0, a0, %lo(.LCPI58_0)
910; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
911; CHECK-NEXT:    vlse32.v v10, (a0), zero
912; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
913; CHECK-NEXT:    vfredmax.vs v8, v8, v10
914; CHECK-NEXT:    vfmv.f.s fa0, v8
915; CHECK-NEXT:    ret
916  %red = call float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float> %v)
917  ret float %red
918}
919
920declare float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float>)
921
922define float @vreduce_fmax_nxv32f32(<vscale x 32 x float> %v) {
923; CHECK-LABEL: vreduce_fmax_nxv32f32:
924; CHECK:       # %bb.0:
925; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
926; CHECK-NEXT:    vfmax.vv v8, v8, v16
927; CHECK-NEXT:    lui a0, %hi(.LCPI59_0)
928; CHECK-NEXT:    addi a0, a0, %lo(.LCPI59_0)
929; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
930; CHECK-NEXT:    vlse32.v v16, (a0), zero
931; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
932; CHECK-NEXT:    vfredmax.vs v8, v8, v16
933; CHECK-NEXT:    vfmv.f.s fa0, v8
934; CHECK-NEXT:    ret
935  %red = call float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float> %v)
936  ret float %red
937}
938
939declare double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double>)
940
941define double @vreduce_fmax_nxv1f64(<vscale x 1 x double> %v) {
942; CHECK-LABEL: vreduce_fmax_nxv1f64:
943; CHECK:       # %bb.0:
944; CHECK-NEXT:    lui a0, %hi(.LCPI60_0)
945; CHECK-NEXT:    addi a0, a0, %lo(.LCPI60_0)
946; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
947; CHECK-NEXT:    vlse64.v v9, (a0), zero
948; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
949; CHECK-NEXT:    vfredmax.vs v8, v8, v9
950; CHECK-NEXT:    vfmv.f.s fa0, v8
951; CHECK-NEXT:    ret
952  %red = call double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
953  ret double %red
954}
955
956define double @vreduce_fmax_nxv1f64_nonans(<vscale x 1 x double> %v) {
957; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans:
958; CHECK:       # %bb.0:
959; CHECK-NEXT:    lui a0, %hi(.LCPI61_0)
960; CHECK-NEXT:    addi a0, a0, %lo(.LCPI61_0)
961; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
962; CHECK-NEXT:    vlse64.v v9, (a0), zero
963; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
964; CHECK-NEXT:    vfredmax.vs v8, v8, v9
965; CHECK-NEXT:    vfmv.f.s fa0, v8
966; CHECK-NEXT:    ret
967  %red = call nnan double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
968  ret double %red
969}
970
971define double @vreduce_fmax_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {
972; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans_noinfs:
973; CHECK:       # %bb.0:
974; CHECK-NEXT:    lui a0, %hi(.LCPI62_0)
975; CHECK-NEXT:    addi a0, a0, %lo(.LCPI62_0)
976; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
977; CHECK-NEXT:    vlse64.v v9, (a0), zero
978; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
979; CHECK-NEXT:    vfredmax.vs v8, v8, v9
980; CHECK-NEXT:    vfmv.f.s fa0, v8
981; CHECK-NEXT:    ret
982  %red = call nnan ninf double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
983  ret double %red
984}
985
986declare double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double>)
987
988define double @vreduce_fmax_nxv2f64(<vscale x 2 x double> %v) {
989; CHECK-LABEL: vreduce_fmax_nxv2f64:
990; CHECK:       # %bb.0:
991; CHECK-NEXT:    lui a0, %hi(.LCPI63_0)
992; CHECK-NEXT:    addi a0, a0, %lo(.LCPI63_0)
993; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
994; CHECK-NEXT:    vlse64.v v10, (a0), zero
995; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
996; CHECK-NEXT:    vfredmax.vs v8, v8, v10
997; CHECK-NEXT:    vfmv.f.s fa0, v8
998; CHECK-NEXT:    ret
999  %red = call double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double> %v)
1000  ret double %red
1001}
1002
1003declare double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double>)
1004
1005define double @vreduce_fmax_nxv4f64(<vscale x 4 x double> %v) {
1006; CHECK-LABEL: vreduce_fmax_nxv4f64:
1007; CHECK:       # %bb.0:
1008; CHECK-NEXT:    lui a0, %hi(.LCPI64_0)
1009; CHECK-NEXT:    addi a0, a0, %lo(.LCPI64_0)
1010; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
1011; CHECK-NEXT:    vlse64.v v12, (a0), zero
1012; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
1013; CHECK-NEXT:    vfredmax.vs v8, v8, v12
1014; CHECK-NEXT:    vfmv.f.s fa0, v8
1015; CHECK-NEXT:    ret
1016  %red = call double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double> %v)
1017  ret double %red
1018}
1019
1020declare double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double>)
1021
1022define double @vreduce_fmax_nxv16f64(<vscale x 16 x double> %v) {
1023; CHECK-LABEL: vreduce_fmax_nxv16f64:
1024; CHECK:       # %bb.0:
1025; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1026; CHECK-NEXT:    vfmax.vv v8, v8, v16
1027; CHECK-NEXT:    lui a0, %hi(.LCPI65_0)
1028; CHECK-NEXT:    addi a0, a0, %lo(.LCPI65_0)
1029; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
1030; CHECK-NEXT:    vlse64.v v16, (a0), zero
1031; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1032; CHECK-NEXT:    vfredmax.vs v8, v8, v16
1033; CHECK-NEXT:    vfmv.f.s fa0, v8
1034; CHECK-NEXT:    ret
1035  %red = call double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double> %v)
1036  ret double %red
1037}
1038
1039define float @vreduce_nsz_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
1040; CHECK-LABEL: vreduce_nsz_fadd_nxv1f32:
1041; CHECK:       # %bb.0:
1042; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
1043; CHECK-NEXT:    vfmv.s.f v9, fa0
1044; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
1045; CHECK-NEXT:    vfredusum.vs v8, v8, v9
1046; CHECK-NEXT:    vfmv.f.s fa0, v8
1047; CHECK-NEXT:    ret
1048  %red = call reassoc nsz float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
1049  ret float %red
1050}
1051
1052; Test Widen VECREDUCE_SEQ_FADD
1053declare half @llvm.vector.reduce.fadd.nxv3f16(half, <vscale x 3 x half>)
1054
1055define half @vreduce_ord_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) {
1056; CHECK-LABEL: vreduce_ord_fadd_nxv3f16:
1057; CHECK:       # %bb.0:
1058; CHECK-NEXT:    csrr a0, vlenb
1059; CHECK-NEXT:    srli a0, a0, 3
1060; CHECK-NEXT:    slli a1, a0, 1
1061; CHECK-NEXT:    add a1, a1, a0
1062; CHECK-NEXT:    add a0, a1, a0
1063; CHECK-NEXT:    fmv.h.x ft0, zero
1064; CHECK-NEXT:    fneg.h ft0, ft0
1065; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, mu
1066; CHECK-NEXT:    vfmv.v.f v9, ft0
1067; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, mu
1068; CHECK-NEXT:    vslideup.vx v8, v9, a1
1069; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
1070; CHECK-NEXT:    vfmv.s.f v9, fa0
1071; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
1072; CHECK-NEXT:    vfredosum.vs v8, v8, v9
1073; CHECK-NEXT:    vfmv.f.s fa0, v8
1074; CHECK-NEXT:    ret
1075  %red = call half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v)
1076  ret half %red
1077}
1078
1079declare half @llvm.vector.reduce.fadd.nxv6f16(half, <vscale x 6 x half>)
1080
1081define half @vreduce_ord_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {
1082; CHECK-LABEL: vreduce_ord_fadd_nxv6f16:
1083; CHECK:       # %bb.0:
1084; CHECK-NEXT:    csrr a0, vlenb
1085; CHECK-NEXT:    srli a0, a0, 2
1086; CHECK-NEXT:    add a1, a0, a0
1087; CHECK-NEXT:    fmv.h.x ft0, zero
1088; CHECK-NEXT:    fneg.h ft0, ft0
1089; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, mu
1090; CHECK-NEXT:    vfmv.v.f v10, ft0
1091; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, mu
1092; CHECK-NEXT:    vslideup.vx v9, v10, a0
1093; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
1094; CHECK-NEXT:    vfmv.s.f v10, fa0
1095; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1096; CHECK-NEXT:    vfredosum.vs v8, v8, v10
1097; CHECK-NEXT:    vfmv.f.s fa0, v8
1098; CHECK-NEXT:    ret
1099  %red = call half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v)
1100  ret half %red
1101}
1102
1103declare half @llvm.vector.reduce.fadd.nxv10f16(half, <vscale x 10 x half>)
1104
1105define half @vreduce_ord_fadd_nxv10f16(<vscale x 10 x half> %v, half %s) {
1106; CHECK-LABEL: vreduce_ord_fadd_nxv10f16:
1107; CHECK:       # %bb.0:
1108; CHECK-NEXT:    csrr a0, vlenb
1109; CHECK-NEXT:    srli a0, a0, 2
1110; CHECK-NEXT:    add a1, a0, a0
1111; CHECK-NEXT:    fmv.h.x ft0, zero
1112; CHECK-NEXT:    fneg.h ft0, ft0
1113; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, mu
1114; CHECK-NEXT:    vfmv.v.f v12, ft0
1115; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, mu
1116; CHECK-NEXT:    vslideup.vx v10, v12, a0
1117; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, mu
1118; CHECK-NEXT:    vslideup.vi v11, v12, 0
1119; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, mu
1120; CHECK-NEXT:    vslideup.vx v11, v12, a0
1121; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
1122; CHECK-NEXT:    vfmv.s.f v12, fa0
1123; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
1124; CHECK-NEXT:    vfredosum.vs v8, v8, v12
1125; CHECK-NEXT:    vfmv.f.s fa0, v8
1126; CHECK-NEXT:    ret
1127  %red = call half @llvm.vector.reduce.fadd.nxv10f16(half %s, <vscale x 10 x half> %v)
1128  ret half %red
1129}
1130
1131declare half @llvm.vector.reduce.fadd.nxv12f16(half, <vscale x 12 x half>)
1132
1133define half @vreduce_ord_fadd_nxv12f16(<vscale x 12 x half> %v, half %s) {
1134; CHECK-LABEL: vreduce_ord_fadd_nxv12f16:
1135; CHECK:       # %bb.0:
1136; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
1137; CHECK-NEXT:    vfmv.s.f v12, fa0
1138; CHECK-NEXT:    fmv.h.x ft0, zero
1139; CHECK-NEXT:    fneg.h ft0, ft0
1140; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
1141; CHECK-NEXT:    vfmv.v.f v11, ft0
1142; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
1143; CHECK-NEXT:    vfredosum.vs v8, v8, v12
1144; CHECK-NEXT:    vfmv.f.s fa0, v8
1145; CHECK-NEXT:    ret
1146  %red = call half @llvm.vector.reduce.fadd.nxv12f16(half %s, <vscale x 12 x half> %v)
1147  ret half %red
1148}
1149
1150; Test Widen vector reduce type (fadd/fmin/fmax)
1151define half @vreduce_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) {
1152; CHECK-LABEL: vreduce_fadd_nxv3f16:
1153; CHECK:       # %bb.0:
1154; CHECK-NEXT:    csrr a0, vlenb
1155; CHECK-NEXT:    srli a0, a0, 3
1156; CHECK-NEXT:    slli a1, a0, 1
1157; CHECK-NEXT:    add a1, a1, a0
1158; CHECK-NEXT:    add a0, a1, a0
1159; CHECK-NEXT:    fmv.h.x ft0, zero
1160; CHECK-NEXT:    fneg.h ft0, ft0
1161; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, mu
1162; CHECK-NEXT:    vfmv.v.f v9, ft0
1163; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, mu
1164; CHECK-NEXT:    vslideup.vx v8, v9, a1
1165; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
1166; CHECK-NEXT:    vfmv.s.f v9, fa0
1167; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
1168; CHECK-NEXT:    vfredusum.vs v8, v8, v9
1169; CHECK-NEXT:    vfmv.f.s fa0, v8
1170; CHECK-NEXT:    ret
1171  %red = call reassoc half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v)
1172  ret half %red
1173}
1174
1175define half @vreduce_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {
1176; CHECK-LABEL: vreduce_fadd_nxv6f16:
1177; CHECK:       # %bb.0:
1178; CHECK-NEXT:    csrr a0, vlenb
1179; CHECK-NEXT:    srli a0, a0, 2
1180; CHECK-NEXT:    add a1, a0, a0
1181; CHECK-NEXT:    fmv.h.x ft0, zero
1182; CHECK-NEXT:    fneg.h ft0, ft0
1183; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, mu
1184; CHECK-NEXT:    vfmv.v.f v10, ft0
1185; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, mu
1186; CHECK-NEXT:    vslideup.vx v9, v10, a0
1187; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
1188; CHECK-NEXT:    vfmv.s.f v10, fa0
1189; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1190; CHECK-NEXT:    vfredusum.vs v8, v8, v10
1191; CHECK-NEXT:    vfmv.f.s fa0, v8
1192; CHECK-NEXT:    ret
1193  %red = call reassoc half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v)
1194  ret half %red
1195}
1196
1197declare half @llvm.vector.reduce.fmin.nxv10f16(<vscale x 10 x half>)
1198
1199define half @vreduce_fmin_nxv10f16(<vscale x 10 x half> %v) {
1200; CHECK-LABEL: vreduce_fmin_nxv10f16:
1201; CHECK:       # %bb.0:
1202; CHECK-NEXT:    csrr a0, vlenb
1203; CHECK-NEXT:    lui a1, %hi(.LCPI73_0)
1204; CHECK-NEXT:    flh ft0, %lo(.LCPI73_0)(a1)
1205; CHECK-NEXT:    srli a0, a0, 2
1206; CHECK-NEXT:    add a1, a0, a0
1207; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, mu
1208; CHECK-NEXT:    vfmv.v.f v12, ft0
1209; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, mu
1210; CHECK-NEXT:    vslideup.vx v10, v12, a0
1211; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, mu
1212; CHECK-NEXT:    vslideup.vi v11, v12, 0
1213; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, mu
1214; CHECK-NEXT:    vslideup.vx v11, v12, a0
1215; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
1216; CHECK-NEXT:    vfmv.s.f v12, ft0
1217; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
1218; CHECK-NEXT:    vfredmin.vs v8, v8, v12
1219; CHECK-NEXT:    vfmv.f.s fa0, v8
1220; CHECK-NEXT:    ret
1221  %red = call half @llvm.vector.reduce.fmin.nxv10f16(<vscale x 10 x half> %v)
1222  ret half %red
1223}
1224
1225declare half @llvm.vector.reduce.fmax.nxv12f16(<vscale x 12 x half>)
1226
1227define half @vreduce_fmax_nxv12f16(<vscale x 12 x half> %v) {
1228; CHECK-LABEL: vreduce_fmax_nxv12f16:
1229; CHECK:       # %bb.0:
1230; CHECK-NEXT:    lui a0, %hi(.LCPI74_0)
1231; CHECK-NEXT:    flh ft0, %lo(.LCPI74_0)(a0)
1232; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
1233; CHECK-NEXT:    vfmv.s.f v12, ft0
1234; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
1235; CHECK-NEXT:    vfmv.v.f v11, ft0
1236; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
1237; CHECK-NEXT:    vfredmax.vs v8, v8, v12
1238; CHECK-NEXT:    vfmv.f.s fa0, v8
1239; CHECK-NEXT:    ret
1240  %red = call half @llvm.vector.reduce.fmax.nxv12f16(<vscale x 12 x half> %v)
1241  ret half %red
1242}
1243