1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare half @llvm.vector.reduce.fadd.nxv1f16(half, <vscale x 1 x half>)
8
9define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
10; CHECK-LABEL: vreduce_fadd_nxv1f16:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    fmv.h.x ft0, zero
13; CHECK-NEXT:    fneg.h ft0, ft0
14; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
15; CHECK-NEXT:    vfmv.s.f v9, ft0
16; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
17; CHECK-NEXT:    vfredusum.vs v8, v8, v9
18; CHECK-NEXT:    vfmv.f.s ft0, v8
19; CHECK-NEXT:    fadd.h fa0, fa0, ft0
20; CHECK-NEXT:    ret
21  %red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
22  ret half %red
23}
24
25define half @vreduce_ord_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
26; CHECK-LABEL: vreduce_ord_fadd_nxv1f16:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
29; CHECK-NEXT:    vfmv.s.f v9, fa0
30; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
31; CHECK-NEXT:    vfredosum.vs v8, v8, v9
32; CHECK-NEXT:    vfmv.f.s fa0, v8
33; CHECK-NEXT:    ret
34  %red = call half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
35  ret half %red
36}
37
38declare half @llvm.vector.reduce.fadd.nxv2f16(half, <vscale x 2 x half>)
39
40define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
41; CHECK-LABEL: vreduce_fadd_nxv2f16:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    fmv.h.x ft0, zero
44; CHECK-NEXT:    fneg.h ft0, ft0
45; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
46; CHECK-NEXT:    vfmv.s.f v9, ft0
47; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
48; CHECK-NEXT:    vfredusum.vs v8, v8, v9
49; CHECK-NEXT:    vfmv.f.s ft0, v8
50; CHECK-NEXT:    fadd.h fa0, fa0, ft0
51; CHECK-NEXT:    ret
52  %red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
53  ret half %red
54}
55
56define half @vreduce_ord_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
57; CHECK-LABEL: vreduce_ord_fadd_nxv2f16:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
60; CHECK-NEXT:    vfmv.s.f v9, fa0
61; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
62; CHECK-NEXT:    vfredosum.vs v8, v8, v9
63; CHECK-NEXT:    vfmv.f.s fa0, v8
64; CHECK-NEXT:    ret
65  %red = call half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
66  ret half %red
67}
68
69declare half @llvm.vector.reduce.fadd.nxv4f16(half, <vscale x 4 x half>)
70
71define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
72; CHECK-LABEL: vreduce_fadd_nxv4f16:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    fmv.h.x ft0, zero
75; CHECK-NEXT:    fneg.h ft0, ft0
76; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
77; CHECK-NEXT:    vfmv.s.f v9, ft0
78; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
79; CHECK-NEXT:    vfredusum.vs v8, v8, v9
80; CHECK-NEXT:    vfmv.f.s ft0, v8
81; CHECK-NEXT:    fadd.h fa0, fa0, ft0
82; CHECK-NEXT:    ret
83  %red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
84  ret half %red
85}
86
87define half @vreduce_ord_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
88; CHECK-LABEL: vreduce_ord_fadd_nxv4f16:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
91; CHECK-NEXT:    vfmv.s.f v9, fa0
92; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
93; CHECK-NEXT:    vfredosum.vs v8, v8, v9
94; CHECK-NEXT:    vfmv.f.s fa0, v8
95; CHECK-NEXT:    ret
96  %red = call half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
97  ret half %red
98}
99
100declare float @llvm.vector.reduce.fadd.nxv1f32(float, <vscale x 1 x float>)
101
102define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
103; CHECK-LABEL: vreduce_fadd_nxv1f32:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    fmv.w.x ft0, zero
106; CHECK-NEXT:    fneg.s ft0, ft0
107; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
108; CHECK-NEXT:    vfmv.s.f v9, ft0
109; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
110; CHECK-NEXT:    vfredusum.vs v8, v8, v9
111; CHECK-NEXT:    vfmv.f.s ft0, v8
112; CHECK-NEXT:    fadd.s fa0, fa0, ft0
113; CHECK-NEXT:    ret
114  %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
115  ret float %red
116}
117
118define float @vreduce_ord_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
119; CHECK-LABEL: vreduce_ord_fadd_nxv1f32:
120; CHECK:       # %bb.0:
121; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
122; CHECK-NEXT:    vfmv.s.f v9, fa0
123; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
124; CHECK-NEXT:    vfredosum.vs v8, v8, v9
125; CHECK-NEXT:    vfmv.f.s fa0, v8
126; CHECK-NEXT:    ret
127  %red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
128  ret float %red
129}
130
131define float @vreduce_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
132; CHECK-LABEL: vreduce_fwadd_nxv1f32:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    fmv.w.x ft0, zero
135; CHECK-NEXT:    fneg.s ft0, ft0
136; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
137; CHECK-NEXT:    vfmv.s.f v9, ft0
138; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
139; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
140; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
141; CHECK-NEXT:    vfmv.f.s ft0, v8
142; CHECK-NEXT:    fadd.s fa0, fa0, ft0
143; CHECK-NEXT:    ret
144  %e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
145  %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %e)
146  ret float %red
147}
148
149define float @vreduce_ord_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {
150; CHECK-LABEL: vreduce_ord_fwadd_nxv1f32:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
153; CHECK-NEXT:    vfmv.s.f v9, fa0
154; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
155; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
156; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
157; CHECK-NEXT:    vfmv.f.s fa0, v8
158; CHECK-NEXT:    ret
159  %e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
160  %red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %e)
161  ret float %red
162}
163
164declare float @llvm.vector.reduce.fadd.nxv2f32(float, <vscale x 2 x float>)
165
166define float @vreduce_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
167; CHECK-LABEL: vreduce_fadd_nxv2f32:
168; CHECK:       # %bb.0:
169; CHECK-NEXT:    fmv.w.x ft0, zero
170; CHECK-NEXT:    fneg.s ft0, ft0
171; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
172; CHECK-NEXT:    vfmv.s.f v9, ft0
173; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
174; CHECK-NEXT:    vfredusum.vs v8, v8, v9
175; CHECK-NEXT:    vfmv.f.s ft0, v8
176; CHECK-NEXT:    fadd.s fa0, fa0, ft0
177; CHECK-NEXT:    ret
178  %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
179  ret float %red
180}
181
182define float @vreduce_ord_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
183; CHECK-LABEL: vreduce_ord_fadd_nxv2f32:
184; CHECK:       # %bb.0:
185; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
186; CHECK-NEXT:    vfmv.s.f v9, fa0
187; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
188; CHECK-NEXT:    vfredosum.vs v8, v8, v9
189; CHECK-NEXT:    vfmv.f.s fa0, v8
190; CHECK-NEXT:    ret
191  %red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
192  ret float %red
193}
194
195define float @vreduce_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) {
196; CHECK-LABEL: vreduce_fwadd_nxv2f32:
197; CHECK:       # %bb.0:
198; CHECK-NEXT:    fmv.w.x ft0, zero
199; CHECK-NEXT:    fneg.s ft0, ft0
200; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
201; CHECK-NEXT:    vfmv.s.f v9, ft0
202; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
203; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
204; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
205; CHECK-NEXT:    vfmv.f.s ft0, v8
206; CHECK-NEXT:    fadd.s fa0, fa0, ft0
207; CHECK-NEXT:    ret
208  %e = fpext <vscale x 2 x half> %v to <vscale x 2 x float>
209  %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %e)
210  ret float %red
211}
212
213define float @vreduce_ord_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) {
214; CHECK-LABEL: vreduce_ord_fwadd_nxv2f32:
215; CHECK:       # %bb.0:
216; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
217; CHECK-NEXT:    vfmv.s.f v9, fa0
218; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
219; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
220; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
221; CHECK-NEXT:    vfmv.f.s fa0, v8
222; CHECK-NEXT:    ret
223  %e = fpext <vscale x 2 x half> %v to <vscale x 2 x float>
224  %red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %e)
225  ret float %red
226}
227
228declare float @llvm.vector.reduce.fadd.nxv4f32(float, <vscale x 4 x float>)
229
230define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
231; CHECK-LABEL: vreduce_fadd_nxv4f32:
232; CHECK:       # %bb.0:
233; CHECK-NEXT:    fmv.w.x ft0, zero
234; CHECK-NEXT:    fneg.s ft0, ft0
235; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
236; CHECK-NEXT:    vfmv.s.f v10, ft0
237; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
238; CHECK-NEXT:    vfredusum.vs v8, v8, v10
239; CHECK-NEXT:    vfmv.f.s ft0, v8
240; CHECK-NEXT:    fadd.s fa0, fa0, ft0
241; CHECK-NEXT:    ret
242  %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
243  ret float %red
244}
245
246define float @vreduce_ord_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
247; CHECK-LABEL: vreduce_ord_fadd_nxv4f32:
248; CHECK:       # %bb.0:
249; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
250; CHECK-NEXT:    vfmv.s.f v10, fa0
251; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
252; CHECK-NEXT:    vfredosum.vs v8, v8, v10
253; CHECK-NEXT:    vfmv.f.s fa0, v8
254; CHECK-NEXT:    ret
255  %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
256  ret float %red
257}
258
259define float @vreduce_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
260; CHECK-LABEL: vreduce_fwadd_nxv4f32:
261; CHECK:       # %bb.0:
262; CHECK-NEXT:    fmv.w.x ft0, zero
263; CHECK-NEXT:    fneg.s ft0, ft0
264; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
265; CHECK-NEXT:    vfmv.s.f v9, ft0
266; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
267; CHECK-NEXT:    vfwredusum.vs v8, v8, v9
268; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
269; CHECK-NEXT:    vfmv.f.s ft0, v8
270; CHECK-NEXT:    fadd.s fa0, fa0, ft0
271; CHECK-NEXT:    ret
272  %e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
273  %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %e)
274  ret float %red
275}
276
277define float @vreduce_ord_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {
278; CHECK-LABEL: vreduce_ord_fwadd_nxv4f32:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
281; CHECK-NEXT:    vfmv.s.f v9, fa0
282; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
283; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
284; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
285; CHECK-NEXT:    vfmv.f.s fa0, v8
286; CHECK-NEXT:    ret
287  %e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>
288  %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %e)
289  ret float %red
290}
291
292declare double @llvm.vector.reduce.fadd.nxv1f64(double, <vscale x 1 x double>)
293
294define double @vreduce_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
295; RV32-LABEL: vreduce_fadd_nxv1f64:
296; RV32:       # %bb.0:
297; RV32-NEXT:    fcvt.d.w ft0, zero
298; RV32-NEXT:    fneg.d ft0, ft0
299; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
300; RV32-NEXT:    vfmv.s.f v9, ft0
301; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
302; RV32-NEXT:    vfredusum.vs v8, v8, v9
303; RV32-NEXT:    vfmv.f.s ft0, v8
304; RV32-NEXT:    fadd.d fa0, fa0, ft0
305; RV32-NEXT:    ret
306;
307; RV64-LABEL: vreduce_fadd_nxv1f64:
308; RV64:       # %bb.0:
309; RV64-NEXT:    fmv.d.x ft0, zero
310; RV64-NEXT:    fneg.d ft0, ft0
311; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
312; RV64-NEXT:    vfmv.s.f v9, ft0
313; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
314; RV64-NEXT:    vfredusum.vs v8, v8, v9
315; RV64-NEXT:    vfmv.f.s ft0, v8
316; RV64-NEXT:    fadd.d fa0, fa0, ft0
317; RV64-NEXT:    ret
318  %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
319  ret double %red
320}
321
322define double @vreduce_ord_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
323; CHECK-LABEL: vreduce_ord_fadd_nxv1f64:
324; CHECK:       # %bb.0:
325; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
326; CHECK-NEXT:    vfmv.s.f v9, fa0
327; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
328; CHECK-NEXT:    vfredosum.vs v8, v8, v9
329; CHECK-NEXT:    vfmv.f.s fa0, v8
330; CHECK-NEXT:    ret
331  %red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
332  ret double %red
333}
334
335define double @vreduce_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) {
336; RV32-LABEL: vreduce_fwadd_nxv1f64:
337; RV32:       # %bb.0:
338; RV32-NEXT:    fcvt.d.w ft0, zero
339; RV32-NEXT:    fneg.d ft0, ft0
340; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
341; RV32-NEXT:    vfmv.s.f v9, ft0
342; RV32-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
343; RV32-NEXT:    vfwredusum.vs v8, v8, v9
344; RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
345; RV32-NEXT:    vfmv.f.s ft0, v8
346; RV32-NEXT:    fadd.d fa0, fa0, ft0
347; RV32-NEXT:    ret
348;
349; RV64-LABEL: vreduce_fwadd_nxv1f64:
350; RV64:       # %bb.0:
351; RV64-NEXT:    fmv.d.x ft0, zero
352; RV64-NEXT:    fneg.d ft0, ft0
353; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
354; RV64-NEXT:    vfmv.s.f v9, ft0
355; RV64-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
356; RV64-NEXT:    vfwredusum.vs v8, v8, v9
357; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
358; RV64-NEXT:    vfmv.f.s ft0, v8
359; RV64-NEXT:    fadd.d fa0, fa0, ft0
360; RV64-NEXT:    ret
361  %e = fpext <vscale x 1 x float> %v to <vscale x 1 x double>
362  %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %e)
363  ret double %red
364}
365
366define double @vreduce_ord_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) {
367; CHECK-LABEL: vreduce_ord_fwadd_nxv1f64:
368; CHECK:       # %bb.0:
369; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
370; CHECK-NEXT:    vfmv.s.f v9, fa0
371; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
372; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
373; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
374; CHECK-NEXT:    vfmv.f.s fa0, v8
375; CHECK-NEXT:    ret
376  %e = fpext <vscale x 1 x float> %v to <vscale x 1 x double>
377  %red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %e)
378  ret double %red
379}
380
381declare double @llvm.vector.reduce.fadd.nxv2f64(double, <vscale x 2 x double>)
382
383define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
384; RV32-LABEL: vreduce_fadd_nxv2f64:
385; RV32:       # %bb.0:
386; RV32-NEXT:    fcvt.d.w ft0, zero
387; RV32-NEXT:    fneg.d ft0, ft0
388; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
389; RV32-NEXT:    vfmv.s.f v10, ft0
390; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
391; RV32-NEXT:    vfredusum.vs v8, v8, v10
392; RV32-NEXT:    vfmv.f.s ft0, v8
393; RV32-NEXT:    fadd.d fa0, fa0, ft0
394; RV32-NEXT:    ret
395;
396; RV64-LABEL: vreduce_fadd_nxv2f64:
397; RV64:       # %bb.0:
398; RV64-NEXT:    fmv.d.x ft0, zero
399; RV64-NEXT:    fneg.d ft0, ft0
400; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
401; RV64-NEXT:    vfmv.s.f v10, ft0
402; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
403; RV64-NEXT:    vfredusum.vs v8, v8, v10
404; RV64-NEXT:    vfmv.f.s ft0, v8
405; RV64-NEXT:    fadd.d fa0, fa0, ft0
406; RV64-NEXT:    ret
407  %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
408  ret double %red
409}
410
411define double @vreduce_ord_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
412; CHECK-LABEL: vreduce_ord_fadd_nxv2f64:
413; CHECK:       # %bb.0:
414; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
415; CHECK-NEXT:    vfmv.s.f v10, fa0
416; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
417; CHECK-NEXT:    vfredosum.vs v8, v8, v10
418; CHECK-NEXT:    vfmv.f.s fa0, v8
419; CHECK-NEXT:    ret
420  %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
421  ret double %red
422}
423
424define double @vreduce_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
425; RV32-LABEL: vreduce_fwadd_nxv2f64:
426; RV32:       # %bb.0:
427; RV32-NEXT:    fcvt.d.w ft0, zero
428; RV32-NEXT:    fneg.d ft0, ft0
429; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
430; RV32-NEXT:    vfmv.s.f v9, ft0
431; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
432; RV32-NEXT:    vfwredusum.vs v8, v8, v9
433; RV32-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
434; RV32-NEXT:    vfmv.f.s ft0, v8
435; RV32-NEXT:    fadd.d fa0, fa0, ft0
436; RV32-NEXT:    ret
437;
438; RV64-LABEL: vreduce_fwadd_nxv2f64:
439; RV64:       # %bb.0:
440; RV64-NEXT:    fmv.d.x ft0, zero
441; RV64-NEXT:    fneg.d ft0, ft0
442; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
443; RV64-NEXT:    vfmv.s.f v9, ft0
444; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
445; RV64-NEXT:    vfwredusum.vs v8, v8, v9
446; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
447; RV64-NEXT:    vfmv.f.s ft0, v8
448; RV64-NEXT:    fadd.d fa0, fa0, ft0
449; RV64-NEXT:    ret
450  %e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
451  %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %e)
452  ret double %red
453}
454
455define double @vreduce_ord_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {
456; CHECK-LABEL: vreduce_ord_fwadd_nxv2f64:
457; CHECK:       # %bb.0:
458; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
459; CHECK-NEXT:    vfmv.s.f v9, fa0
460; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
461; CHECK-NEXT:    vfwredosum.vs v8, v8, v9
462; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
463; CHECK-NEXT:    vfmv.f.s fa0, v8
464; CHECK-NEXT:    ret
465  %e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>
466  %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %e)
467  ret double %red
468}
469
470declare double @llvm.vector.reduce.fadd.nxv4f64(double, <vscale x 4 x double>)
471
472define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
473; RV32-LABEL: vreduce_fadd_nxv4f64:
474; RV32:       # %bb.0:
475; RV32-NEXT:    fcvt.d.w ft0, zero
476; RV32-NEXT:    fneg.d ft0, ft0
477; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
478; RV32-NEXT:    vfmv.s.f v12, ft0
479; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
480; RV32-NEXT:    vfredusum.vs v8, v8, v12
481; RV32-NEXT:    vfmv.f.s ft0, v8
482; RV32-NEXT:    fadd.d fa0, fa0, ft0
483; RV32-NEXT:    ret
484;
485; RV64-LABEL: vreduce_fadd_nxv4f64:
486; RV64:       # %bb.0:
487; RV64-NEXT:    fmv.d.x ft0, zero
488; RV64-NEXT:    fneg.d ft0, ft0
489; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
490; RV64-NEXT:    vfmv.s.f v12, ft0
491; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
492; RV64-NEXT:    vfredusum.vs v8, v8, v12
493; RV64-NEXT:    vfmv.f.s ft0, v8
494; RV64-NEXT:    fadd.d fa0, fa0, ft0
495; RV64-NEXT:    ret
496  %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
497  ret double %red
498}
499
500define double @vreduce_ord_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
501; CHECK-LABEL: vreduce_ord_fadd_nxv4f64:
502; CHECK:       # %bb.0:
503; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
504; CHECK-NEXT:    vfmv.s.f v12, fa0
505; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
506; CHECK-NEXT:    vfredosum.vs v8, v8, v12
507; CHECK-NEXT:    vfmv.f.s fa0, v8
508; CHECK-NEXT:    ret
509  %red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
510  ret double %red
511}
512
513define double @vreduce_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
514; RV32-LABEL: vreduce_fwadd_nxv4f64:
515; RV32:       # %bb.0:
516; RV32-NEXT:    fcvt.d.w ft0, zero
517; RV32-NEXT:    fneg.d ft0, ft0
518; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
519; RV32-NEXT:    vfmv.s.f v10, ft0
520; RV32-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
521; RV32-NEXT:    vfwredusum.vs v8, v8, v10
522; RV32-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
523; RV32-NEXT:    vfmv.f.s ft0, v8
524; RV32-NEXT:    fadd.d fa0, fa0, ft0
525; RV32-NEXT:    ret
526;
527; RV64-LABEL: vreduce_fwadd_nxv4f64:
528; RV64:       # %bb.0:
529; RV64-NEXT:    fmv.d.x ft0, zero
530; RV64-NEXT:    fneg.d ft0, ft0
531; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
532; RV64-NEXT:    vfmv.s.f v10, ft0
533; RV64-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
534; RV64-NEXT:    vfwredusum.vs v8, v8, v10
535; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
536; RV64-NEXT:    vfmv.f.s ft0, v8
537; RV64-NEXT:    fadd.d fa0, fa0, ft0
538; RV64-NEXT:    ret
539  %e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>
540  %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %e)
541  ret double %red
542}
543
544define double @vreduce_ord_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {
545; CHECK-LABEL: vreduce_ord_fwadd_nxv4f64:
546; CHECK:       # %bb.0:
547; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
548; CHECK-NEXT:    vfmv.s.f v10, fa0
549; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
550; CHECK-NEXT:    vfwredosum.vs v8, v8, v10
551; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
552; CHECK-NEXT:    vfmv.f.s fa0, v8
553; CHECK-NEXT:    ret
554  %e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>
555  %red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %e)
556  ret double %red
557}
558
559declare half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half>)
560
561define half @vreduce_fmin_nxv1f16(<vscale x 1 x half> %v) {
562; CHECK-LABEL: vreduce_fmin_nxv1f16:
563; CHECK:       # %bb.0:
564; CHECK-NEXT:    lui a0, %hi(.LCPI30_0)
565; CHECK-NEXT:    addi a0, a0, %lo(.LCPI30_0)
566; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
567; CHECK-NEXT:    vlse16.v v9, (a0), zero
568; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
569; CHECK-NEXT:    vfredmin.vs v8, v8, v9
570; CHECK-NEXT:    vfmv.f.s fa0, v8
571; CHECK-NEXT:    ret
572  %red = call half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
573  ret half %red
574}
575
576define half @vreduce_fmin_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
577; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans:
578; CHECK:       # %bb.0:
579; CHECK-NEXT:    lui a0, %hi(.LCPI31_0)
580; CHECK-NEXT:    addi a0, a0, %lo(.LCPI31_0)
581; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
582; CHECK-NEXT:    vlse16.v v9, (a0), zero
583; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
584; CHECK-NEXT:    vfredmin.vs v8, v8, v9
585; CHECK-NEXT:    vfmv.f.s fa0, v8
586; CHECK-NEXT:    ret
587  %red = call nnan half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
588  ret half %red
589}
590
591define half @vreduce_fmin_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
592; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans_noinfs:
593; CHECK:       # %bb.0:
594; CHECK-NEXT:    lui a0, %hi(.LCPI32_0)
595; CHECK-NEXT:    addi a0, a0, %lo(.LCPI32_0)
596; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
597; CHECK-NEXT:    vlse16.v v9, (a0), zero
598; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
599; CHECK-NEXT:    vfredmin.vs v8, v8, v9
600; CHECK-NEXT:    vfmv.f.s fa0, v8
601; CHECK-NEXT:    ret
602  %red = call nnan ninf half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
603  ret half %red
604}
605
606declare half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half>)
607
608define half @vreduce_fmin_nxv2f16(<vscale x 2 x half> %v) {
609; CHECK-LABEL: vreduce_fmin_nxv2f16:
610; CHECK:       # %bb.0:
611; CHECK-NEXT:    lui a0, %hi(.LCPI33_0)
612; CHECK-NEXT:    addi a0, a0, %lo(.LCPI33_0)
613; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
614; CHECK-NEXT:    vlse16.v v9, (a0), zero
615; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
616; CHECK-NEXT:    vfredmin.vs v8, v8, v9
617; CHECK-NEXT:    vfmv.f.s fa0, v8
618; CHECK-NEXT:    ret
619  %red = call half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half> %v)
620  ret half %red
621}
622
623declare half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half>)
624
625define half @vreduce_fmin_nxv4f16(<vscale x 4 x half> %v) {
626; CHECK-LABEL: vreduce_fmin_nxv4f16:
627; CHECK:       # %bb.0:
628; CHECK-NEXT:    lui a0, %hi(.LCPI34_0)
629; CHECK-NEXT:    addi a0, a0, %lo(.LCPI34_0)
630; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
631; CHECK-NEXT:    vlse16.v v9, (a0), zero
632; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
633; CHECK-NEXT:    vfredmin.vs v8, v8, v9
634; CHECK-NEXT:    vfmv.f.s fa0, v8
635; CHECK-NEXT:    ret
636  %red = call half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half> %v)
637  ret half %red
638}
639
640declare half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half>)
641
642define half @vreduce_fmin_nxv64f16(<vscale x 64 x half> %v) {
643; CHECK-LABEL: vreduce_fmin_nxv64f16:
644; CHECK:       # %bb.0:
645; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
646; CHECK-NEXT:    vfmin.vv v8, v8, v16
647; CHECK-NEXT:    lui a0, %hi(.LCPI35_0)
648; CHECK-NEXT:    addi a0, a0, %lo(.LCPI35_0)
649; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
650; CHECK-NEXT:    vlse16.v v16, (a0), zero
651; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
652; CHECK-NEXT:    vfredmin.vs v8, v8, v16
653; CHECK-NEXT:    vfmv.f.s fa0, v8
654; CHECK-NEXT:    ret
655  %red = call half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half> %v)
656  ret half %red
657}
658
659declare float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float>)
660
661define float @vreduce_fmin_nxv1f32(<vscale x 1 x float> %v) {
662; CHECK-LABEL: vreduce_fmin_nxv1f32:
663; CHECK:       # %bb.0:
664; CHECK-NEXT:    lui a0, %hi(.LCPI36_0)
665; CHECK-NEXT:    addi a0, a0, %lo(.LCPI36_0)
666; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
667; CHECK-NEXT:    vlse32.v v9, (a0), zero
668; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
669; CHECK-NEXT:    vfredmin.vs v8, v8, v9
670; CHECK-NEXT:    vfmv.f.s fa0, v8
671; CHECK-NEXT:    ret
672  %red = call float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
673  ret float %red
674}
675
676define float @vreduce_fmin_nxv1f32_nonans(<vscale x 1 x float> %v) {
677; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans:
678; CHECK:       # %bb.0:
679; CHECK-NEXT:    lui a0, %hi(.LCPI37_0)
680; CHECK-NEXT:    addi a0, a0, %lo(.LCPI37_0)
681; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
682; CHECK-NEXT:    vlse32.v v9, (a0), zero
683; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
684; CHECK-NEXT:    vfredmin.vs v8, v8, v9
685; CHECK-NEXT:    vfmv.f.s fa0, v8
686; CHECK-NEXT:    ret
687  %red = call nnan float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
688  ret float %red
689}
690
691define float @vreduce_fmin_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
692; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans_noinfs:
693; CHECK:       # %bb.0:
694; CHECK-NEXT:    lui a0, %hi(.LCPI38_0)
695; CHECK-NEXT:    addi a0, a0, %lo(.LCPI38_0)
696; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
697; CHECK-NEXT:    vlse32.v v9, (a0), zero
698; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
699; CHECK-NEXT:    vfredmin.vs v8, v8, v9
700; CHECK-NEXT:    vfmv.f.s fa0, v8
701; CHECK-NEXT:    ret
702  %red = call nnan ninf float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
703  ret float %red
704}
705
706declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>)
707
708define float @vreduce_fmin_nxv2f32(<vscale x 2 x float> %v) {
709; CHECK-LABEL: vreduce_fmin_nxv2f32:
710; CHECK:       # %bb.0:
711; CHECK-NEXT:    lui a0, %hi(.LCPI39_0)
712; CHECK-NEXT:    addi a0, a0, %lo(.LCPI39_0)
713; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
714; CHECK-NEXT:    vlse32.v v9, (a0), zero
715; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
716; CHECK-NEXT:    vfredmin.vs v8, v8, v9
717; CHECK-NEXT:    vfmv.f.s fa0, v8
718; CHECK-NEXT:    ret
719  %red = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %v)
720  ret float %red
721}
722
723declare float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float>)
724
725define float @vreduce_fmin_nxv4f32(<vscale x 4 x float> %v) {
726; CHECK-LABEL: vreduce_fmin_nxv4f32:
727; CHECK:       # %bb.0:
728; CHECK-NEXT:    lui a0, %hi(.LCPI40_0)
729; CHECK-NEXT:    addi a0, a0, %lo(.LCPI40_0)
730; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
731; CHECK-NEXT:    vlse32.v v10, (a0), zero
732; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
733; CHECK-NEXT:    vfredmin.vs v8, v8, v10
734; CHECK-NEXT:    vfmv.f.s fa0, v8
735; CHECK-NEXT:    ret
736  %red = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %v)
737  ret float %red
738}
739
740declare float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float>)
741
742define float @vreduce_fmin_nxv32f32(<vscale x 32 x float> %v) {
743; CHECK-LABEL: vreduce_fmin_nxv32f32:
744; CHECK:       # %bb.0:
745; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
746; CHECK-NEXT:    vfmin.vv v8, v8, v16
747; CHECK-NEXT:    lui a0, %hi(.LCPI41_0)
748; CHECK-NEXT:    addi a0, a0, %lo(.LCPI41_0)
749; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
750; CHECK-NEXT:    vlse32.v v16, (a0), zero
751; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
752; CHECK-NEXT:    vfredmin.vs v8, v8, v16
753; CHECK-NEXT:    vfmv.f.s fa0, v8
754; CHECK-NEXT:    ret
755  %red = call float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float> %v)
756  ret float %red
757}
758
759declare double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double>)
760
761define double @vreduce_fmin_nxv1f64(<vscale x 1 x double> %v) {
762; CHECK-LABEL: vreduce_fmin_nxv1f64:
763; CHECK:       # %bb.0:
764; CHECK-NEXT:    lui a0, %hi(.LCPI42_0)
765; CHECK-NEXT:    addi a0, a0, %lo(.LCPI42_0)
766; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
767; CHECK-NEXT:    vlse64.v v9, (a0), zero
768; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
769; CHECK-NEXT:    vfredmin.vs v8, v8, v9
770; CHECK-NEXT:    vfmv.f.s fa0, v8
771; CHECK-NEXT:    ret
772  %red = call double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
773  ret double %red
774}
775
776define double @vreduce_fmin_nxv1f64_nonans(<vscale x 1 x double> %v) {
777; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans:
778; CHECK:       # %bb.0:
779; CHECK-NEXT:    lui a0, %hi(.LCPI43_0)
780; CHECK-NEXT:    addi a0, a0, %lo(.LCPI43_0)
781; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
782; CHECK-NEXT:    vlse64.v v9, (a0), zero
783; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
784; CHECK-NEXT:    vfredmin.vs v8, v8, v9
785; CHECK-NEXT:    vfmv.f.s fa0, v8
786; CHECK-NEXT:    ret
787  %red = call nnan double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
788  ret double %red
789}
790
791define double @vreduce_fmin_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {
792; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans_noinfs:
793; CHECK:       # %bb.0:
794; CHECK-NEXT:    lui a0, %hi(.LCPI44_0)
795; CHECK-NEXT:    addi a0, a0, %lo(.LCPI44_0)
796; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
797; CHECK-NEXT:    vlse64.v v9, (a0), zero
798; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
799; CHECK-NEXT:    vfredmin.vs v8, v8, v9
800; CHECK-NEXT:    vfmv.f.s fa0, v8
801; CHECK-NEXT:    ret
802  %red = call nnan ninf double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
803  ret double %red
804}
805
806declare double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double>)
807
808define double @vreduce_fmin_nxv2f64(<vscale x 2 x double> %v) {
809; CHECK-LABEL: vreduce_fmin_nxv2f64:
810; CHECK:       # %bb.0:
811; CHECK-NEXT:    lui a0, %hi(.LCPI45_0)
812; CHECK-NEXT:    addi a0, a0, %lo(.LCPI45_0)
813; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
814; CHECK-NEXT:    vlse64.v v10, (a0), zero
815; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
816; CHECK-NEXT:    vfredmin.vs v8, v8, v10
817; CHECK-NEXT:    vfmv.f.s fa0, v8
818; CHECK-NEXT:    ret
819  %red = call double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double> %v)
820  ret double %red
821}
822
823declare double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double>)
824
825define double @vreduce_fmin_nxv4f64(<vscale x 4 x double> %v) {
826; CHECK-LABEL: vreduce_fmin_nxv4f64:
827; CHECK:       # %bb.0:
828; CHECK-NEXT:    lui a0, %hi(.LCPI46_0)
829; CHECK-NEXT:    addi a0, a0, %lo(.LCPI46_0)
830; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
831; CHECK-NEXT:    vlse64.v v12, (a0), zero
832; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
833; CHECK-NEXT:    vfredmin.vs v8, v8, v12
834; CHECK-NEXT:    vfmv.f.s fa0, v8
835; CHECK-NEXT:    ret
836  %red = call double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double> %v)
837  ret double %red
838}
839
840declare double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double>)
841
842define double @vreduce_fmin_nxv16f64(<vscale x 16 x double> %v) {
843; CHECK-LABEL: vreduce_fmin_nxv16f64:
844; CHECK:       # %bb.0:
845; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
846; CHECK-NEXT:    vfmin.vv v8, v8, v16
847; CHECK-NEXT:    lui a0, %hi(.LCPI47_0)
848; CHECK-NEXT:    addi a0, a0, %lo(.LCPI47_0)
849; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
850; CHECK-NEXT:    vlse64.v v16, (a0), zero
851; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
852; CHECK-NEXT:    vfredmin.vs v8, v8, v16
853; CHECK-NEXT:    vfmv.f.s fa0, v8
854; CHECK-NEXT:    ret
855  %red = call double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double> %v)
856  ret double %red
857}
858
859declare half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half>)
860
861define half @vreduce_fmax_nxv1f16(<vscale x 1 x half> %v) {
862; CHECK-LABEL: vreduce_fmax_nxv1f16:
863; CHECK:       # %bb.0:
864; CHECK-NEXT:    lui a0, %hi(.LCPI48_0)
865; CHECK-NEXT:    addi a0, a0, %lo(.LCPI48_0)
866; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
867; CHECK-NEXT:    vlse16.v v9, (a0), zero
868; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
869; CHECK-NEXT:    vfredmax.vs v8, v8, v9
870; CHECK-NEXT:    vfmv.f.s fa0, v8
871; CHECK-NEXT:    ret
872  %red = call half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
873  ret half %red
874}
875
876define half @vreduce_fmax_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
877; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans:
878; CHECK:       # %bb.0:
879; CHECK-NEXT:    lui a0, %hi(.LCPI49_0)
880; CHECK-NEXT:    addi a0, a0, %lo(.LCPI49_0)
881; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
882; CHECK-NEXT:    vlse16.v v9, (a0), zero
883; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
884; CHECK-NEXT:    vfredmax.vs v8, v8, v9
885; CHECK-NEXT:    vfmv.f.s fa0, v8
886; CHECK-NEXT:    ret
887  %red = call nnan half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
888  ret half %red
889}
890
891define half @vreduce_fmax_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
892; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans_noinfs:
893; CHECK:       # %bb.0:
894; CHECK-NEXT:    lui a0, %hi(.LCPI50_0)
895; CHECK-NEXT:    addi a0, a0, %lo(.LCPI50_0)
896; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
897; CHECK-NEXT:    vlse16.v v9, (a0), zero
898; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
899; CHECK-NEXT:    vfredmax.vs v8, v8, v9
900; CHECK-NEXT:    vfmv.f.s fa0, v8
901; CHECK-NEXT:    ret
902  %red = call nnan ninf half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
903  ret half %red
904}
905
906declare half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half>)
907
908define half @vreduce_fmax_nxv2f16(<vscale x 2 x half> %v) {
909; CHECK-LABEL: vreduce_fmax_nxv2f16:
910; CHECK:       # %bb.0:
911; CHECK-NEXT:    lui a0, %hi(.LCPI51_0)
912; CHECK-NEXT:    addi a0, a0, %lo(.LCPI51_0)
913; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
914; CHECK-NEXT:    vlse16.v v9, (a0), zero
915; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
916; CHECK-NEXT:    vfredmax.vs v8, v8, v9
917; CHECK-NEXT:    vfmv.f.s fa0, v8
918; CHECK-NEXT:    ret
919  %red = call half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half> %v)
920  ret half %red
921}
922
923declare half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half>)
924
925define half @vreduce_fmax_nxv4f16(<vscale x 4 x half> %v) {
926; CHECK-LABEL: vreduce_fmax_nxv4f16:
927; CHECK:       # %bb.0:
928; CHECK-NEXT:    lui a0, %hi(.LCPI52_0)
929; CHECK-NEXT:    addi a0, a0, %lo(.LCPI52_0)
930; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
931; CHECK-NEXT:    vlse16.v v9, (a0), zero
932; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
933; CHECK-NEXT:    vfredmax.vs v8, v8, v9
934; CHECK-NEXT:    vfmv.f.s fa0, v8
935; CHECK-NEXT:    ret
936  %red = call half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half> %v)
937  ret half %red
938}
939
940declare half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half>)
941
942define half @vreduce_fmax_nxv64f16(<vscale x 64 x half> %v) {
943; CHECK-LABEL: vreduce_fmax_nxv64f16:
944; CHECK:       # %bb.0:
945; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
946; CHECK-NEXT:    vfmax.vv v8, v8, v16
947; CHECK-NEXT:    lui a0, %hi(.LCPI53_0)
948; CHECK-NEXT:    addi a0, a0, %lo(.LCPI53_0)
949; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
950; CHECK-NEXT:    vlse16.v v16, (a0), zero
951; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
952; CHECK-NEXT:    vfredmax.vs v8, v8, v16
953; CHECK-NEXT:    vfmv.f.s fa0, v8
954; CHECK-NEXT:    ret
955  %red = call half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half> %v)
956  ret half %red
957}
958
959declare float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float>)
960
961define float @vreduce_fmax_nxv1f32(<vscale x 1 x float> %v) {
962; CHECK-LABEL: vreduce_fmax_nxv1f32:
963; CHECK:       # %bb.0:
964; CHECK-NEXT:    lui a0, %hi(.LCPI54_0)
965; CHECK-NEXT:    addi a0, a0, %lo(.LCPI54_0)
966; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
967; CHECK-NEXT:    vlse32.v v9, (a0), zero
968; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
969; CHECK-NEXT:    vfredmax.vs v8, v8, v9
970; CHECK-NEXT:    vfmv.f.s fa0, v8
971; CHECK-NEXT:    ret
972  %red = call float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
973  ret float %red
974}
975
976define float @vreduce_fmax_nxv1f32_nonans(<vscale x 1 x float> %v) {
977; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans:
978; CHECK:       # %bb.0:
979; CHECK-NEXT:    lui a0, %hi(.LCPI55_0)
980; CHECK-NEXT:    addi a0, a0, %lo(.LCPI55_0)
981; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
982; CHECK-NEXT:    vlse32.v v9, (a0), zero
983; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
984; CHECK-NEXT:    vfredmax.vs v8, v8, v9
985; CHECK-NEXT:    vfmv.f.s fa0, v8
986; CHECK-NEXT:    ret
987  %red = call nnan float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
988  ret float %red
989}
990
991define float @vreduce_fmax_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
992; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans_noinfs:
993; CHECK:       # %bb.0:
994; CHECK-NEXT:    lui a0, %hi(.LCPI56_0)
995; CHECK-NEXT:    addi a0, a0, %lo(.LCPI56_0)
996; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
997; CHECK-NEXT:    vlse32.v v9, (a0), zero
998; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
999; CHECK-NEXT:    vfredmax.vs v8, v8, v9
1000; CHECK-NEXT:    vfmv.f.s fa0, v8
1001; CHECK-NEXT:    ret
1002  %red = call nnan ninf float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
1003  ret float %red
1004}
1005
1006declare float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float>)
1007
1008define float @vreduce_fmax_nxv2f32(<vscale x 2 x float> %v) {
1009; CHECK-LABEL: vreduce_fmax_nxv2f32:
1010; CHECK:       # %bb.0:
1011; CHECK-NEXT:    lui a0, %hi(.LCPI57_0)
1012; CHECK-NEXT:    addi a0, a0, %lo(.LCPI57_0)
1013; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
1014; CHECK-NEXT:    vlse32.v v9, (a0), zero
1015; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
1016; CHECK-NEXT:    vfredmax.vs v8, v8, v9
1017; CHECK-NEXT:    vfmv.f.s fa0, v8
1018; CHECK-NEXT:    ret
1019  %red = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %v)
1020  ret float %red
1021}
1022
1023declare float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float>)
1024
1025define float @vreduce_fmax_nxv4f32(<vscale x 4 x float> %v) {
1026; CHECK-LABEL: vreduce_fmax_nxv4f32:
1027; CHECK:       # %bb.0:
1028; CHECK-NEXT:    lui a0, %hi(.LCPI58_0)
1029; CHECK-NEXT:    addi a0, a0, %lo(.LCPI58_0)
1030; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
1031; CHECK-NEXT:    vlse32.v v10, (a0), zero
1032; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
1033; CHECK-NEXT:    vfredmax.vs v8, v8, v10
1034; CHECK-NEXT:    vfmv.f.s fa0, v8
1035; CHECK-NEXT:    ret
1036  %red = call float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float> %v)
1037  ret float %red
1038}
1039
1040declare float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float>)
1041
1042define float @vreduce_fmax_nxv32f32(<vscale x 32 x float> %v) {
1043; CHECK-LABEL: vreduce_fmax_nxv32f32:
1044; CHECK:       # %bb.0:
1045; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
1046; CHECK-NEXT:    vfmax.vv v8, v8, v16
1047; CHECK-NEXT:    lui a0, %hi(.LCPI59_0)
1048; CHECK-NEXT:    addi a0, a0, %lo(.LCPI59_0)
1049; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
1050; CHECK-NEXT:    vlse32.v v16, (a0), zero
1051; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
1052; CHECK-NEXT:    vfredmax.vs v8, v8, v16
1053; CHECK-NEXT:    vfmv.f.s fa0, v8
1054; CHECK-NEXT:    ret
1055  %red = call float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float> %v)
1056  ret float %red
1057}
1058
1059declare double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double>)
1060
1061define double @vreduce_fmax_nxv1f64(<vscale x 1 x double> %v) {
1062; CHECK-LABEL: vreduce_fmax_nxv1f64:
1063; CHECK:       # %bb.0:
1064; CHECK-NEXT:    lui a0, %hi(.LCPI60_0)
1065; CHECK-NEXT:    addi a0, a0, %lo(.LCPI60_0)
1066; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
1067; CHECK-NEXT:    vlse64.v v9, (a0), zero
1068; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
1069; CHECK-NEXT:    vfredmax.vs v8, v8, v9
1070; CHECK-NEXT:    vfmv.f.s fa0, v8
1071; CHECK-NEXT:    ret
1072  %red = call double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
1073  ret double %red
1074}
1075
1076define double @vreduce_fmax_nxv1f64_nonans(<vscale x 1 x double> %v) {
1077; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans:
1078; CHECK:       # %bb.0:
1079; CHECK-NEXT:    lui a0, %hi(.LCPI61_0)
1080; CHECK-NEXT:    addi a0, a0, %lo(.LCPI61_0)
1081; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
1082; CHECK-NEXT:    vlse64.v v9, (a0), zero
1083; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
1084; CHECK-NEXT:    vfredmax.vs v8, v8, v9
1085; CHECK-NEXT:    vfmv.f.s fa0, v8
1086; CHECK-NEXT:    ret
1087  %red = call nnan double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
1088  ret double %red
1089}
1090
1091define double @vreduce_fmax_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {
1092; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans_noinfs:
1093; CHECK:       # %bb.0:
1094; CHECK-NEXT:    lui a0, %hi(.LCPI62_0)
1095; CHECK-NEXT:    addi a0, a0, %lo(.LCPI62_0)
1096; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
1097; CHECK-NEXT:    vlse64.v v9, (a0), zero
1098; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
1099; CHECK-NEXT:    vfredmax.vs v8, v8, v9
1100; CHECK-NEXT:    vfmv.f.s fa0, v8
1101; CHECK-NEXT:    ret
1102  %red = call nnan ninf double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
1103  ret double %red
1104}
1105
1106declare double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double>)
1107
1108define double @vreduce_fmax_nxv2f64(<vscale x 2 x double> %v) {
1109; CHECK-LABEL: vreduce_fmax_nxv2f64:
1110; CHECK:       # %bb.0:
1111; CHECK-NEXT:    lui a0, %hi(.LCPI63_0)
1112; CHECK-NEXT:    addi a0, a0, %lo(.LCPI63_0)
1113; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
1114; CHECK-NEXT:    vlse64.v v10, (a0), zero
1115; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
1116; CHECK-NEXT:    vfredmax.vs v8, v8, v10
1117; CHECK-NEXT:    vfmv.f.s fa0, v8
1118; CHECK-NEXT:    ret
1119  %red = call double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double> %v)
1120  ret double %red
1121}
1122
1123declare double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double>)
1124
1125define double @vreduce_fmax_nxv4f64(<vscale x 4 x double> %v) {
1126; CHECK-LABEL: vreduce_fmax_nxv4f64:
1127; CHECK:       # %bb.0:
1128; CHECK-NEXT:    lui a0, %hi(.LCPI64_0)
1129; CHECK-NEXT:    addi a0, a0, %lo(.LCPI64_0)
1130; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
1131; CHECK-NEXT:    vlse64.v v12, (a0), zero
1132; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
1133; CHECK-NEXT:    vfredmax.vs v8, v8, v12
1134; CHECK-NEXT:    vfmv.f.s fa0, v8
1135; CHECK-NEXT:    ret
1136  %red = call double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double> %v)
1137  ret double %red
1138}
1139
1140declare double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double>)
1141
1142define double @vreduce_fmax_nxv16f64(<vscale x 16 x double> %v) {
1143; CHECK-LABEL: vreduce_fmax_nxv16f64:
1144; CHECK:       # %bb.0:
1145; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1146; CHECK-NEXT:    vfmax.vv v8, v8, v16
1147; CHECK-NEXT:    lui a0, %hi(.LCPI65_0)
1148; CHECK-NEXT:    addi a0, a0, %lo(.LCPI65_0)
1149; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
1150; CHECK-NEXT:    vlse64.v v16, (a0), zero
1151; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1152; CHECK-NEXT:    vfredmax.vs v8, v8, v16
1153; CHECK-NEXT:    vfmv.f.s fa0, v8
1154; CHECK-NEXT:    ret
1155  %red = call double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double> %v)
1156  ret double %red
1157}
1158
1159define float @vreduce_nsz_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
1160; CHECK-LABEL: vreduce_nsz_fadd_nxv1f32:
1161; CHECK:       # %bb.0:
1162; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
1163; CHECK-NEXT:    vmv.s.x v9, zero
1164; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
1165; CHECK-NEXT:    vfredusum.vs v8, v8, v9
1166; CHECK-NEXT:    vfmv.f.s ft0, v8
1167; CHECK-NEXT:    fadd.s fa0, fa0, ft0
1168; CHECK-NEXT:    ret
1169  %red = call reassoc nsz float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
1170  ret float %red
1171}
1172