1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6
7define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
8; CHECK-LABEL: vnsrl_wv_nxv1i32_sext:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
11; CHECK-NEXT:    vnsrl.wv v8, v8, v9
12; CHECK-NEXT:    ret
13  %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
14  %x = lshr <vscale x 1 x i64> %va, %vc
15  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
16  ret <vscale x 1 x i32> %y
17}
18
19define <vscale x 1 x i32> @vnsrl_wx_i32_nxv1i32_sext(<vscale x 1 x i64> %va, i32 %b) {
20; CHECK-LABEL: vnsrl_wx_i32_nxv1i32_sext:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
23; CHECK-NEXT:    vnsrl.wx v8, v8, a0
24; CHECK-NEXT:    ret
25  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
26  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
27  %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
28  %x = lshr <vscale x 1 x i64> %va, %vb
29  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
30  ret <vscale x 1 x i32> %y
31}
32
33define <vscale x 1 x i32> @vnsrl_wi_i32_nxv1i32_sext(<vscale x 1 x i64> %va) {
34; CHECK-LABEL: vnsrl_wi_i32_nxv1i32_sext:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
37; CHECK-NEXT:    vnsrl.wi v8, v8, 15
38; CHECK-NEXT:    ret
39  %head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
40  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
41  %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
42  %x = lshr <vscale x 1 x i64> %va, %vb
43  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
44  ret <vscale x 1 x i32> %y
45}
46
47define <vscale x 2 x i32> @vnsrl_wv_nxv2i32_sext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
48; CHECK-LABEL: vnsrl_wv_nxv2i32_sext:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
51; CHECK-NEXT:    vnsrl.wv v11, v8, v10
52; CHECK-NEXT:    vmv.v.v v8, v11
53; CHECK-NEXT:    ret
54  %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
55  %x = lshr <vscale x 2 x i64> %va, %vc
56  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
57  ret <vscale x 2 x i32> %y
58}
59
60define <vscale x 2 x i32> @vnsrl_wx_i32_nxv2i32_sext(<vscale x 2 x i64> %va, i32 %b) {
61; CHECK-LABEL: vnsrl_wx_i32_nxv2i32_sext:
62; CHECK:       # %bb.0:
63; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
64; CHECK-NEXT:    vnsrl.wx v10, v8, a0
65; CHECK-NEXT:    vmv.v.v v8, v10
66; CHECK-NEXT:    ret
67  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
68  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
69  %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
70  %x = lshr <vscale x 2 x i64> %va, %vb
71  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
72  ret <vscale x 2 x i32> %y
73}
74
75define <vscale x 2 x i32> @vnsrl_wi_i32_nxv2i32_sext(<vscale x 2 x i64> %va) {
76; CHECK-LABEL: vnsrl_wi_i32_nxv2i32_sext:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
79; CHECK-NEXT:    vnsrl.wi v10, v8, 15
80; CHECK-NEXT:    vmv.v.v v8, v10
81; CHECK-NEXT:    ret
82  %head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
83  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
84  %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
85  %x = lshr <vscale x 2 x i64> %va, %vb
86  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
87  ret <vscale x 2 x i32> %y
88}
89
90define <vscale x 4 x i32> @vnsrl_wv_nxv4i32_sext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
91; CHECK-LABEL: vnsrl_wv_nxv4i32_sext:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
94; CHECK-NEXT:    vnsrl.wv v14, v8, v12
95; CHECK-NEXT:    vmv.v.v v8, v14
96; CHECK-NEXT:    ret
97  %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
98  %x = lshr <vscale x 4 x i64> %va, %vc
99  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
100  ret <vscale x 4 x i32> %y
101}
102
103define <vscale x 4 x i32> @vnsrl_wx_i32_nxv4i32_sext(<vscale x 4 x i64> %va, i32 %b) {
104; CHECK-LABEL: vnsrl_wx_i32_nxv4i32_sext:
105; CHECK:       # %bb.0:
106; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
107; CHECK-NEXT:    vnsrl.wx v12, v8, a0
108; CHECK-NEXT:    vmv.v.v v8, v12
109; CHECK-NEXT:    ret
110  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
111  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
112  %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
113  %x = lshr <vscale x 4 x i64> %va, %vb
114  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
115  ret <vscale x 4 x i32> %y
116}
117
118define <vscale x 4 x i32> @vnsrl_wi_i32_nxv4i32_sext(<vscale x 4 x i64> %va) {
119; CHECK-LABEL: vnsrl_wi_i32_nxv4i32_sext:
120; CHECK:       # %bb.0:
121; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
122; CHECK-NEXT:    vnsrl.wi v12, v8, 15
123; CHECK-NEXT:    vmv.v.v v8, v12
124; CHECK-NEXT:    ret
125  %head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
126  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
127  %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
128  %x = lshr <vscale x 4 x i64> %va, %vb
129  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
130  ret <vscale x 4 x i32> %y
131}
132
133define <vscale x 8 x i32> @vnsrl_wv_nxv8i32_sext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
134; CHECK-LABEL: vnsrl_wv_nxv8i32_sext:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
137; CHECK-NEXT:    vnsrl.wv v20, v8, v16
138; CHECK-NEXT:    vmv.v.v v8, v20
139; CHECK-NEXT:    ret
140  %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
141  %x = lshr <vscale x 8 x i64> %va, %vc
142  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
143  ret <vscale x 8 x i32> %y
144}
145
146define <vscale x 8 x i32> @vnsrl_wx_i32_nxv8i32_sext(<vscale x 8 x i64> %va, i32 %b) {
147; CHECK-LABEL: vnsrl_wx_i32_nxv8i32_sext:
148; CHECK:       # %bb.0:
149; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
150; CHECK-NEXT:    vnsrl.wx v16, v8, a0
151; CHECK-NEXT:    vmv.v.v v8, v16
152; CHECK-NEXT:    ret
153  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
154  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
155  %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
156  %x = lshr <vscale x 8 x i64> %va, %vb
157  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
158  ret <vscale x 8 x i32> %y
159}
160
161define <vscale x 8 x i32> @vnsrl_wi_i32_nxv8i32_sext(<vscale x 8 x i64> %va) {
162; CHECK-LABEL: vnsrl_wi_i32_nxv8i32_sext:
163; CHECK:       # %bb.0:
164; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
165; CHECK-NEXT:    vnsrl.wi v16, v8, 15
166; CHECK-NEXT:    vmv.v.v v8, v16
167; CHECK-NEXT:    ret
168  %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
169  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
170  %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
171  %x = lshr <vscale x 8 x i64> %va, %vb
172  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
173  ret <vscale x 8 x i32> %y
174}
175
176define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_zext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
177; CHECK-LABEL: vnsrl_wv_nxv1i32_zext:
178; CHECK:       # %bb.0:
179; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
180; CHECK-NEXT:    vnsrl.wv v8, v8, v9
181; CHECK-NEXT:    ret
182  %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
183  %x = lshr <vscale x 1 x i64> %va, %vc
184  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
185  ret <vscale x 1 x i32> %y
186}
187
188define <vscale x 1 x i32> @vnsrl_wx_i32_nxv1i32_zext(<vscale x 1 x i64> %va, i32 %b) {
189; CHECK-LABEL: vnsrl_wx_i32_nxv1i32_zext:
190; CHECK:       # %bb.0:
191; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
192; CHECK-NEXT:    vnsrl.wx v8, v8, a0
193; CHECK-NEXT:    ret
194  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
195  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
196  %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
197  %x = lshr <vscale x 1 x i64> %va, %vb
198  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
199  ret <vscale x 1 x i32> %y
200}
201
202define <vscale x 1 x i32> @vnsrl_wi_i32_nxv1i32_zext(<vscale x 1 x i64> %va) {
203; CHECK-LABEL: vnsrl_wi_i32_nxv1i32_zext:
204; CHECK:       # %bb.0:
205; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
206; CHECK-NEXT:    vnsrl.wi v8, v8, 15
207; CHECK-NEXT:    ret
208  %head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
209  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
210  %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
211  %x = lshr <vscale x 1 x i64> %va, %vb
212  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
213  ret <vscale x 1 x i32> %y
214}
215
216define <vscale x 2 x i32> @vnsrl_wv_nxv2i32_zext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
217; CHECK-LABEL: vnsrl_wv_nxv2i32_zext:
218; CHECK:       # %bb.0:
219; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
220; CHECK-NEXT:    vnsrl.wv v11, v8, v10
221; CHECK-NEXT:    vmv.v.v v8, v11
222; CHECK-NEXT:    ret
223  %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
224  %x = lshr <vscale x 2 x i64> %va, %vc
225  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
226  ret <vscale x 2 x i32> %y
227}
228
229define <vscale x 2 x i32> @vnsrl_wx_i32_nxv2i32_zext(<vscale x 2 x i64> %va, i32 %b) {
230; CHECK-LABEL: vnsrl_wx_i32_nxv2i32_zext:
231; CHECK:       # %bb.0:
232; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
233; CHECK-NEXT:    vnsrl.wx v10, v8, a0
234; CHECK-NEXT:    vmv.v.v v8, v10
235; CHECK-NEXT:    ret
236  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
237  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
238  %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
239  %x = lshr <vscale x 2 x i64> %va, %vb
240  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
241  ret <vscale x 2 x i32> %y
242}
243
244define <vscale x 2 x i32> @vnsrl_wi_i32_nxv2i32_zext(<vscale x 2 x i64> %va) {
245; CHECK-LABEL: vnsrl_wi_i32_nxv2i32_zext:
246; CHECK:       # %bb.0:
247; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
248; CHECK-NEXT:    vnsrl.wi v10, v8, 15
249; CHECK-NEXT:    vmv.v.v v8, v10
250; CHECK-NEXT:    ret
251  %head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
252  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
253  %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
254  %x = lshr <vscale x 2 x i64> %va, %vb
255  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
256  ret <vscale x 2 x i32> %y
257}
258
259define <vscale x 4 x i32> @vnsrl_wv_nxv4i32_zext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
260; CHECK-LABEL: vnsrl_wv_nxv4i32_zext:
261; CHECK:       # %bb.0:
262; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
263; CHECK-NEXT:    vnsrl.wv v14, v8, v12
264; CHECK-NEXT:    vmv.v.v v8, v14
265; CHECK-NEXT:    ret
266  %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
267  %x = lshr <vscale x 4 x i64> %va, %vc
268  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
269  ret <vscale x 4 x i32> %y
270}
271
272define <vscale x 4 x i32> @vnsrl_wx_i32_nxv4i32_zext(<vscale x 4 x i64> %va, i32 %b) {
273; CHECK-LABEL: vnsrl_wx_i32_nxv4i32_zext:
274; CHECK:       # %bb.0:
275; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
276; CHECK-NEXT:    vnsrl.wx v12, v8, a0
277; CHECK-NEXT:    vmv.v.v v8, v12
278; CHECK-NEXT:    ret
279  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
280  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
281  %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
282  %x = lshr <vscale x 4 x i64> %va, %vb
283  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
284  ret <vscale x 4 x i32> %y
285}
286
287define <vscale x 4 x i32> @vnsrl_wi_i32_nxv4i32_zext(<vscale x 4 x i64> %va) {
288; CHECK-LABEL: vnsrl_wi_i32_nxv4i32_zext:
289; CHECK:       # %bb.0:
290; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
291; CHECK-NEXT:    vnsrl.wi v12, v8, 15
292; CHECK-NEXT:    vmv.v.v v8, v12
293; CHECK-NEXT:    ret
294  %head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
295  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
296  %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
297  %x = lshr <vscale x 4 x i64> %va, %vb
298  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
299  ret <vscale x 4 x i32> %y
300}
301
302define <vscale x 8 x i32> @vnsrl_wv_nxv8i32_zext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
303; CHECK-LABEL: vnsrl_wv_nxv8i32_zext:
304; CHECK:       # %bb.0:
305; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
306; CHECK-NEXT:    vnsrl.wv v20, v8, v16
307; CHECK-NEXT:    vmv.v.v v8, v20
308; CHECK-NEXT:    ret
309  %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
310  %x = lshr <vscale x 8 x i64> %va, %vc
311  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
312  ret <vscale x 8 x i32> %y
313}
314
315define <vscale x 8 x i32> @vnsrl_wx_i32_nxv8i32_zext(<vscale x 8 x i64> %va, i32 %b) {
316; CHECK-LABEL: vnsrl_wx_i32_nxv8i32_zext:
317; CHECK:       # %bb.0:
318; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
319; CHECK-NEXT:    vnsrl.wx v16, v8, a0
320; CHECK-NEXT:    vmv.v.v v8, v16
321; CHECK-NEXT:    ret
322  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
323  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
324  %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
325  %x = lshr <vscale x 8 x i64> %va, %vb
326  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
327  ret <vscale x 8 x i32> %y
328}
329
330define <vscale x 8 x i32> @vnsrl_wi_i32_nxv8i32_zext(<vscale x 8 x i64> %va) {
331; CHECK-LABEL: vnsrl_wi_i32_nxv8i32_zext:
332; CHECK:       # %bb.0:
333; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
334; CHECK-NEXT:    vnsrl.wi v16, v8, 15
335; CHECK-NEXT:    vmv.v.v v8, v16
336; CHECK-NEXT:    ret
337  %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
338  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
339  %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
340  %x = lshr <vscale x 8 x i64> %va, %vb
341  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
342  ret <vscale x 8 x i32> %y
343}
344