1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
3; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
5; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
6declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(
7  <vscale x 1 x i8>,
8  <vscale x 1 x i8>,
9  <vscale x 1 x i8>,
10  iXLen);
11
12define <vscale x 1 x i8> @intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
13; CHECK-LABEL: intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8:
14; CHECK:       # %bb.0: # %entry
15; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
16; CHECK-NEXT:    vmul.vv v8, v8, v9
17; CHECK-NEXT:    ret
18entry:
19  %a = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(
20    <vscale x 1 x i8> undef,
21    <vscale x 1 x i8> %0,
22    <vscale x 1 x i8> %1,
23    iXLen %2)
24
25  ret <vscale x 1 x i8> %a
26}
27
28declare <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.nxv1i8(
29  <vscale x 1 x i8>,
30  <vscale x 1 x i8>,
31  <vscale x 1 x i8>,
32  <vscale x 1 x i1>,
33  iXLen, iXLen);
34
35define <vscale x 1 x i8> @intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
36; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8:
37; CHECK:       # %bb.0: # %entry
38; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
39; CHECK-NEXT:    vmul.vv v8, v9, v10, v0.t
40; CHECK-NEXT:    ret
41entry:
42  %a = call <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.nxv1i8(
43    <vscale x 1 x i8> %0,
44    <vscale x 1 x i8> %1,
45    <vscale x 1 x i8> %2,
46    <vscale x 1 x i1> %3,
47    iXLen %4, iXLen 1)
48
49  ret <vscale x 1 x i8> %a
50}
51
52declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8(
53  <vscale x 2 x i8>,
54  <vscale x 2 x i8>,
55  <vscale x 2 x i8>,
56  iXLen);
57
58define <vscale x 2 x i8> @intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
59; CHECK-LABEL: intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8:
60; CHECK:       # %bb.0: # %entry
61; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
62; CHECK-NEXT:    vmul.vv v8, v8, v9
63; CHECK-NEXT:    ret
64entry:
65  %a = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8(
66    <vscale x 2 x i8> undef,
67    <vscale x 2 x i8> %0,
68    <vscale x 2 x i8> %1,
69    iXLen %2)
70
71  ret <vscale x 2 x i8> %a
72}
73
74declare <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.nxv2i8(
75  <vscale x 2 x i8>,
76  <vscale x 2 x i8>,
77  <vscale x 2 x i8>,
78  <vscale x 2 x i1>,
79  iXLen, iXLen);
80
81define <vscale x 2 x i8> @intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
82; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8:
83; CHECK:       # %bb.0: # %entry
84; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu
85; CHECK-NEXT:    vmul.vv v8, v9, v10, v0.t
86; CHECK-NEXT:    ret
87entry:
88  %a = call <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.nxv2i8(
89    <vscale x 2 x i8> %0,
90    <vscale x 2 x i8> %1,
91    <vscale x 2 x i8> %2,
92    <vscale x 2 x i1> %3,
93    iXLen %4, iXLen 1)
94
95  ret <vscale x 2 x i8> %a
96}
97
98declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8(
99  <vscale x 4 x i8>,
100  <vscale x 4 x i8>,
101  <vscale x 4 x i8>,
102  iXLen);
103
104define <vscale x 4 x i8> @intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
105; CHECK-LABEL: intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8:
106; CHECK:       # %bb.0: # %entry
107; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu
108; CHECK-NEXT:    vmul.vv v8, v8, v9
109; CHECK-NEXT:    ret
110entry:
111  %a = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8(
112    <vscale x 4 x i8> undef,
113    <vscale x 4 x i8> %0,
114    <vscale x 4 x i8> %1,
115    iXLen %2)
116
117  ret <vscale x 4 x i8> %a
118}
119
120declare <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.nxv4i8(
121  <vscale x 4 x i8>,
122  <vscale x 4 x i8>,
123  <vscale x 4 x i8>,
124  <vscale x 4 x i1>,
125  iXLen, iXLen);
126
127define <vscale x 4 x i8> @intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
128; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8:
129; CHECK:       # %bb.0: # %entry
130; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu
131; CHECK-NEXT:    vmul.vv v8, v9, v10, v0.t
132; CHECK-NEXT:    ret
133entry:
134  %a = call <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.nxv4i8(
135    <vscale x 4 x i8> %0,
136    <vscale x 4 x i8> %1,
137    <vscale x 4 x i8> %2,
138    <vscale x 4 x i1> %3,
139    iXLen %4, iXLen 1)
140
141  ret <vscale x 4 x i8> %a
142}
143
144declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8(
145  <vscale x 8 x i8>,
146  <vscale x 8 x i8>,
147  <vscale x 8 x i8>,
148  iXLen);
149
150define <vscale x 8 x i8> @intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
151; CHECK-LABEL: intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8:
152; CHECK:       # %bb.0: # %entry
153; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
154; CHECK-NEXT:    vmul.vv v8, v8, v9
155; CHECK-NEXT:    ret
156entry:
157  %a = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8(
158    <vscale x 8 x i8> undef,
159    <vscale x 8 x i8> %0,
160    <vscale x 8 x i8> %1,
161    iXLen %2)
162
163  ret <vscale x 8 x i8> %a
164}
165
166declare <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.nxv8i8(
167  <vscale x 8 x i8>,
168  <vscale x 8 x i8>,
169  <vscale x 8 x i8>,
170  <vscale x 8 x i1>,
171  iXLen, iXLen);
172
173define <vscale x 8 x i8> @intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
174; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8:
175; CHECK:       # %bb.0: # %entry
176; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
177; CHECK-NEXT:    vmul.vv v8, v9, v10, v0.t
178; CHECK-NEXT:    ret
179entry:
180  %a = call <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.nxv8i8(
181    <vscale x 8 x i8> %0,
182    <vscale x 8 x i8> %1,
183    <vscale x 8 x i8> %2,
184    <vscale x 8 x i1> %3,
185    iXLen %4, iXLen 1)
186
187  ret <vscale x 8 x i8> %a
188}
189
190declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8(
191  <vscale x 16 x i8>,
192  <vscale x 16 x i8>,
193  <vscale x 16 x i8>,
194  iXLen);
195
196define <vscale x 16 x i8> @intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
197; CHECK-LABEL: intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8:
198; CHECK:       # %bb.0: # %entry
199; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu
200; CHECK-NEXT:    vmul.vv v8, v8, v10
201; CHECK-NEXT:    ret
202entry:
203  %a = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8(
204    <vscale x 16 x i8> undef,
205    <vscale x 16 x i8> %0,
206    <vscale x 16 x i8> %1,
207    iXLen %2)
208
209  ret <vscale x 16 x i8> %a
210}
211
212declare <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.nxv16i8(
213  <vscale x 16 x i8>,
214  <vscale x 16 x i8>,
215  <vscale x 16 x i8>,
216  <vscale x 16 x i1>,
217  iXLen, iXLen);
218
219define <vscale x 16 x i8> @intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
220; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8:
221; CHECK:       # %bb.0: # %entry
222; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu
223; CHECK-NEXT:    vmul.vv v8, v10, v12, v0.t
224; CHECK-NEXT:    ret
225entry:
226  %a = call <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.nxv16i8(
227    <vscale x 16 x i8> %0,
228    <vscale x 16 x i8> %1,
229    <vscale x 16 x i8> %2,
230    <vscale x 16 x i1> %3,
231    iXLen %4, iXLen 1)
232
233  ret <vscale x 16 x i8> %a
234}
235
236declare <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.nxv32i8(
237  <vscale x 32 x i8>,
238  <vscale x 32 x i8>,
239  <vscale x 32 x i8>,
240  iXLen);
241
242define <vscale x 32 x i8> @intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
243; CHECK-LABEL: intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8:
244; CHECK:       # %bb.0: # %entry
245; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu
246; CHECK-NEXT:    vmul.vv v8, v8, v12
247; CHECK-NEXT:    ret
248entry:
249  %a = call <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.nxv32i8(
250    <vscale x 32 x i8> undef,
251    <vscale x 32 x i8> %0,
252    <vscale x 32 x i8> %1,
253    iXLen %2)
254
255  ret <vscale x 32 x i8> %a
256}
257
258declare <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.nxv32i8(
259  <vscale x 32 x i8>,
260  <vscale x 32 x i8>,
261  <vscale x 32 x i8>,
262  <vscale x 32 x i1>,
263  iXLen, iXLen);
264
265define <vscale x 32 x i8> @intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
266; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8:
267; CHECK:       # %bb.0: # %entry
268; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu
269; CHECK-NEXT:    vmul.vv v8, v12, v16, v0.t
270; CHECK-NEXT:    ret
271entry:
272  %a = call <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.nxv32i8(
273    <vscale x 32 x i8> %0,
274    <vscale x 32 x i8> %1,
275    <vscale x 32 x i8> %2,
276    <vscale x 32 x i1> %3,
277    iXLen %4, iXLen 1)
278
279  ret <vscale x 32 x i8> %a
280}
281
282declare <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.nxv64i8(
283  <vscale x 64 x i8>,
284  <vscale x 64 x i8>,
285  <vscale x 64 x i8>,
286  iXLen);
287
288define <vscale x 64 x i8> @intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
289; CHECK-LABEL: intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8:
290; CHECK:       # %bb.0: # %entry
291; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, mu
292; CHECK-NEXT:    vmul.vv v8, v8, v16
293; CHECK-NEXT:    ret
294entry:
295  %a = call <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.nxv64i8(
296    <vscale x 64 x i8> undef,
297    <vscale x 64 x i8> %0,
298    <vscale x 64 x i8> %1,
299    iXLen %2)
300
301  ret <vscale x 64 x i8> %a
302}
303
304declare <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8(
305  <vscale x 64 x i8>,
306  <vscale x 64 x i8>,
307  <vscale x 64 x i8>,
308  <vscale x 64 x i1>,
309  iXLen, iXLen);
310
311define <vscale x 64 x i8> @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
312; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8:
313; CHECK:       # %bb.0: # %entry
314; CHECK-NEXT:    vl8r.v v24, (a0)
315; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu
316; CHECK-NEXT:    vmul.vv v8, v16, v24, v0.t
317; CHECK-NEXT:    ret
318entry:
319  %a = call <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8(
320    <vscale x 64 x i8> %0,
321    <vscale x 64 x i8> %1,
322    <vscale x 64 x i8> %2,
323    <vscale x 64 x i1> %3,
324    iXLen %4, iXLen 1)
325
326  ret <vscale x 64 x i8> %a
327}
328
329declare <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.nxv1i16(
330  <vscale x 1 x i16>,
331  <vscale x 1 x i16>,
332  <vscale x 1 x i16>,
333  iXLen);
334
335define <vscale x 1 x i16> @intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
336; CHECK-LABEL: intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16:
337; CHECK:       # %bb.0: # %entry
338; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
339; CHECK-NEXT:    vmul.vv v8, v8, v9
340; CHECK-NEXT:    ret
341entry:
342  %a = call <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.nxv1i16(
343    <vscale x 1 x i16> undef,
344    <vscale x 1 x i16> %0,
345    <vscale x 1 x i16> %1,
346    iXLen %2)
347
348  ret <vscale x 1 x i16> %a
349}
350
351declare <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.nxv1i16(
352  <vscale x 1 x i16>,
353  <vscale x 1 x i16>,
354  <vscale x 1 x i16>,
355  <vscale x 1 x i1>,
356  iXLen, iXLen);
357
358define <vscale x 1 x i16> @intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
359; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16:
360; CHECK:       # %bb.0: # %entry
361; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
362; CHECK-NEXT:    vmul.vv v8, v9, v10, v0.t
363; CHECK-NEXT:    ret
364entry:
365  %a = call <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.nxv1i16(
366    <vscale x 1 x i16> %0,
367    <vscale x 1 x i16> %1,
368    <vscale x 1 x i16> %2,
369    <vscale x 1 x i1> %3,
370    iXLen %4, iXLen 1)
371
372  ret <vscale x 1 x i16> %a
373}
374
375declare <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.nxv2i16(
376  <vscale x 2 x i16>,
377  <vscale x 2 x i16>,
378  <vscale x 2 x i16>,
379  iXLen);
380
381define <vscale x 2 x i16> @intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
382; CHECK-LABEL: intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16:
383; CHECK:       # %bb.0: # %entry
384; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
385; CHECK-NEXT:    vmul.vv v8, v8, v9
386; CHECK-NEXT:    ret
387entry:
388  %a = call <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.nxv2i16(
389    <vscale x 2 x i16> undef,
390    <vscale x 2 x i16> %0,
391    <vscale x 2 x i16> %1,
392    iXLen %2)
393
394  ret <vscale x 2 x i16> %a
395}
396
397declare <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.nxv2i16(
398  <vscale x 2 x i16>,
399  <vscale x 2 x i16>,
400  <vscale x 2 x i16>,
401  <vscale x 2 x i1>,
402  iXLen, iXLen);
403
404define <vscale x 2 x i16> @intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
405; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16:
406; CHECK:       # %bb.0: # %entry
407; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
408; CHECK-NEXT:    vmul.vv v8, v9, v10, v0.t
409; CHECK-NEXT:    ret
410entry:
411  %a = call <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.nxv2i16(
412    <vscale x 2 x i16> %0,
413    <vscale x 2 x i16> %1,
414    <vscale x 2 x i16> %2,
415    <vscale x 2 x i1> %3,
416    iXLen %4, iXLen 1)
417
418  ret <vscale x 2 x i16> %a
419}
420
421declare <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.nxv4i16(
422  <vscale x 4 x i16>,
423  <vscale x 4 x i16>,
424  <vscale x 4 x i16>,
425  iXLen);
426
427define <vscale x 4 x i16> @intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
428; CHECK-LABEL: intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16:
429; CHECK:       # %bb.0: # %entry
430; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
431; CHECK-NEXT:    vmul.vv v8, v8, v9
432; CHECK-NEXT:    ret
433entry:
434  %a = call <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.nxv4i16(
435    <vscale x 4 x i16> undef,
436    <vscale x 4 x i16> %0,
437    <vscale x 4 x i16> %1,
438    iXLen %2)
439
440  ret <vscale x 4 x i16> %a
441}
442
443declare <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.nxv4i16(
444  <vscale x 4 x i16>,
445  <vscale x 4 x i16>,
446  <vscale x 4 x i16>,
447  <vscale x 4 x i1>,
448  iXLen, iXLen);
449
450define <vscale x 4 x i16> @intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
451; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16:
452; CHECK:       # %bb.0: # %entry
453; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
454; CHECK-NEXT:    vmul.vv v8, v9, v10, v0.t
455; CHECK-NEXT:    ret
456entry:
457  %a = call <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.nxv4i16(
458    <vscale x 4 x i16> %0,
459    <vscale x 4 x i16> %1,
460    <vscale x 4 x i16> %2,
461    <vscale x 4 x i1> %3,
462    iXLen %4, iXLen 1)
463
464  ret <vscale x 4 x i16> %a
465}
466
467declare <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.nxv8i16(
468  <vscale x 8 x i16>,
469  <vscale x 8 x i16>,
470  <vscale x 8 x i16>,
471  iXLen);
472
473define <vscale x 8 x i16> @intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
474; CHECK-LABEL: intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16:
475; CHECK:       # %bb.0: # %entry
476; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
477; CHECK-NEXT:    vmul.vv v8, v8, v10
478; CHECK-NEXT:    ret
479entry:
480  %a = call <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.nxv8i16(
481    <vscale x 8 x i16> undef,
482    <vscale x 8 x i16> %0,
483    <vscale x 8 x i16> %1,
484    iXLen %2)
485
486  ret <vscale x 8 x i16> %a
487}
488
489declare <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.nxv8i16(
490  <vscale x 8 x i16>,
491  <vscale x 8 x i16>,
492  <vscale x 8 x i16>,
493  <vscale x 8 x i1>,
494  iXLen, iXLen);
495
496define <vscale x 8 x i16> @intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
497; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16:
498; CHECK:       # %bb.0: # %entry
499; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
500; CHECK-NEXT:    vmul.vv v8, v10, v12, v0.t
501; CHECK-NEXT:    ret
502entry:
503  %a = call <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.nxv8i16(
504    <vscale x 8 x i16> %0,
505    <vscale x 8 x i16> %1,
506    <vscale x 8 x i16> %2,
507    <vscale x 8 x i1> %3,
508    iXLen %4, iXLen 1)
509
510  ret <vscale x 8 x i16> %a
511}
512
513declare <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.nxv16i16(
514  <vscale x 16 x i16>,
515  <vscale x 16 x i16>,
516  <vscale x 16 x i16>,
517  iXLen);
518
519define <vscale x 16 x i16> @intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
520; CHECK-LABEL: intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16:
521; CHECK:       # %bb.0: # %entry
522; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu
523; CHECK-NEXT:    vmul.vv v8, v8, v12
524; CHECK-NEXT:    ret
525entry:
526  %a = call <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.nxv16i16(
527    <vscale x 16 x i16> undef,
528    <vscale x 16 x i16> %0,
529    <vscale x 16 x i16> %1,
530    iXLen %2)
531
532  ret <vscale x 16 x i16> %a
533}
534
535declare <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.nxv16i16(
536  <vscale x 16 x i16>,
537  <vscale x 16 x i16>,
538  <vscale x 16 x i16>,
539  <vscale x 16 x i1>,
540  iXLen, iXLen);
541
542define <vscale x 16 x i16> @intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
543; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16:
544; CHECK:       # %bb.0: # %entry
545; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu
546; CHECK-NEXT:    vmul.vv v8, v12, v16, v0.t
547; CHECK-NEXT:    ret
548entry:
549  %a = call <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.nxv16i16(
550    <vscale x 16 x i16> %0,
551    <vscale x 16 x i16> %1,
552    <vscale x 16 x i16> %2,
553    <vscale x 16 x i1> %3,
554    iXLen %4, iXLen 1)
555
556  ret <vscale x 16 x i16> %a
557}
558
559declare <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.nxv32i16(
560  <vscale x 32 x i16>,
561  <vscale x 32 x i16>,
562  <vscale x 32 x i16>,
563  iXLen);
564
565define <vscale x 32 x i16> @intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
566; CHECK-LABEL: intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16:
567; CHECK:       # %bb.0: # %entry
568; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, mu
569; CHECK-NEXT:    vmul.vv v8, v8, v16
570; CHECK-NEXT:    ret
571entry:
572  %a = call <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.nxv32i16(
573    <vscale x 32 x i16> undef,
574    <vscale x 32 x i16> %0,
575    <vscale x 32 x i16> %1,
576    iXLen %2)
577
578  ret <vscale x 32 x i16> %a
579}
580
581declare <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16(
582  <vscale x 32 x i16>,
583  <vscale x 32 x i16>,
584  <vscale x 32 x i16>,
585  <vscale x 32 x i1>,
586  iXLen, iXLen);
587
588define <vscale x 32 x i16> @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
589; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16:
590; CHECK:       # %bb.0: # %entry
591; CHECK-NEXT:    vl8re16.v v24, (a0)
592; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
593; CHECK-NEXT:    vmul.vv v8, v16, v24, v0.t
594; CHECK-NEXT:    ret
595entry:
596  %a = call <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16(
597    <vscale x 32 x i16> %0,
598    <vscale x 32 x i16> %1,
599    <vscale x 32 x i16> %2,
600    <vscale x 32 x i1> %3,
601    iXLen %4, iXLen 1)
602
603  ret <vscale x 32 x i16> %a
604}
605
606declare <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.nxv1i32(
607  <vscale x 1 x i32>,
608  <vscale x 1 x i32>,
609  <vscale x 1 x i32>,
610  iXLen);
611
612define <vscale x 1 x i32> @intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
613; CHECK-LABEL: intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32:
614; CHECK:       # %bb.0: # %entry
615; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
616; CHECK-NEXT:    vmul.vv v8, v8, v9
617; CHECK-NEXT:    ret
618entry:
619  %a = call <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.nxv1i32(
620    <vscale x 1 x i32> undef,
621    <vscale x 1 x i32> %0,
622    <vscale x 1 x i32> %1,
623    iXLen %2)
624
625  ret <vscale x 1 x i32> %a
626}
627
628declare <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.nxv1i32(
629  <vscale x 1 x i32>,
630  <vscale x 1 x i32>,
631  <vscale x 1 x i32>,
632  <vscale x 1 x i1>,
633  iXLen, iXLen);
634
635define <vscale x 1 x i32> @intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
636; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32:
637; CHECK:       # %bb.0: # %entry
638; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
639; CHECK-NEXT:    vmul.vv v8, v9, v10, v0.t
640; CHECK-NEXT:    ret
641entry:
642  %a = call <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.nxv1i32(
643    <vscale x 1 x i32> %0,
644    <vscale x 1 x i32> %1,
645    <vscale x 1 x i32> %2,
646    <vscale x 1 x i1> %3,
647    iXLen %4, iXLen 1)
648
649  ret <vscale x 1 x i32> %a
650}
651
652declare <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.nxv2i32(
653  <vscale x 2 x i32>,
654  <vscale x 2 x i32>,
655  <vscale x 2 x i32>,
656  iXLen);
657
658define <vscale x 2 x i32> @intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
659; CHECK-LABEL: intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32:
660; CHECK:       # %bb.0: # %entry
661; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
662; CHECK-NEXT:    vmul.vv v8, v8, v9
663; CHECK-NEXT:    ret
664entry:
665  %a = call <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.nxv2i32(
666    <vscale x 2 x i32> undef,
667    <vscale x 2 x i32> %0,
668    <vscale x 2 x i32> %1,
669    iXLen %2)
670
671  ret <vscale x 2 x i32> %a
672}
673
674declare <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.nxv2i32(
675  <vscale x 2 x i32>,
676  <vscale x 2 x i32>,
677  <vscale x 2 x i32>,
678  <vscale x 2 x i1>,
679  iXLen, iXLen);
680
681define <vscale x 2 x i32> @intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
682; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32:
683; CHECK:       # %bb.0: # %entry
684; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
685; CHECK-NEXT:    vmul.vv v8, v9, v10, v0.t
686; CHECK-NEXT:    ret
687entry:
688  %a = call <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.nxv2i32(
689    <vscale x 2 x i32> %0,
690    <vscale x 2 x i32> %1,
691    <vscale x 2 x i32> %2,
692    <vscale x 2 x i1> %3,
693    iXLen %4, iXLen 1)
694
695  ret <vscale x 2 x i32> %a
696}
697
698declare <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(
699  <vscale x 4 x i32>,
700  <vscale x 4 x i32>,
701  <vscale x 4 x i32>,
702  iXLen);
703
704define <vscale x 4 x i32> @intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
705; CHECK-LABEL: intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32:
706; CHECK:       # %bb.0: # %entry
707; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
708; CHECK-NEXT:    vmul.vv v8, v8, v10
709; CHECK-NEXT:    ret
710entry:
711  %a = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(
712    <vscale x 4 x i32> undef,
713    <vscale x 4 x i32> %0,
714    <vscale x 4 x i32> %1,
715    iXLen %2)
716
717  ret <vscale x 4 x i32> %a
718}
719
720declare <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.nxv4i32(
721  <vscale x 4 x i32>,
722  <vscale x 4 x i32>,
723  <vscale x 4 x i32>,
724  <vscale x 4 x i1>,
725  iXLen, iXLen);
726
727define <vscale x 4 x i32> @intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
728; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32:
729; CHECK:       # %bb.0: # %entry
730; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
731; CHECK-NEXT:    vmul.vv v8, v10, v12, v0.t
732; CHECK-NEXT:    ret
733entry:
734  %a = call <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.nxv4i32(
735    <vscale x 4 x i32> %0,
736    <vscale x 4 x i32> %1,
737    <vscale x 4 x i32> %2,
738    <vscale x 4 x i1> %3,
739    iXLen %4, iXLen 1)
740
741  ret <vscale x 4 x i32> %a
742}
743
744declare <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.nxv8i32(
745  <vscale x 8 x i32>,
746  <vscale x 8 x i32>,
747  <vscale x 8 x i32>,
748  iXLen);
749
750define <vscale x 8 x i32> @intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
751; CHECK-LABEL: intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32:
752; CHECK:       # %bb.0: # %entry
753; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
754; CHECK-NEXT:    vmul.vv v8, v8, v12
755; CHECK-NEXT:    ret
756entry:
757  %a = call <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.nxv8i32(
758    <vscale x 8 x i32> undef,
759    <vscale x 8 x i32> %0,
760    <vscale x 8 x i32> %1,
761    iXLen %2)
762
763  ret <vscale x 8 x i32> %a
764}
765
766declare <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.nxv8i32(
767  <vscale x 8 x i32>,
768  <vscale x 8 x i32>,
769  <vscale x 8 x i32>,
770  <vscale x 8 x i1>,
771  iXLen, iXLen);
772
773define <vscale x 8 x i32> @intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
774; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32:
775; CHECK:       # %bb.0: # %entry
776; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
777; CHECK-NEXT:    vmul.vv v8, v12, v16, v0.t
778; CHECK-NEXT:    ret
779entry:
780  %a = call <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.nxv8i32(
781    <vscale x 8 x i32> %0,
782    <vscale x 8 x i32> %1,
783    <vscale x 8 x i32> %2,
784    <vscale x 8 x i1> %3,
785    iXLen %4, iXLen 1)
786
787  ret <vscale x 8 x i32> %a
788}
789
790declare <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.nxv16i32(
791  <vscale x 16 x i32>,
792  <vscale x 16 x i32>,
793  <vscale x 16 x i32>,
794  iXLen);
795
796define <vscale x 16 x i32> @intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
797; CHECK-LABEL: intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32:
798; CHECK:       # %bb.0: # %entry
799; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, mu
800; CHECK-NEXT:    vmul.vv v8, v8, v16
801; CHECK-NEXT:    ret
802entry:
803  %a = call <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.nxv16i32(
804    <vscale x 16 x i32> undef,
805    <vscale x 16 x i32> %0,
806    <vscale x 16 x i32> %1,
807    iXLen %2)
808
809  ret <vscale x 16 x i32> %a
810}
811
812declare <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32(
813  <vscale x 16 x i32>,
814  <vscale x 16 x i32>,
815  <vscale x 16 x i32>,
816  <vscale x 16 x i1>,
817  iXLen, iXLen);
818
819define <vscale x 16 x i32> @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
820; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32:
821; CHECK:       # %bb.0: # %entry
822; CHECK-NEXT:    vl8re32.v v24, (a0)
823; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu
824; CHECK-NEXT:    vmul.vv v8, v16, v24, v0.t
825; CHECK-NEXT:    ret
826entry:
827  %a = call <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32(
828    <vscale x 16 x i32> %0,
829    <vscale x 16 x i32> %1,
830    <vscale x 16 x i32> %2,
831    <vscale x 16 x i1> %3,
832    iXLen %4, iXLen 1)
833
834  ret <vscale x 16 x i32> %a
835}
836
837declare <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.nxv1i64(
838  <vscale x 1 x i64>,
839  <vscale x 1 x i64>,
840  <vscale x 1 x i64>,
841  iXLen);
842
843define <vscale x 1 x i64> @intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
844; CHECK-LABEL: intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64:
845; CHECK:       # %bb.0: # %entry
846; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
847; CHECK-NEXT:    vmul.vv v8, v8, v9
848; CHECK-NEXT:    ret
849entry:
850  %a = call <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.nxv1i64(
851    <vscale x 1 x i64> undef,
852    <vscale x 1 x i64> %0,
853    <vscale x 1 x i64> %1,
854    iXLen %2)
855
856  ret <vscale x 1 x i64> %a
857}
858
859declare <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.nxv1i64(
860  <vscale x 1 x i64>,
861  <vscale x 1 x i64>,
862  <vscale x 1 x i64>,
863  <vscale x 1 x i1>,
864  iXLen, iXLen);
865
866define <vscale x 1 x i64> @intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
867; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64:
868; CHECK:       # %bb.0: # %entry
869; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
870; CHECK-NEXT:    vmul.vv v8, v9, v10, v0.t
871; CHECK-NEXT:    ret
872entry:
873  %a = call <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.nxv1i64(
874    <vscale x 1 x i64> %0,
875    <vscale x 1 x i64> %1,
876    <vscale x 1 x i64> %2,
877    <vscale x 1 x i1> %3,
878    iXLen %4, iXLen 1)
879
880  ret <vscale x 1 x i64> %a
881}
882
883declare <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.nxv2i64(
884  <vscale x 2 x i64>,
885  <vscale x 2 x i64>,
886  <vscale x 2 x i64>,
887  iXLen);
888
889define <vscale x 2 x i64> @intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
890; CHECK-LABEL: intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64:
891; CHECK:       # %bb.0: # %entry
892; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
893; CHECK-NEXT:    vmul.vv v8, v8, v10
894; CHECK-NEXT:    ret
895entry:
896  %a = call <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.nxv2i64(
897    <vscale x 2 x i64> undef,
898    <vscale x 2 x i64> %0,
899    <vscale x 2 x i64> %1,
900    iXLen %2)
901
902  ret <vscale x 2 x i64> %a
903}
904
905declare <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.nxv2i64(
906  <vscale x 2 x i64>,
907  <vscale x 2 x i64>,
908  <vscale x 2 x i64>,
909  <vscale x 2 x i1>,
910  iXLen, iXLen);
911
912define <vscale x 2 x i64> @intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
913; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64:
914; CHECK:       # %bb.0: # %entry
915; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
916; CHECK-NEXT:    vmul.vv v8, v10, v12, v0.t
917; CHECK-NEXT:    ret
918entry:
919  %a = call <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.nxv2i64(
920    <vscale x 2 x i64> %0,
921    <vscale x 2 x i64> %1,
922    <vscale x 2 x i64> %2,
923    <vscale x 2 x i1> %3,
924    iXLen %4, iXLen 1)
925
926  ret <vscale x 2 x i64> %a
927}
928
929declare <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.nxv4i64(
930  <vscale x 4 x i64>,
931  <vscale x 4 x i64>,
932  <vscale x 4 x i64>,
933  iXLen);
934
935define <vscale x 4 x i64> @intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
936; CHECK-LABEL: intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64:
937; CHECK:       # %bb.0: # %entry
938; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
939; CHECK-NEXT:    vmul.vv v8, v8, v12
940; CHECK-NEXT:    ret
941entry:
942  %a = call <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.nxv4i64(
943    <vscale x 4 x i64> undef,
944    <vscale x 4 x i64> %0,
945    <vscale x 4 x i64> %1,
946    iXLen %2)
947
948  ret <vscale x 4 x i64> %a
949}
950
951declare <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.nxv4i64(
952  <vscale x 4 x i64>,
953  <vscale x 4 x i64>,
954  <vscale x 4 x i64>,
955  <vscale x 4 x i1>,
956  iXLen, iXLen);
957
958define <vscale x 4 x i64> @intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
959; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64:
960; CHECK:       # %bb.0: # %entry
961; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
962; CHECK-NEXT:    vmul.vv v8, v12, v16, v0.t
963; CHECK-NEXT:    ret
964entry:
965  %a = call <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.nxv4i64(
966    <vscale x 4 x i64> %0,
967    <vscale x 4 x i64> %1,
968    <vscale x 4 x i64> %2,
969    <vscale x 4 x i1> %3,
970    iXLen %4, iXLen 1)
971
972  ret <vscale x 4 x i64> %a
973}
974
975declare <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.nxv8i64(
976  <vscale x 8 x i64>,
977  <vscale x 8 x i64>,
978  <vscale x 8 x i64>,
979  iXLen);
980
981define <vscale x 8 x i64> @intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
982; CHECK-LABEL: intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64:
983; CHECK:       # %bb.0: # %entry
984; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
985; CHECK-NEXT:    vmul.vv v8, v8, v16
986; CHECK-NEXT:    ret
987entry:
988  %a = call <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.nxv8i64(
989    <vscale x 8 x i64> undef,
990    <vscale x 8 x i64> %0,
991    <vscale x 8 x i64> %1,
992    iXLen %2)
993
994  ret <vscale x 8 x i64> %a
995}
996
997declare <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.nxv8i64(
998  <vscale x 8 x i64>,
999  <vscale x 8 x i64>,
1000  <vscale x 8 x i64>,
1001  <vscale x 8 x i1>,
1002  iXLen, iXLen);
1003
1004define <vscale x 8 x i64> @intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
1005; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64:
1006; CHECK:       # %bb.0: # %entry
1007; CHECK-NEXT:    vl8re64.v v24, (a0)
1008; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
1009; CHECK-NEXT:    vmul.vv v8, v16, v24, v0.t
1010; CHECK-NEXT:    ret
1011entry:
1012  %a = call <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.nxv8i64(
1013    <vscale x 8 x i64> %0,
1014    <vscale x 8 x i64> %1,
1015    <vscale x 8 x i64> %2,
1016    <vscale x 8 x i1> %3,
1017    iXLen %4, iXLen 1)
1018
1019  ret <vscale x 8 x i64> %a
1020}
1021
1022declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8(
1023  <vscale x 1 x i8>,
1024  <vscale x 1 x i8>,
1025  i8,
1026  iXLen);
1027
1028define <vscale x 1 x i8> @intrinsic_vmul_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
1029; CHECK-LABEL: intrinsic_vmul_vx_nxv1i8_nxv1i8_i8:
1030; CHECK:       # %bb.0: # %entry
1031; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
1032; CHECK-NEXT:    vmul.vx v8, v8, a0
1033; CHECK-NEXT:    ret
1034entry:
1035  %a = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8(
1036    <vscale x 1 x i8> undef,
1037    <vscale x 1 x i8> %0,
1038    i8 %1,
1039    iXLen %2)
1040
1041  ret <vscale x 1 x i8> %a
1042}
1043
1044declare <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.i8(
1045  <vscale x 1 x i8>,
1046  <vscale x 1 x i8>,
1047  i8,
1048  <vscale x 1 x i1>,
1049  iXLen, iXLen);
1050
1051define <vscale x 1 x i8> @intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
1052; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8:
1053; CHECK:       # %bb.0: # %entry
1054; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
1055; CHECK-NEXT:    vmul.vx v8, v9, a0, v0.t
1056; CHECK-NEXT:    ret
1057entry:
1058  %a = call <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.i8(
1059    <vscale x 1 x i8> %0,
1060    <vscale x 1 x i8> %1,
1061    i8 %2,
1062    <vscale x 1 x i1> %3,
1063    iXLen %4, iXLen 1)
1064
1065  ret <vscale x 1 x i8> %a
1066}
1067
1068declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8(
1069  <vscale x 2 x i8>,
1070  <vscale x 2 x i8>,
1071  i8,
1072  iXLen);
1073
1074define <vscale x 2 x i8> @intrinsic_vmul_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
1075; CHECK-LABEL: intrinsic_vmul_vx_nxv2i8_nxv2i8_i8:
1076; CHECK:       # %bb.0: # %entry
1077; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
1078; CHECK-NEXT:    vmul.vx v8, v8, a0
1079; CHECK-NEXT:    ret
1080entry:
1081  %a = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8(
1082    <vscale x 2 x i8> undef,
1083    <vscale x 2 x i8> %0,
1084    i8 %1,
1085    iXLen %2)
1086
1087  ret <vscale x 2 x i8> %a
1088}
1089
1090declare <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.i8(
1091  <vscale x 2 x i8>,
1092  <vscale x 2 x i8>,
1093  i8,
1094  <vscale x 2 x i1>,
1095  iXLen, iXLen);
1096
1097define <vscale x 2 x i8> @intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
1098; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8:
1099; CHECK:       # %bb.0: # %entry
1100; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
1101; CHECK-NEXT:    vmul.vx v8, v9, a0, v0.t
1102; CHECK-NEXT:    ret
1103entry:
1104  %a = call <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.i8(
1105    <vscale x 2 x i8> %0,
1106    <vscale x 2 x i8> %1,
1107    i8 %2,
1108    <vscale x 2 x i1> %3,
1109    iXLen %4, iXLen 1)
1110
1111  ret <vscale x 2 x i8> %a
1112}
1113
1114declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8(
1115  <vscale x 4 x i8>,
1116  <vscale x 4 x i8>,
1117  i8,
1118  iXLen);
1119
1120define <vscale x 4 x i8> @intrinsic_vmul_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
1121; CHECK-LABEL: intrinsic_vmul_vx_nxv4i8_nxv4i8_i8:
1122; CHECK:       # %bb.0: # %entry
1123; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
1124; CHECK-NEXT:    vmul.vx v8, v8, a0
1125; CHECK-NEXT:    ret
1126entry:
1127  %a = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8(
1128    <vscale x 4 x i8> undef,
1129    <vscale x 4 x i8> %0,
1130    i8 %1,
1131    iXLen %2)
1132
1133  ret <vscale x 4 x i8> %a
1134}
1135
1136declare <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.i8(
1137  <vscale x 4 x i8>,
1138  <vscale x 4 x i8>,
1139  i8,
1140  <vscale x 4 x i1>,
1141  iXLen, iXLen);
1142
1143define <vscale x 4 x i8> @intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
1144; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8:
1145; CHECK:       # %bb.0: # %entry
1146; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu
1147; CHECK-NEXT:    vmul.vx v8, v9, a0, v0.t
1148; CHECK-NEXT:    ret
1149entry:
1150  %a = call <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.i8(
1151    <vscale x 4 x i8> %0,
1152    <vscale x 4 x i8> %1,
1153    i8 %2,
1154    <vscale x 4 x i1> %3,
1155    iXLen %4, iXLen 1)
1156
1157  ret <vscale x 4 x i8> %a
1158}
1159
1160declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8(
1161  <vscale x 8 x i8>,
1162  <vscale x 8 x i8>,
1163  i8,
1164  iXLen);
1165
1166define <vscale x 8 x i8> @intrinsic_vmul_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
1167; CHECK-LABEL: intrinsic_vmul_vx_nxv8i8_nxv8i8_i8:
1168; CHECK:       # %bb.0: # %entry
1169; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
1170; CHECK-NEXT:    vmul.vx v8, v8, a0
1171; CHECK-NEXT:    ret
1172entry:
1173  %a = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8(
1174    <vscale x 8 x i8> undef,
1175    <vscale x 8 x i8> %0,
1176    i8 %1,
1177    iXLen %2)
1178
1179  ret <vscale x 8 x i8> %a
1180}
1181
1182declare <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.i8(
1183  <vscale x 8 x i8>,
1184  <vscale x 8 x i8>,
1185  i8,
1186  <vscale x 8 x i1>,
1187  iXLen, iXLen);
1188
1189define <vscale x 8 x i8> @intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
1190; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8:
1191; CHECK:       # %bb.0: # %entry
1192; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
1193; CHECK-NEXT:    vmul.vx v8, v9, a0, v0.t
1194; CHECK-NEXT:    ret
1195entry:
1196  %a = call <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.i8(
1197    <vscale x 8 x i8> %0,
1198    <vscale x 8 x i8> %1,
1199    i8 %2,
1200    <vscale x 8 x i1> %3,
1201    iXLen %4, iXLen 1)
1202
1203  ret <vscale x 8 x i8> %a
1204}
1205
1206declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8(
1207  <vscale x 16 x i8>,
1208  <vscale x 16 x i8>,
1209  i8,
1210  iXLen);
1211
1212define <vscale x 16 x i8> @intrinsic_vmul_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
1213; CHECK-LABEL: intrinsic_vmul_vx_nxv16i8_nxv16i8_i8:
1214; CHECK:       # %bb.0: # %entry
1215; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
1216; CHECK-NEXT:    vmul.vx v8, v8, a0
1217; CHECK-NEXT:    ret
1218entry:
1219  %a = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8(
1220    <vscale x 16 x i8> undef,
1221    <vscale x 16 x i8> %0,
1222    i8 %1,
1223    iXLen %2)
1224
1225  ret <vscale x 16 x i8> %a
1226}
1227
1228declare <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.i8(
1229  <vscale x 16 x i8>,
1230  <vscale x 16 x i8>,
1231  i8,
1232  <vscale x 16 x i1>,
1233  iXLen, iXLen);
1234
1235define <vscale x 16 x i8> @intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
1236; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8:
1237; CHECK:       # %bb.0: # %entry
1238; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu
1239; CHECK-NEXT:    vmul.vx v8, v10, a0, v0.t
1240; CHECK-NEXT:    ret
1241entry:
1242  %a = call <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.i8(
1243    <vscale x 16 x i8> %0,
1244    <vscale x 16 x i8> %1,
1245    i8 %2,
1246    <vscale x 16 x i1> %3,
1247    iXLen %4, iXLen 1)
1248
1249  ret <vscale x 16 x i8> %a
1250}
1251
1252declare <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.i8(
1253  <vscale x 32 x i8>,
1254  <vscale x 32 x i8>,
1255  i8,
1256  iXLen);
1257
1258define <vscale x 32 x i8> @intrinsic_vmul_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
1259; CHECK-LABEL: intrinsic_vmul_vx_nxv32i8_nxv32i8_i8:
1260; CHECK:       # %bb.0: # %entry
1261; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
1262; CHECK-NEXT:    vmul.vx v8, v8, a0
1263; CHECK-NEXT:    ret
1264entry:
1265  %a = call <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.i8(
1266    <vscale x 32 x i8> undef,
1267    <vscale x 32 x i8> %0,
1268    i8 %1,
1269    iXLen %2)
1270
1271  ret <vscale x 32 x i8> %a
1272}
1273
1274declare <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.i8(
1275  <vscale x 32 x i8>,
1276  <vscale x 32 x i8>,
1277  i8,
1278  <vscale x 32 x i1>,
1279  iXLen, iXLen);
1280
1281define <vscale x 32 x i8> @intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
1282; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8:
1283; CHECK:       # %bb.0: # %entry
1284; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu
1285; CHECK-NEXT:    vmul.vx v8, v12, a0, v0.t
1286; CHECK-NEXT:    ret
1287entry:
1288  %a = call <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.i8(
1289    <vscale x 32 x i8> %0,
1290    <vscale x 32 x i8> %1,
1291    i8 %2,
1292    <vscale x 32 x i1> %3,
1293    iXLen %4, iXLen 1)
1294
1295  ret <vscale x 32 x i8> %a
1296}
1297
1298declare <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.i8(
1299  <vscale x 64 x i8>,
1300  <vscale x 64 x i8>,
1301  i8,
1302  iXLen);
1303
1304define <vscale x 64 x i8> @intrinsic_vmul_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
1305; CHECK-LABEL: intrinsic_vmul_vx_nxv64i8_nxv64i8_i8:
1306; CHECK:       # %bb.0: # %entry
1307; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu
1308; CHECK-NEXT:    vmul.vx v8, v8, a0
1309; CHECK-NEXT:    ret
1310entry:
1311  %a = call <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.i8(
1312    <vscale x 64 x i8> undef,
1313    <vscale x 64 x i8> %0,
1314    i8 %1,
1315    iXLen %2)
1316
1317  ret <vscale x 64 x i8> %a
1318}
1319
1320declare <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.i8(
1321  <vscale x 64 x i8>,
1322  <vscale x 64 x i8>,
1323  i8,
1324  <vscale x 64 x i1>,
1325  iXLen, iXLen);
1326
1327define <vscale x 64 x i8> @intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
1328; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8:
1329; CHECK:       # %bb.0: # %entry
1330; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu
1331; CHECK-NEXT:    vmul.vx v8, v16, a0, v0.t
1332; CHECK-NEXT:    ret
1333entry:
1334  %a = call <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.i8(
1335    <vscale x 64 x i8> %0,
1336    <vscale x 64 x i8> %1,
1337    i8 %2,
1338    <vscale x 64 x i1> %3,
1339    iXLen %4, iXLen 1)
1340
1341  ret <vscale x 64 x i8> %a
1342}
1343
1344declare <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.i16(
1345  <vscale x 1 x i16>,
1346  <vscale x 1 x i16>,
1347  i16,
1348  iXLen);
1349
1350define <vscale x 1 x i16> @intrinsic_vmul_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
1351; CHECK-LABEL: intrinsic_vmul_vx_nxv1i16_nxv1i16_i16:
1352; CHECK:       # %bb.0: # %entry
1353; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu
1354; CHECK-NEXT:    vmul.vx v8, v8, a0
1355; CHECK-NEXT:    ret
1356entry:
1357  %a = call <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.i16(
1358    <vscale x 1 x i16> undef,
1359    <vscale x 1 x i16> %0,
1360    i16 %1,
1361    iXLen %2)
1362
1363  ret <vscale x 1 x i16> %a
1364}
1365
1366declare <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.i16(
1367  <vscale x 1 x i16>,
1368  <vscale x 1 x i16>,
1369  i16,
1370  <vscale x 1 x i1>,
1371  iXLen, iXLen);
1372
1373define <vscale x 1 x i16> @intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
1374; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16:
1375; CHECK:       # %bb.0: # %entry
1376; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu
1377; CHECK-NEXT:    vmul.vx v8, v9, a0, v0.t
1378; CHECK-NEXT:    ret
1379entry:
1380  %a = call <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.i16(
1381    <vscale x 1 x i16> %0,
1382    <vscale x 1 x i16> %1,
1383    i16 %2,
1384    <vscale x 1 x i1> %3,
1385    iXLen %4, iXLen 1)
1386
1387  ret <vscale x 1 x i16> %a
1388}
1389
1390declare <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.i16(
1391  <vscale x 2 x i16>,
1392  <vscale x 2 x i16>,
1393  i16,
1394  iXLen);
1395
1396define <vscale x 2 x i16> @intrinsic_vmul_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
1397; CHECK-LABEL: intrinsic_vmul_vx_nxv2i16_nxv2i16_i16:
1398; CHECK:       # %bb.0: # %entry
1399; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu
1400; CHECK-NEXT:    vmul.vx v8, v8, a0
1401; CHECK-NEXT:    ret
1402entry:
1403  %a = call <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.i16(
1404    <vscale x 2 x i16> undef,
1405    <vscale x 2 x i16> %0,
1406    i16 %1,
1407    iXLen %2)
1408
1409  ret <vscale x 2 x i16> %a
1410}
1411
1412declare <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.i16(
1413  <vscale x 2 x i16>,
1414  <vscale x 2 x i16>,
1415  i16,
1416  <vscale x 2 x i1>,
1417  iXLen, iXLen);
1418
1419define <vscale x 2 x i16> @intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
1420; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16:
1421; CHECK:       # %bb.0: # %entry
1422; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu
1423; CHECK-NEXT:    vmul.vx v8, v9, a0, v0.t
1424; CHECK-NEXT:    ret
1425entry:
1426  %a = call <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.i16(
1427    <vscale x 2 x i16> %0,
1428    <vscale x 2 x i16> %1,
1429    i16 %2,
1430    <vscale x 2 x i1> %3,
1431    iXLen %4, iXLen 1)
1432
1433  ret <vscale x 2 x i16> %a
1434}
1435
1436declare <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.i16(
1437  <vscale x 4 x i16>,
1438  <vscale x 4 x i16>,
1439  i16,
1440  iXLen);
1441
1442define <vscale x 4 x i16> @intrinsic_vmul_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
1443; CHECK-LABEL: intrinsic_vmul_vx_nxv4i16_nxv4i16_i16:
1444; CHECK:       # %bb.0: # %entry
1445; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu
1446; CHECK-NEXT:    vmul.vx v8, v8, a0
1447; CHECK-NEXT:    ret
1448entry:
1449  %a = call <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.i16(
1450    <vscale x 4 x i16> undef,
1451    <vscale x 4 x i16> %0,
1452    i16 %1,
1453    iXLen %2)
1454
1455  ret <vscale x 4 x i16> %a
1456}
1457
1458declare <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.i16(
1459  <vscale x 4 x i16>,
1460  <vscale x 4 x i16>,
1461  i16,
1462  <vscale x 4 x i1>,
1463  iXLen, iXLen);
1464
1465define <vscale x 4 x i16> @intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
1466; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16:
1467; CHECK:       # %bb.0: # %entry
1468; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu
1469; CHECK-NEXT:    vmul.vx v8, v9, a0, v0.t
1470; CHECK-NEXT:    ret
1471entry:
1472  %a = call <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.i16(
1473    <vscale x 4 x i16> %0,
1474    <vscale x 4 x i16> %1,
1475    i16 %2,
1476    <vscale x 4 x i1> %3,
1477    iXLen %4, iXLen 1)
1478
1479  ret <vscale x 4 x i16> %a
1480}
1481
1482declare <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.i16(
1483  <vscale x 8 x i16>,
1484  <vscale x 8 x i16>,
1485  i16,
1486  iXLen);
1487
1488define <vscale x 8 x i16> @intrinsic_vmul_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
1489; CHECK-LABEL: intrinsic_vmul_vx_nxv8i16_nxv8i16_i16:
1490; CHECK:       # %bb.0: # %entry
1491; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu
1492; CHECK-NEXT:    vmul.vx v8, v8, a0
1493; CHECK-NEXT:    ret
1494entry:
1495  %a = call <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.i16(
1496    <vscale x 8 x i16> undef,
1497    <vscale x 8 x i16> %0,
1498    i16 %1,
1499    iXLen %2)
1500
1501  ret <vscale x 8 x i16> %a
1502}
1503
1504declare <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.i16(
1505  <vscale x 8 x i16>,
1506  <vscale x 8 x i16>,
1507  i16,
1508  <vscale x 8 x i1>,
1509  iXLen, iXLen);
1510
1511define <vscale x 8 x i16> @intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
1512; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16:
1513; CHECK:       # %bb.0: # %entry
1514; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu
1515; CHECK-NEXT:    vmul.vx v8, v10, a0, v0.t
1516; CHECK-NEXT:    ret
1517entry:
1518  %a = call <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.i16(
1519    <vscale x 8 x i16> %0,
1520    <vscale x 8 x i16> %1,
1521    i16 %2,
1522    <vscale x 8 x i1> %3,
1523    iXLen %4, iXLen 1)
1524
1525  ret <vscale x 8 x i16> %a
1526}
1527
1528declare <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.i16(
1529  <vscale x 16 x i16>,
1530  <vscale x 16 x i16>,
1531  i16,
1532  iXLen);
1533
1534define <vscale x 16 x i16> @intrinsic_vmul_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
1535; CHECK-LABEL: intrinsic_vmul_vx_nxv16i16_nxv16i16_i16:
1536; CHECK:       # %bb.0: # %entry
1537; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
1538; CHECK-NEXT:    vmul.vx v8, v8, a0
1539; CHECK-NEXT:    ret
1540entry:
1541  %a = call <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.i16(
1542    <vscale x 16 x i16> undef,
1543    <vscale x 16 x i16> %0,
1544    i16 %1,
1545    iXLen %2)
1546
1547  ret <vscale x 16 x i16> %a
1548}
1549
1550declare <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.i16(
1551  <vscale x 16 x i16>,
1552  <vscale x 16 x i16>,
1553  i16,
1554  <vscale x 16 x i1>,
1555  iXLen, iXLen);
1556
1557define <vscale x 16 x i16> @intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
1558; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16:
1559; CHECK:       # %bb.0: # %entry
1560; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
1561; CHECK-NEXT:    vmul.vx v8, v12, a0, v0.t
1562; CHECK-NEXT:    ret
1563entry:
1564  %a = call <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.i16(
1565    <vscale x 16 x i16> %0,
1566    <vscale x 16 x i16> %1,
1567    i16 %2,
1568    <vscale x 16 x i1> %3,
1569    iXLen %4, iXLen 1)
1570
1571  ret <vscale x 16 x i16> %a
1572}
1573
1574declare <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.i16(
1575  <vscale x 32 x i16>,
1576  <vscale x 32 x i16>,
1577  i16,
1578  iXLen);
1579
1580define <vscale x 32 x i16> @intrinsic_vmul_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
1581; CHECK-LABEL: intrinsic_vmul_vx_nxv32i16_nxv32i16_i16:
1582; CHECK:       # %bb.0: # %entry
1583; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
1584; CHECK-NEXT:    vmul.vx v8, v8, a0
1585; CHECK-NEXT:    ret
1586entry:
1587  %a = call <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.i16(
1588    <vscale x 32 x i16> undef,
1589    <vscale x 32 x i16> %0,
1590    i16 %1,
1591    iXLen %2)
1592
1593  ret <vscale x 32 x i16> %a
1594}
1595
1596declare <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.i16(
1597  <vscale x 32 x i16>,
1598  <vscale x 32 x i16>,
1599  i16,
1600  <vscale x 32 x i1>,
1601  iXLen, iXLen);
1602
1603define <vscale x 32 x i16> @intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
1604; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16:
1605; CHECK:       # %bb.0: # %entry
1606; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
1607; CHECK-NEXT:    vmul.vx v8, v16, a0, v0.t
1608; CHECK-NEXT:    ret
1609entry:
1610  %a = call <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.i16(
1611    <vscale x 32 x i16> %0,
1612    <vscale x 32 x i16> %1,
1613    i16 %2,
1614    <vscale x 32 x i1> %3,
1615    iXLen %4, iXLen 1)
1616
1617  ret <vscale x 32 x i16> %a
1618}
1619
1620declare <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.i32(
1621  <vscale x 1 x i32>,
1622  <vscale x 1 x i32>,
1623  i32,
1624  iXLen);
1625
1626define <vscale x 1 x i32> @intrinsic_vmul_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
1627; CHECK-LABEL: intrinsic_vmul_vx_nxv1i32_nxv1i32_i32:
1628; CHECK:       # %bb.0: # %entry
1629; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
1630; CHECK-NEXT:    vmul.vx v8, v8, a0
1631; CHECK-NEXT:    ret
1632entry:
1633  %a = call <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.i32(
1634    <vscale x 1 x i32> undef,
1635    <vscale x 1 x i32> %0,
1636    i32 %1,
1637    iXLen %2)
1638
1639  ret <vscale x 1 x i32> %a
1640}
1641
1642declare <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.i32(
1643  <vscale x 1 x i32>,
1644  <vscale x 1 x i32>,
1645  i32,
1646  <vscale x 1 x i1>,
1647  iXLen, iXLen);
1648
1649define <vscale x 1 x i32> @intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
1650; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32:
1651; CHECK:       # %bb.0: # %entry
1652; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
1653; CHECK-NEXT:    vmul.vx v8, v9, a0, v0.t
1654; CHECK-NEXT:    ret
1655entry:
1656  %a = call <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.i32(
1657    <vscale x 1 x i32> %0,
1658    <vscale x 1 x i32> %1,
1659    i32 %2,
1660    <vscale x 1 x i1> %3,
1661    iXLen %4, iXLen 1)
1662
1663  ret <vscale x 1 x i32> %a
1664}
1665
1666declare <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.i32(
1667  <vscale x 2 x i32>,
1668  <vscale x 2 x i32>,
1669  i32,
1670  iXLen);
1671
1672define <vscale x 2 x i32> @intrinsic_vmul_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
1673; CHECK-LABEL: intrinsic_vmul_vx_nxv2i32_nxv2i32_i32:
1674; CHECK:       # %bb.0: # %entry
1675; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
1676; CHECK-NEXT:    vmul.vx v8, v8, a0
1677; CHECK-NEXT:    ret
1678entry:
1679  %a = call <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.i32(
1680    <vscale x 2 x i32> undef,
1681    <vscale x 2 x i32> %0,
1682    i32 %1,
1683    iXLen %2)
1684
1685  ret <vscale x 2 x i32> %a
1686}
1687
1688declare <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.i32(
1689  <vscale x 2 x i32>,
1690  <vscale x 2 x i32>,
1691  i32,
1692  <vscale x 2 x i1>,
1693  iXLen, iXLen);
1694
1695define <vscale x 2 x i32> @intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
1696; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32:
1697; CHECK:       # %bb.0: # %entry
1698; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
1699; CHECK-NEXT:    vmul.vx v8, v9, a0, v0.t
1700; CHECK-NEXT:    ret
1701entry:
1702  %a = call <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.i32(
1703    <vscale x 2 x i32> %0,
1704    <vscale x 2 x i32> %1,
1705    i32 %2,
1706    <vscale x 2 x i1> %3,
1707    iXLen %4, iXLen 1)
1708
1709  ret <vscale x 2 x i32> %a
1710}
1711
1712declare <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.i32(
1713  <vscale x 4 x i32>,
1714  <vscale x 4 x i32>,
1715  i32,
1716  iXLen);
1717
1718define <vscale x 4 x i32> @intrinsic_vmul_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
1719; CHECK-LABEL: intrinsic_vmul_vx_nxv4i32_nxv4i32_i32:
1720; CHECK:       # %bb.0: # %entry
1721; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
1722; CHECK-NEXT:    vmul.vx v8, v8, a0
1723; CHECK-NEXT:    ret
1724entry:
1725  %a = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.i32(
1726    <vscale x 4 x i32> undef,
1727    <vscale x 4 x i32> %0,
1728    i32 %1,
1729    iXLen %2)
1730
1731  ret <vscale x 4 x i32> %a
1732}
1733
1734declare <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.i32(
1735  <vscale x 4 x i32>,
1736  <vscale x 4 x i32>,
1737  i32,
1738  <vscale x 4 x i1>,
1739  iXLen, iXLen);
1740
1741define <vscale x 4 x i32> @intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
1742; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32:
1743; CHECK:       # %bb.0: # %entry
1744; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
1745; CHECK-NEXT:    vmul.vx v8, v10, a0, v0.t
1746; CHECK-NEXT:    ret
1747entry:
1748  %a = call <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.i32(
1749    <vscale x 4 x i32> %0,
1750    <vscale x 4 x i32> %1,
1751    i32 %2,
1752    <vscale x 4 x i1> %3,
1753    iXLen %4, iXLen 1)
1754
1755  ret <vscale x 4 x i32> %a
1756}
1757
1758declare <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.i32(
1759  <vscale x 8 x i32>,
1760  <vscale x 8 x i32>,
1761  i32,
1762  iXLen);
1763
1764define <vscale x 8 x i32> @intrinsic_vmul_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
1765; CHECK-LABEL: intrinsic_vmul_vx_nxv8i32_nxv8i32_i32:
1766; CHECK:       # %bb.0: # %entry
1767; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
1768; CHECK-NEXT:    vmul.vx v8, v8, a0
1769; CHECK-NEXT:    ret
1770entry:
1771  %a = call <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.i32(
1772    <vscale x 8 x i32> undef,
1773    <vscale x 8 x i32> %0,
1774    i32 %1,
1775    iXLen %2)
1776
1777  ret <vscale x 8 x i32> %a
1778}
1779
1780declare <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.i32(
1781  <vscale x 8 x i32>,
1782  <vscale x 8 x i32>,
1783  i32,
1784  <vscale x 8 x i1>,
1785  iXLen, iXLen);
1786
1787define <vscale x 8 x i32> @intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
1788; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32:
1789; CHECK:       # %bb.0: # %entry
1790; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
1791; CHECK-NEXT:    vmul.vx v8, v12, a0, v0.t
1792; CHECK-NEXT:    ret
1793entry:
1794  %a = call <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.i32(
1795    <vscale x 8 x i32> %0,
1796    <vscale x 8 x i32> %1,
1797    i32 %2,
1798    <vscale x 8 x i1> %3,
1799    iXLen %4, iXLen 1)
1800
1801  ret <vscale x 8 x i32> %a
1802}
1803
1804declare <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.i32(
1805  <vscale x 16 x i32>,
1806  <vscale x 16 x i32>,
1807  i32,
1808  iXLen);
1809
1810define <vscale x 16 x i32> @intrinsic_vmul_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
1811; CHECK-LABEL: intrinsic_vmul_vx_nxv16i32_nxv16i32_i32:
1812; CHECK:       # %bb.0: # %entry
1813; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu
1814; CHECK-NEXT:    vmul.vx v8, v8, a0
1815; CHECK-NEXT:    ret
1816entry:
1817  %a = call <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.i32(
1818    <vscale x 16 x i32> undef,
1819    <vscale x 16 x i32> %0,
1820    i32 %1,
1821    iXLen %2)
1822
1823  ret <vscale x 16 x i32> %a
1824}
1825
1826declare <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.i32(
1827  <vscale x 16 x i32>,
1828  <vscale x 16 x i32>,
1829  i32,
1830  <vscale x 16 x i1>,
1831  iXLen, iXLen);
1832
1833define <vscale x 16 x i32> @intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
1834; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32:
1835; CHECK:       # %bb.0: # %entry
1836; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu
1837; CHECK-NEXT:    vmul.vx v8, v16, a0, v0.t
1838; CHECK-NEXT:    ret
1839entry:
1840  %a = call <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.i32(
1841    <vscale x 16 x i32> %0,
1842    <vscale x 16 x i32> %1,
1843    i32 %2,
1844    <vscale x 16 x i1> %3,
1845    iXLen %4, iXLen 1)
1846
1847  ret <vscale x 16 x i32> %a
1848}
1849
1850declare <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.i64(
1851  <vscale x 1 x i64>,
1852  <vscale x 1 x i64>,
1853  i64,
1854  iXLen);
1855
1856define <vscale x 1 x i64> @intrinsic_vmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
1857; RV32-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64:
1858; RV32:       # %bb.0: # %entry
1859; RV32-NEXT:    addi sp, sp, -16
1860; RV32-NEXT:    sw a1, 12(sp)
1861; RV32-NEXT:    sw a0, 8(sp)
1862; RV32-NEXT:    addi a0, sp, 8
1863; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
1864; RV32-NEXT:    vlse64.v v9, (a0), zero
1865; RV32-NEXT:    vmul.vv v8, v8, v9
1866; RV32-NEXT:    addi sp, sp, 16
1867; RV32-NEXT:    ret
1868;
1869; RV64-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64:
1870; RV64:       # %bb.0: # %entry
1871; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
1872; RV64-NEXT:    vmul.vx v8, v8, a0
1873; RV64-NEXT:    ret
1874entry:
1875  %a = call <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.i64(
1876    <vscale x 1 x i64> undef,
1877    <vscale x 1 x i64> %0,
1878    i64 %1,
1879    iXLen %2)
1880
1881  ret <vscale x 1 x i64> %a
1882}
1883
1884declare <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.i64(
1885  <vscale x 1 x i64>,
1886  <vscale x 1 x i64>,
1887  i64,
1888  <vscale x 1 x i1>,
1889  iXLen, iXLen);
1890
1891define <vscale x 1 x i64> @intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
1892; RV32-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64:
1893; RV32:       # %bb.0: # %entry
1894; RV32-NEXT:    addi sp, sp, -16
1895; RV32-NEXT:    sw a1, 12(sp)
1896; RV32-NEXT:    sw a0, 8(sp)
1897; RV32-NEXT:    addi a0, sp, 8
1898; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
1899; RV32-NEXT:    vlse64.v v10, (a0), zero
1900; RV32-NEXT:    vmul.vv v8, v9, v10, v0.t
1901; RV32-NEXT:    addi sp, sp, 16
1902; RV32-NEXT:    ret
1903;
1904; RV64-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64:
1905; RV64:       # %bb.0: # %entry
1906; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
1907; RV64-NEXT:    vmul.vx v8, v9, a0, v0.t
1908; RV64-NEXT:    ret
1909entry:
1910  %a = call <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.i64(
1911    <vscale x 1 x i64> %0,
1912    <vscale x 1 x i64> %1,
1913    i64 %2,
1914    <vscale x 1 x i1> %3,
1915    iXLen %4, iXLen 1)
1916
1917  ret <vscale x 1 x i64> %a
1918}
1919
1920declare <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.i64(
1921  <vscale x 2 x i64>,
1922  <vscale x 2 x i64>,
1923  i64,
1924  iXLen);
1925
1926define <vscale x 2 x i64> @intrinsic_vmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
1927; RV32-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64:
1928; RV32:       # %bb.0: # %entry
1929; RV32-NEXT:    addi sp, sp, -16
1930; RV32-NEXT:    sw a1, 12(sp)
1931; RV32-NEXT:    sw a0, 8(sp)
1932; RV32-NEXT:    addi a0, sp, 8
1933; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
1934; RV32-NEXT:    vlse64.v v10, (a0), zero
1935; RV32-NEXT:    vmul.vv v8, v8, v10
1936; RV32-NEXT:    addi sp, sp, 16
1937; RV32-NEXT:    ret
1938;
1939; RV64-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64:
1940; RV64:       # %bb.0: # %entry
1941; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, mu
1942; RV64-NEXT:    vmul.vx v8, v8, a0
1943; RV64-NEXT:    ret
1944entry:
1945  %a = call <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.i64(
1946    <vscale x 2 x i64> undef,
1947    <vscale x 2 x i64> %0,
1948    i64 %1,
1949    iXLen %2)
1950
1951  ret <vscale x 2 x i64> %a
1952}
1953
1954declare <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.i64(
1955  <vscale x 2 x i64>,
1956  <vscale x 2 x i64>,
1957  i64,
1958  <vscale x 2 x i1>,
1959  iXLen, iXLen);
1960
1961define <vscale x 2 x i64> @intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
1962; RV32-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64:
1963; RV32:       # %bb.0: # %entry
1964; RV32-NEXT:    addi sp, sp, -16
1965; RV32-NEXT:    sw a1, 12(sp)
1966; RV32-NEXT:    sw a0, 8(sp)
1967; RV32-NEXT:    addi a0, sp, 8
1968; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu
1969; RV32-NEXT:    vlse64.v v12, (a0), zero
1970; RV32-NEXT:    vmul.vv v8, v10, v12, v0.t
1971; RV32-NEXT:    addi sp, sp, 16
1972; RV32-NEXT:    ret
1973;
1974; RV64-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64:
1975; RV64:       # %bb.0: # %entry
1976; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, mu
1977; RV64-NEXT:    vmul.vx v8, v10, a0, v0.t
1978; RV64-NEXT:    ret
1979entry:
1980  %a = call <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.i64(
1981    <vscale x 2 x i64> %0,
1982    <vscale x 2 x i64> %1,
1983    i64 %2,
1984    <vscale x 2 x i1> %3,
1985    iXLen %4, iXLen 1)
1986
1987  ret <vscale x 2 x i64> %a
1988}
1989
1990declare <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.i64(
1991  <vscale x 4 x i64>,
1992  <vscale x 4 x i64>,
1993  i64,
1994  iXLen);
1995
1996define <vscale x 4 x i64> @intrinsic_vmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
1997; RV32-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64:
1998; RV32:       # %bb.0: # %entry
1999; RV32-NEXT:    addi sp, sp, -16
2000; RV32-NEXT:    sw a1, 12(sp)
2001; RV32-NEXT:    sw a0, 8(sp)
2002; RV32-NEXT:    addi a0, sp, 8
2003; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
2004; RV32-NEXT:    vlse64.v v12, (a0), zero
2005; RV32-NEXT:    vmul.vv v8, v8, v12
2006; RV32-NEXT:    addi sp, sp, 16
2007; RV32-NEXT:    ret
2008;
2009; RV64-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64:
2010; RV64:       # %bb.0: # %entry
2011; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, mu
2012; RV64-NEXT:    vmul.vx v8, v8, a0
2013; RV64-NEXT:    ret
2014entry:
2015  %a = call <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.i64(
2016    <vscale x 4 x i64> undef,
2017    <vscale x 4 x i64> %0,
2018    i64 %1,
2019    iXLen %2)
2020
2021  ret <vscale x 4 x i64> %a
2022}
2023
2024declare <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.i64(
2025  <vscale x 4 x i64>,
2026  <vscale x 4 x i64>,
2027  i64,
2028  <vscale x 4 x i1>,
2029  iXLen, iXLen);
2030
2031define <vscale x 4 x i64> @intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
2032; RV32-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64:
2033; RV32:       # %bb.0: # %entry
2034; RV32-NEXT:    addi sp, sp, -16
2035; RV32-NEXT:    sw a1, 12(sp)
2036; RV32-NEXT:    sw a0, 8(sp)
2037; RV32-NEXT:    addi a0, sp, 8
2038; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu
2039; RV32-NEXT:    vlse64.v v16, (a0), zero
2040; RV32-NEXT:    vmul.vv v8, v12, v16, v0.t
2041; RV32-NEXT:    addi sp, sp, 16
2042; RV32-NEXT:    ret
2043;
2044; RV64-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64:
2045; RV64:       # %bb.0: # %entry
2046; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, mu
2047; RV64-NEXT:    vmul.vx v8, v12, a0, v0.t
2048; RV64-NEXT:    ret
2049entry:
2050  %a = call <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.i64(
2051    <vscale x 4 x i64> %0,
2052    <vscale x 4 x i64> %1,
2053    i64 %2,
2054    <vscale x 4 x i1> %3,
2055    iXLen %4, iXLen 1)
2056
2057  ret <vscale x 4 x i64> %a
2058}
2059
2060declare <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.i64(
2061  <vscale x 8 x i64>,
2062  <vscale x 8 x i64>,
2063  i64,
2064  iXLen);
2065
2066define <vscale x 8 x i64> @intrinsic_vmul_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
2067; RV32-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64:
2068; RV32:       # %bb.0: # %entry
2069; RV32-NEXT:    addi sp, sp, -16
2070; RV32-NEXT:    sw a1, 12(sp)
2071; RV32-NEXT:    sw a0, 8(sp)
2072; RV32-NEXT:    addi a0, sp, 8
2073; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
2074; RV32-NEXT:    vlse64.v v16, (a0), zero
2075; RV32-NEXT:    vmul.vv v8, v8, v16
2076; RV32-NEXT:    addi sp, sp, 16
2077; RV32-NEXT:    ret
2078;
2079; RV64-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64:
2080; RV64:       # %bb.0: # %entry
2081; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
2082; RV64-NEXT:    vmul.vx v8, v8, a0
2083; RV64-NEXT:    ret
2084entry:
2085  %a = call <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.i64(
2086    <vscale x 8 x i64> undef,
2087    <vscale x 8 x i64> %0,
2088    i64 %1,
2089    iXLen %2)
2090
2091  ret <vscale x 8 x i64> %a
2092}
2093
2094declare <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.i64(
2095  <vscale x 8 x i64>,
2096  <vscale x 8 x i64>,
2097  i64,
2098  <vscale x 8 x i1>,
2099  iXLen, iXLen);
2100
2101define <vscale x 8 x i64> @intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
2102; RV32-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64:
2103; RV32:       # %bb.0: # %entry
2104; RV32-NEXT:    addi sp, sp, -16
2105; RV32-NEXT:    sw a1, 12(sp)
2106; RV32-NEXT:    sw a0, 8(sp)
2107; RV32-NEXT:    addi a0, sp, 8
2108; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu
2109; RV32-NEXT:    vlse64.v v24, (a0), zero
2110; RV32-NEXT:    vmul.vv v8, v16, v24, v0.t
2111; RV32-NEXT:    addi sp, sp, 16
2112; RV32-NEXT:    ret
2113;
2114; RV64-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64:
2115; RV64:       # %bb.0: # %entry
2116; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu
2117; RV64-NEXT:    vmul.vx v8, v16, a0, v0.t
2118; RV64-NEXT:    ret
2119entry:
2120  %a = call <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.i64(
2121    <vscale x 8 x i64> %0,
2122    <vscale x 8 x i64> %1,
2123    i64 %2,
2124    <vscale x 8 x i1> %3,
2125    iXLen %4, iXLen 1)
2126
2127  ret <vscale x 8 x i64> %a
2128}
2129