1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 4 5define <vscale x 1 x i8> @vmul_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) { 6; CHECK-LABEL: vmul_vv_nxv1i8: 7; CHECK: # %bb.0: 8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 9; CHECK-NEXT: vmul.vv v8, v8, v9 10; CHECK-NEXT: ret 11 %vc = mul <vscale x 1 x i8> %va, %vb 12 ret <vscale x 1 x i8> %vc 13} 14 15define <vscale x 1 x i8> @vmul_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) { 16; CHECK-LABEL: vmul_vx_nxv1i8: 17; CHECK: # %bb.0: 18; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 19; CHECK-NEXT: vmul.vx v8, v8, a0 20; CHECK-NEXT: ret 21 %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0 22 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer 23 %vc = mul <vscale x 1 x i8> %va, %splat 24 ret <vscale x 1 x i8> %vc 25} 26 27define <vscale x 1 x i8> @vmul_vi_nxv1i8_0(<vscale x 1 x i8> %va) { 28; CHECK-LABEL: vmul_vi_nxv1i8_0: 29; CHECK: # %bb.0: 30; CHECK-NEXT: li a0, -7 31; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 32; CHECK-NEXT: vmul.vx v8, v8, a0 33; CHECK-NEXT: ret 34 %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0 35 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer 36 %vc = mul <vscale x 1 x i8> %va, %splat 37 ret <vscale x 1 x i8> %vc 38} 39 40define <vscale x 2 x i8> @vmul_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) { 41; CHECK-LABEL: vmul_vv_nxv2i8: 42; CHECK: # %bb.0: 43; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu 44; CHECK-NEXT: vmul.vv v8, v8, v9 45; CHECK-NEXT: ret 46 %vc = mul <vscale x 2 x i8> %va, %vb 47 ret <vscale x 2 x i8> %vc 48} 49 50define <vscale x 2 x i8> @vmul_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) { 51; CHECK-LABEL: vmul_vx_nxv2i8: 52; CHECK: # %bb.0: 53; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 54; CHECK-NEXT: vmul.vx v8, v8, a0 55; CHECK-NEXT: ret 56 %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0 57 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer 58 %vc = mul <vscale x 2 x i8> %va, %splat 59 ret <vscale x 2 x i8> %vc 60} 61 62define <vscale x 2 x i8> @vmul_vi_nxv2i8_0(<vscale x 2 x i8> %va) { 63; CHECK-LABEL: vmul_vi_nxv2i8_0: 64; CHECK: # %bb.0: 65; CHECK-NEXT: li a0, -7 66; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 67; CHECK-NEXT: vmul.vx v8, v8, a0 68; CHECK-NEXT: ret 69 %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0 70 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer 71 %vc = mul <vscale x 2 x i8> %va, %splat 72 ret <vscale x 2 x i8> %vc 73} 74 75define <vscale x 4 x i8> @vmul_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) { 76; CHECK-LABEL: vmul_vv_nxv4i8: 77; CHECK: # %bb.0: 78; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 79; CHECK-NEXT: vmul.vv v8, v8, v9 80; CHECK-NEXT: ret 81 %vc = mul <vscale x 4 x i8> %va, %vb 82 ret <vscale x 4 x i8> %vc 83} 84 85define <vscale x 4 x i8> @vmul_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) { 86; CHECK-LABEL: vmul_vx_nxv4i8: 87; CHECK: # %bb.0: 88; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 89; CHECK-NEXT: vmul.vx v8, v8, a0 90; CHECK-NEXT: ret 91 %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0 92 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer 93 %vc = mul <vscale x 4 x i8> %va, %splat 94 ret <vscale x 4 x i8> %vc 95} 96 97define <vscale x 4 x i8> @vmul_vi_nxv4i8_0(<vscale x 4 x i8> %va) { 98; CHECK-LABEL: vmul_vi_nxv4i8_0: 99; CHECK: # %bb.0: 100; CHECK-NEXT: li a0, -7 101; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 102; CHECK-NEXT: vmul.vx v8, v8, a0 103; CHECK-NEXT: ret 104 %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0 105 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer 106 %vc = mul <vscale x 4 x i8> %va, %splat 107 ret <vscale x 4 x i8> %vc 108} 109 110define <vscale x 8 x i8> @vmul_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 111; CHECK-LABEL: vmul_vv_nxv8i8: 112; CHECK: # %bb.0: 113; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 114; CHECK-NEXT: vmul.vv v8, v8, v9 115; CHECK-NEXT: ret 116 %vc = mul <vscale x 8 x i8> %va, %vb 117 ret <vscale x 8 x i8> %vc 118} 119 120define <vscale x 8 x i8> @vmul_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) { 121; CHECK-LABEL: vmul_vx_nxv8i8: 122; CHECK: # %bb.0: 123; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 124; CHECK-NEXT: vmul.vx v8, v8, a0 125; CHECK-NEXT: ret 126 %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0 127 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer 128 %vc = mul <vscale x 8 x i8> %va, %splat 129 ret <vscale x 8 x i8> %vc 130} 131 132define <vscale x 8 x i8> @vmul_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 133; CHECK-LABEL: vmul_vi_nxv8i8_0: 134; CHECK: # %bb.0: 135; CHECK-NEXT: li a0, -7 136; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 137; CHECK-NEXT: vmul.vx v8, v8, a0 138; CHECK-NEXT: ret 139 %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0 140 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer 141 %vc = mul <vscale x 8 x i8> %va, %splat 142 ret <vscale x 8 x i8> %vc 143} 144 145define <vscale x 16 x i8> @vmul_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) { 146; CHECK-LABEL: vmul_vv_nxv16i8: 147; CHECK: # %bb.0: 148; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu 149; CHECK-NEXT: vmul.vv v8, v8, v10 150; CHECK-NEXT: ret 151 %vc = mul <vscale x 16 x i8> %va, %vb 152 ret <vscale x 16 x i8> %vc 153} 154 155define <vscale x 16 x i8> @vmul_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) { 156; CHECK-LABEL: vmul_vx_nxv16i8: 157; CHECK: # %bb.0: 158; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 159; CHECK-NEXT: vmul.vx v8, v8, a0 160; CHECK-NEXT: ret 161 %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0 162 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 163 %vc = mul <vscale x 16 x i8> %va, %splat 164 ret <vscale x 16 x i8> %vc 165} 166 167define <vscale x 16 x i8> @vmul_vi_nxv16i8_0(<vscale x 16 x i8> %va) { 168; CHECK-LABEL: vmul_vi_nxv16i8_0: 169; CHECK: # %bb.0: 170; CHECK-NEXT: li a0, -7 171; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 172; CHECK-NEXT: vmul.vx v8, v8, a0 173; CHECK-NEXT: ret 174 %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0 175 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 176 %vc = mul <vscale x 16 x i8> %va, %splat 177 ret <vscale x 16 x i8> %vc 178} 179 180define <vscale x 32 x i8> @vmul_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) { 181; CHECK-LABEL: vmul_vv_nxv32i8: 182; CHECK: # %bb.0: 183; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu 184; CHECK-NEXT: vmul.vv v8, v8, v12 185; CHECK-NEXT: ret 186 %vc = mul <vscale x 32 x i8> %va, %vb 187 ret <vscale x 32 x i8> %vc 188} 189 190define <vscale x 32 x i8> @vmul_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) { 191; CHECK-LABEL: vmul_vx_nxv32i8: 192; CHECK: # %bb.0: 193; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 194; CHECK-NEXT: vmul.vx v8, v8, a0 195; CHECK-NEXT: ret 196 %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0 197 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer 198 %vc = mul <vscale x 32 x i8> %va, %splat 199 ret <vscale x 32 x i8> %vc 200} 201 202define <vscale x 32 x i8> @vmul_vi_nxv32i8_0(<vscale x 32 x i8> %va) { 203; CHECK-LABEL: vmul_vi_nxv32i8_0: 204; CHECK: # %bb.0: 205; CHECK-NEXT: li a0, -7 206; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 207; CHECK-NEXT: vmul.vx v8, v8, a0 208; CHECK-NEXT: ret 209 %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0 210 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer 211 %vc = mul <vscale x 32 x i8> %va, %splat 212 ret <vscale x 32 x i8> %vc 213} 214 215define <vscale x 64 x i8> @vmul_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) { 216; CHECK-LABEL: vmul_vv_nxv64i8: 217; CHECK: # %bb.0: 218; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu 219; CHECK-NEXT: vmul.vv v8, v8, v16 220; CHECK-NEXT: ret 221 %vc = mul <vscale x 64 x i8> %va, %vb 222 ret <vscale x 64 x i8> %vc 223} 224 225define <vscale x 64 x i8> @vmul_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) { 226; CHECK-LABEL: vmul_vx_nxv64i8: 227; CHECK: # %bb.0: 228; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 229; CHECK-NEXT: vmul.vx v8, v8, a0 230; CHECK-NEXT: ret 231 %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0 232 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer 233 %vc = mul <vscale x 64 x i8> %va, %splat 234 ret <vscale x 64 x i8> %vc 235} 236 237define <vscale x 64 x i8> @vmul_vi_nxv64i8_0(<vscale x 64 x i8> %va) { 238; CHECK-LABEL: vmul_vi_nxv64i8_0: 239; CHECK: # %bb.0: 240; CHECK-NEXT: li a0, -7 241; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 242; CHECK-NEXT: vmul.vx v8, v8, a0 243; CHECK-NEXT: ret 244 %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0 245 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer 246 %vc = mul <vscale x 64 x i8> %va, %splat 247 ret <vscale x 64 x i8> %vc 248} 249 250define <vscale x 1 x i16> @vmul_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) { 251; CHECK-LABEL: vmul_vv_nxv1i16: 252; CHECK: # %bb.0: 253; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu 254; CHECK-NEXT: vmul.vv v8, v8, v9 255; CHECK-NEXT: ret 256 %vc = mul <vscale x 1 x i16> %va, %vb 257 ret <vscale x 1 x i16> %vc 258} 259 260define <vscale x 1 x i16> @vmul_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) { 261; CHECK-LABEL: vmul_vx_nxv1i16: 262; CHECK: # %bb.0: 263; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 264; CHECK-NEXT: vmul.vx v8, v8, a0 265; CHECK-NEXT: ret 266 %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0 267 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer 268 %vc = mul <vscale x 1 x i16> %va, %splat 269 ret <vscale x 1 x i16> %vc 270} 271 272define <vscale x 1 x i16> @vmul_vi_nxv1i16_0(<vscale x 1 x i16> %va) { 273; CHECK-LABEL: vmul_vi_nxv1i16_0: 274; CHECK: # %bb.0: 275; CHECK-NEXT: li a0, -7 276; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 277; CHECK-NEXT: vmul.vx v8, v8, a0 278; CHECK-NEXT: ret 279 %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0 280 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer 281 %vc = mul <vscale x 1 x i16> %va, %splat 282 ret <vscale x 1 x i16> %vc 283} 284 285define <vscale x 2 x i16> @vmul_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) { 286; CHECK-LABEL: vmul_vv_nxv2i16: 287; CHECK: # %bb.0: 288; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu 289; CHECK-NEXT: vmul.vv v8, v8, v9 290; CHECK-NEXT: ret 291 %vc = mul <vscale x 2 x i16> %va, %vb 292 ret <vscale x 2 x i16> %vc 293} 294 295define <vscale x 2 x i16> @vmul_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) { 296; CHECK-LABEL: vmul_vx_nxv2i16: 297; CHECK: # %bb.0: 298; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 299; CHECK-NEXT: vmul.vx v8, v8, a0 300; CHECK-NEXT: ret 301 %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0 302 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer 303 %vc = mul <vscale x 2 x i16> %va, %splat 304 ret <vscale x 2 x i16> %vc 305} 306 307define <vscale x 2 x i16> @vmul_vi_nxv2i16_0(<vscale x 2 x i16> %va) { 308; CHECK-LABEL: vmul_vi_nxv2i16_0: 309; CHECK: # %bb.0: 310; CHECK-NEXT: li a0, -7 311; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 312; CHECK-NEXT: vmul.vx v8, v8, a0 313; CHECK-NEXT: ret 314 %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0 315 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer 316 %vc = mul <vscale x 2 x i16> %va, %splat 317 ret <vscale x 2 x i16> %vc 318} 319 320define <vscale x 4 x i16> @vmul_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) { 321; CHECK-LABEL: vmul_vv_nxv4i16: 322; CHECK: # %bb.0: 323; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu 324; CHECK-NEXT: vmul.vv v8, v8, v9 325; CHECK-NEXT: ret 326 %vc = mul <vscale x 4 x i16> %va, %vb 327 ret <vscale x 4 x i16> %vc 328} 329 330define <vscale x 4 x i16> @vmul_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) { 331; CHECK-LABEL: vmul_vx_nxv4i16: 332; CHECK: # %bb.0: 333; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu 334; CHECK-NEXT: vmul.vx v8, v8, a0 335; CHECK-NEXT: ret 336 %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0 337 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer 338 %vc = mul <vscale x 4 x i16> %va, %splat 339 ret <vscale x 4 x i16> %vc 340} 341 342define <vscale x 4 x i16> @vmul_vi_nxv4i16_0(<vscale x 4 x i16> %va) { 343; CHECK-LABEL: vmul_vi_nxv4i16_0: 344; CHECK: # %bb.0: 345; CHECK-NEXT: li a0, -7 346; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu 347; CHECK-NEXT: vmul.vx v8, v8, a0 348; CHECK-NEXT: ret 349 %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0 350 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer 351 %vc = mul <vscale x 4 x i16> %va, %splat 352 ret <vscale x 4 x i16> %vc 353} 354 355define <vscale x 8 x i16> @vmul_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 356; CHECK-LABEL: vmul_vv_nxv8i16: 357; CHECK: # %bb.0: 358; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu 359; CHECK-NEXT: vmul.vv v8, v8, v10 360; CHECK-NEXT: ret 361 %vc = mul <vscale x 8 x i16> %va, %vb 362 ret <vscale x 8 x i16> %vc 363} 364 365define <vscale x 8 x i16> @vmul_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) { 366; CHECK-LABEL: vmul_vx_nxv8i16: 367; CHECK: # %bb.0: 368; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu 369; CHECK-NEXT: vmul.vx v8, v8, a0 370; CHECK-NEXT: ret 371 %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0 372 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 373 %vc = mul <vscale x 8 x i16> %va, %splat 374 ret <vscale x 8 x i16> %vc 375} 376 377define <vscale x 8 x i16> @vmul_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 378; CHECK-LABEL: vmul_vi_nxv8i16_0: 379; CHECK: # %bb.0: 380; CHECK-NEXT: li a0, -7 381; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu 382; CHECK-NEXT: vmul.vx v8, v8, a0 383; CHECK-NEXT: ret 384 %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0 385 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 386 %vc = mul <vscale x 8 x i16> %va, %splat 387 ret <vscale x 8 x i16> %vc 388} 389 390define <vscale x 16 x i16> @vmul_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) { 391; CHECK-LABEL: vmul_vv_nxv16i16: 392; CHECK: # %bb.0: 393; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 394; CHECK-NEXT: vmul.vv v8, v8, v12 395; CHECK-NEXT: ret 396 %vc = mul <vscale x 16 x i16> %va, %vb 397 ret <vscale x 16 x i16> %vc 398} 399 400define <vscale x 16 x i16> @vmul_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) { 401; CHECK-LABEL: vmul_vx_nxv16i16: 402; CHECK: # %bb.0: 403; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu 404; CHECK-NEXT: vmul.vx v8, v8, a0 405; CHECK-NEXT: ret 406 %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0 407 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer 408 %vc = mul <vscale x 16 x i16> %va, %splat 409 ret <vscale x 16 x i16> %vc 410} 411 412define <vscale x 16 x i16> @vmul_vi_nxv16i16_0(<vscale x 16 x i16> %va) { 413; CHECK-LABEL: vmul_vi_nxv16i16_0: 414; CHECK: # %bb.0: 415; CHECK-NEXT: li a0, -7 416; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu 417; CHECK-NEXT: vmul.vx v8, v8, a0 418; CHECK-NEXT: ret 419 %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0 420 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer 421 %vc = mul <vscale x 16 x i16> %va, %splat 422 ret <vscale x 16 x i16> %vc 423} 424 425define <vscale x 32 x i16> @vmul_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) { 426; CHECK-LABEL: vmul_vv_nxv32i16: 427; CHECK: # %bb.0: 428; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu 429; CHECK-NEXT: vmul.vv v8, v8, v16 430; CHECK-NEXT: ret 431 %vc = mul <vscale x 32 x i16> %va, %vb 432 ret <vscale x 32 x i16> %vc 433} 434 435define <vscale x 32 x i16> @vmul_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) { 436; CHECK-LABEL: vmul_vx_nxv32i16: 437; CHECK: # %bb.0: 438; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu 439; CHECK-NEXT: vmul.vx v8, v8, a0 440; CHECK-NEXT: ret 441 %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0 442 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer 443 %vc = mul <vscale x 32 x i16> %va, %splat 444 ret <vscale x 32 x i16> %vc 445} 446 447define <vscale x 32 x i16> @vmul_vi_nxv32i16_0(<vscale x 32 x i16> %va) { 448; CHECK-LABEL: vmul_vi_nxv32i16_0: 449; CHECK: # %bb.0: 450; CHECK-NEXT: li a0, -7 451; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu 452; CHECK-NEXT: vmul.vx v8, v8, a0 453; CHECK-NEXT: ret 454 %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0 455 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer 456 %vc = mul <vscale x 32 x i16> %va, %splat 457 ret <vscale x 32 x i16> %vc 458} 459 460define <vscale x 1 x i32> @vmul_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) { 461; CHECK-LABEL: vmul_vv_nxv1i32: 462; CHECK: # %bb.0: 463; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu 464; CHECK-NEXT: vmul.vv v8, v8, v9 465; CHECK-NEXT: ret 466 %vc = mul <vscale x 1 x i32> %va, %vb 467 ret <vscale x 1 x i32> %vc 468} 469 470define <vscale x 1 x i32> @vmul_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) { 471; CHECK-LABEL: vmul_vx_nxv1i32: 472; CHECK: # %bb.0: 473; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 474; CHECK-NEXT: vmul.vx v8, v8, a0 475; CHECK-NEXT: ret 476 %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0 477 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer 478 %vc = mul <vscale x 1 x i32> %va, %splat 479 ret <vscale x 1 x i32> %vc 480} 481 482define <vscale x 1 x i32> @vmul_vi_nxv1i32_0(<vscale x 1 x i32> %va) { 483; CHECK-LABEL: vmul_vi_nxv1i32_0: 484; CHECK: # %bb.0: 485; CHECK-NEXT: li a0, -7 486; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 487; CHECK-NEXT: vmul.vx v8, v8, a0 488; CHECK-NEXT: ret 489 %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0 490 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer 491 %vc = mul <vscale x 1 x i32> %va, %splat 492 ret <vscale x 1 x i32> %vc 493} 494 495define <vscale x 2 x i32> @vmul_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) { 496; CHECK-LABEL: vmul_vv_nxv2i32: 497; CHECK: # %bb.0: 498; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu 499; CHECK-NEXT: vmul.vv v8, v8, v9 500; CHECK-NEXT: ret 501 %vc = mul <vscale x 2 x i32> %va, %vb 502 ret <vscale x 2 x i32> %vc 503} 504 505define <vscale x 2 x i32> @vmul_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) { 506; CHECK-LABEL: vmul_vx_nxv2i32: 507; CHECK: # %bb.0: 508; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu 509; CHECK-NEXT: vmul.vx v8, v8, a0 510; CHECK-NEXT: ret 511 %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0 512 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer 513 %vc = mul <vscale x 2 x i32> %va, %splat 514 ret <vscale x 2 x i32> %vc 515} 516 517define <vscale x 2 x i32> @vmul_vi_nxv2i32_0(<vscale x 2 x i32> %va) { 518; CHECK-LABEL: vmul_vi_nxv2i32_0: 519; CHECK: # %bb.0: 520; CHECK-NEXT: li a0, -7 521; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu 522; CHECK-NEXT: vmul.vx v8, v8, a0 523; CHECK-NEXT: ret 524 %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0 525 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer 526 %vc = mul <vscale x 2 x i32> %va, %splat 527 ret <vscale x 2 x i32> %vc 528} 529 530define <vscale x 4 x i32> @vmul_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) { 531; CHECK-LABEL: vmul_vv_nxv4i32: 532; CHECK: # %bb.0: 533; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu 534; CHECK-NEXT: vmul.vv v8, v8, v10 535; CHECK-NEXT: ret 536 %vc = mul <vscale x 4 x i32> %va, %vb 537 ret <vscale x 4 x i32> %vc 538} 539 540define <vscale x 4 x i32> @vmul_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) { 541; CHECK-LABEL: vmul_vx_nxv4i32: 542; CHECK: # %bb.0: 543; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu 544; CHECK-NEXT: vmul.vx v8, v8, a0 545; CHECK-NEXT: ret 546 %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0 547 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 548 %vc = mul <vscale x 4 x i32> %va, %splat 549 ret <vscale x 4 x i32> %vc 550} 551 552define <vscale x 4 x i32> @vmul_vi_nxv4i32_0(<vscale x 4 x i32> %va) { 553; CHECK-LABEL: vmul_vi_nxv4i32_0: 554; CHECK: # %bb.0: 555; CHECK-NEXT: li a0, -7 556; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu 557; CHECK-NEXT: vmul.vx v8, v8, a0 558; CHECK-NEXT: ret 559 %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0 560 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 561 %vc = mul <vscale x 4 x i32> %va, %splat 562 ret <vscale x 4 x i32> %vc 563} 564 565define <vscale x 8 x i32> @vmul_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 566; CHECK-LABEL: vmul_vv_nxv8i32: 567; CHECK: # %bb.0: 568; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu 569; CHECK-NEXT: vmul.vv v8, v8, v12 570; CHECK-NEXT: ret 571 %vc = mul <vscale x 8 x i32> %va, %vb 572 ret <vscale x 8 x i32> %vc 573} 574 575define <vscale x 8 x i32> @vmul_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) { 576; CHECK-LABEL: vmul_vx_nxv8i32: 577; CHECK: # %bb.0: 578; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu 579; CHECK-NEXT: vmul.vx v8, v8, a0 580; CHECK-NEXT: ret 581 %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0 582 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer 583 %vc = mul <vscale x 8 x i32> %va, %splat 584 ret <vscale x 8 x i32> %vc 585} 586 587define <vscale x 8 x i32> @vmul_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 588; CHECK-LABEL: vmul_vi_nxv8i32_0: 589; CHECK: # %bb.0: 590; CHECK-NEXT: li a0, -7 591; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu 592; CHECK-NEXT: vmul.vx v8, v8, a0 593; CHECK-NEXT: ret 594 %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0 595 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer 596 %vc = mul <vscale x 8 x i32> %va, %splat 597 ret <vscale x 8 x i32> %vc 598} 599 600define <vscale x 16 x i32> @vmul_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) { 601; CHECK-LABEL: vmul_vv_nxv16i32: 602; CHECK: # %bb.0: 603; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 604; CHECK-NEXT: vmul.vv v8, v8, v16 605; CHECK-NEXT: ret 606 %vc = mul <vscale x 16 x i32> %va, %vb 607 ret <vscale x 16 x i32> %vc 608} 609 610define <vscale x 16 x i32> @vmul_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) { 611; CHECK-LABEL: vmul_vx_nxv16i32: 612; CHECK: # %bb.0: 613; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu 614; CHECK-NEXT: vmul.vx v8, v8, a0 615; CHECK-NEXT: ret 616 %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0 617 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer 618 %vc = mul <vscale x 16 x i32> %va, %splat 619 ret <vscale x 16 x i32> %vc 620} 621 622define <vscale x 16 x i32> @vmul_vi_nxv16i32_0(<vscale x 16 x i32> %va) { 623; CHECK-LABEL: vmul_vi_nxv16i32_0: 624; CHECK: # %bb.0: 625; CHECK-NEXT: li a0, -7 626; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu 627; CHECK-NEXT: vmul.vx v8, v8, a0 628; CHECK-NEXT: ret 629 %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0 630 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer 631 %vc = mul <vscale x 16 x i32> %va, %splat 632 ret <vscale x 16 x i32> %vc 633} 634 635define <vscale x 1 x i64> @vmul_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) { 636; CHECK-LABEL: vmul_vv_nxv1i64: 637; CHECK: # %bb.0: 638; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 639; CHECK-NEXT: vmul.vv v8, v8, v9 640; CHECK-NEXT: ret 641 %vc = mul <vscale x 1 x i64> %va, %vb 642 ret <vscale x 1 x i64> %vc 643} 644 645define <vscale x 1 x i64> @vmul_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { 646; RV32-LABEL: vmul_vx_nxv1i64: 647; RV32: # %bb.0: 648; RV32-NEXT: addi sp, sp, -16 649; RV32-NEXT: .cfi_def_cfa_offset 16 650; RV32-NEXT: sw a1, 12(sp) 651; RV32-NEXT: sw a0, 8(sp) 652; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu 653; RV32-NEXT: addi a0, sp, 8 654; RV32-NEXT: vlse64.v v9, (a0), zero 655; RV32-NEXT: vmul.vv v8, v8, v9 656; RV32-NEXT: addi sp, sp, 16 657; RV32-NEXT: ret 658; 659; RV64-LABEL: vmul_vx_nxv1i64: 660; RV64: # %bb.0: 661; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu 662; RV64-NEXT: vmul.vx v8, v8, a0 663; RV64-NEXT: ret 664 %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0 665 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 666 %vc = mul <vscale x 1 x i64> %va, %splat 667 ret <vscale x 1 x i64> %vc 668} 669 670define <vscale x 1 x i64> @vmul_vi_nxv1i64_0(<vscale x 1 x i64> %va) { 671; CHECK-LABEL: vmul_vi_nxv1i64_0: 672; CHECK: # %bb.0: 673; CHECK-NEXT: li a0, -7 674; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu 675; CHECK-NEXT: vmul.vx v8, v8, a0 676; CHECK-NEXT: ret 677 %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0 678 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 679 %vc = mul <vscale x 1 x i64> %va, %splat 680 ret <vscale x 1 x i64> %vc 681} 682 683define <vscale x 1 x i64> @vmul_vi_nxv1i64_1(<vscale x 1 x i64> %va) { 684; CHECK-LABEL: vmul_vi_nxv1i64_1: 685; CHECK: # %bb.0: 686; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 687; CHECK-NEXT: vadd.vv v8, v8, v8 688; CHECK-NEXT: ret 689 %head = insertelement <vscale x 1 x i64> undef, i64 2, i32 0 690 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 691 %vc = mul <vscale x 1 x i64> %va, %splat 692 ret <vscale x 1 x i64> %vc 693} 694 695define <vscale x 1 x i64> @vmul_vi_nxv1i64_2(<vscale x 1 x i64> %va) { 696; CHECK-LABEL: vmul_vi_nxv1i64_2: 697; CHECK: # %bb.0: 698; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 699; CHECK-NEXT: vsll.vi v8, v8, 4 700; CHECK-NEXT: ret 701 %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0 702 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 703 %vc = mul <vscale x 1 x i64> %va, %splat 704 ret <vscale x 1 x i64> %vc 705} 706 707define <vscale x 2 x i64> @vmul_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) { 708; CHECK-LABEL: vmul_vv_nxv2i64: 709; CHECK: # %bb.0: 710; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 711; CHECK-NEXT: vmul.vv v8, v8, v10 712; CHECK-NEXT: ret 713 %vc = mul <vscale x 2 x i64> %va, %vb 714 ret <vscale x 2 x i64> %vc 715} 716 717define <vscale x 2 x i64> @vmul_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { 718; RV32-LABEL: vmul_vx_nxv2i64: 719; RV32: # %bb.0: 720; RV32-NEXT: addi sp, sp, -16 721; RV32-NEXT: .cfi_def_cfa_offset 16 722; RV32-NEXT: sw a1, 12(sp) 723; RV32-NEXT: sw a0, 8(sp) 724; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu 725; RV32-NEXT: addi a0, sp, 8 726; RV32-NEXT: vlse64.v v10, (a0), zero 727; RV32-NEXT: vmul.vv v8, v8, v10 728; RV32-NEXT: addi sp, sp, 16 729; RV32-NEXT: ret 730; 731; RV64-LABEL: vmul_vx_nxv2i64: 732; RV64: # %bb.0: 733; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu 734; RV64-NEXT: vmul.vx v8, v8, a0 735; RV64-NEXT: ret 736 %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0 737 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 738 %vc = mul <vscale x 2 x i64> %va, %splat 739 ret <vscale x 2 x i64> %vc 740} 741 742define <vscale x 2 x i64> @vmul_vi_nxv2i64_0(<vscale x 2 x i64> %va) { 743; CHECK-LABEL: vmul_vi_nxv2i64_0: 744; CHECK: # %bb.0: 745; CHECK-NEXT: li a0, -7 746; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu 747; CHECK-NEXT: vmul.vx v8, v8, a0 748; CHECK-NEXT: ret 749 %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0 750 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 751 %vc = mul <vscale x 2 x i64> %va, %splat 752 ret <vscale x 2 x i64> %vc 753} 754 755define <vscale x 2 x i64> @vmul_vi_nxv2i64_1(<vscale x 2 x i64> %va) { 756; CHECK-LABEL: vmul_vi_nxv2i64_1: 757; CHECK: # %bb.0: 758; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 759; CHECK-NEXT: vadd.vv v8, v8, v8 760; CHECK-NEXT: ret 761 %head = insertelement <vscale x 2 x i64> undef, i64 2, i32 0 762 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 763 %vc = mul <vscale x 2 x i64> %va, %splat 764 ret <vscale x 2 x i64> %vc 765} 766 767define <vscale x 2 x i64> @vmul_vi_nxv2i64_2(<vscale x 2 x i64> %va) { 768; CHECK-LABEL: vmul_vi_nxv2i64_2: 769; CHECK: # %bb.0: 770; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 771; CHECK-NEXT: vsll.vi v8, v8, 4 772; CHECK-NEXT: ret 773 %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0 774 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 775 %vc = mul <vscale x 2 x i64> %va, %splat 776 ret <vscale x 2 x i64> %vc 777} 778 779define <vscale x 4 x i64> @vmul_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) { 780; CHECK-LABEL: vmul_vv_nxv4i64: 781; CHECK: # %bb.0: 782; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 783; CHECK-NEXT: vmul.vv v8, v8, v12 784; CHECK-NEXT: ret 785 %vc = mul <vscale x 4 x i64> %va, %vb 786 ret <vscale x 4 x i64> %vc 787} 788 789define <vscale x 4 x i64> @vmul_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { 790; RV32-LABEL: vmul_vx_nxv4i64: 791; RV32: # %bb.0: 792; RV32-NEXT: addi sp, sp, -16 793; RV32-NEXT: .cfi_def_cfa_offset 16 794; RV32-NEXT: sw a1, 12(sp) 795; RV32-NEXT: sw a0, 8(sp) 796; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu 797; RV32-NEXT: addi a0, sp, 8 798; RV32-NEXT: vlse64.v v12, (a0), zero 799; RV32-NEXT: vmul.vv v8, v8, v12 800; RV32-NEXT: addi sp, sp, 16 801; RV32-NEXT: ret 802; 803; RV64-LABEL: vmul_vx_nxv4i64: 804; RV64: # %bb.0: 805; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu 806; RV64-NEXT: vmul.vx v8, v8, a0 807; RV64-NEXT: ret 808 %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0 809 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 810 %vc = mul <vscale x 4 x i64> %va, %splat 811 ret <vscale x 4 x i64> %vc 812} 813 814define <vscale x 4 x i64> @vmul_vi_nxv4i64_0(<vscale x 4 x i64> %va) { 815; CHECK-LABEL: vmul_vi_nxv4i64_0: 816; CHECK: # %bb.0: 817; CHECK-NEXT: li a0, -7 818; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu 819; CHECK-NEXT: vmul.vx v8, v8, a0 820; CHECK-NEXT: ret 821 %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0 822 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 823 %vc = mul <vscale x 4 x i64> %va, %splat 824 ret <vscale x 4 x i64> %vc 825} 826 827define <vscale x 4 x i64> @vmul_vi_nxv4i64_1(<vscale x 4 x i64> %va) { 828; CHECK-LABEL: vmul_vi_nxv4i64_1: 829; CHECK: # %bb.0: 830; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 831; CHECK-NEXT: vadd.vv v8, v8, v8 832; CHECK-NEXT: ret 833 %head = insertelement <vscale x 4 x i64> undef, i64 2, i32 0 834 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 835 %vc = mul <vscale x 4 x i64> %va, %splat 836 ret <vscale x 4 x i64> %vc 837} 838 839define <vscale x 4 x i64> @vmul_vi_nxv4i64_2(<vscale x 4 x i64> %va) { 840; CHECK-LABEL: vmul_vi_nxv4i64_2: 841; CHECK: # %bb.0: 842; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 843; CHECK-NEXT: vsll.vi v8, v8, 4 844; CHECK-NEXT: ret 845 %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0 846 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 847 %vc = mul <vscale x 4 x i64> %va, %splat 848 ret <vscale x 4 x i64> %vc 849} 850 851define <vscale x 8 x i64> @vmul_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 852; CHECK-LABEL: vmul_vv_nxv8i64: 853; CHECK: # %bb.0: 854; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 855; CHECK-NEXT: vmul.vv v8, v8, v16 856; CHECK-NEXT: ret 857 %vc = mul <vscale x 8 x i64> %va, %vb 858 ret <vscale x 8 x i64> %vc 859} 860 861define <vscale x 8 x i64> @vmul_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 862; RV32-LABEL: vmul_vx_nxv8i64: 863; RV32: # %bb.0: 864; RV32-NEXT: addi sp, sp, -16 865; RV32-NEXT: .cfi_def_cfa_offset 16 866; RV32-NEXT: sw a1, 12(sp) 867; RV32-NEXT: sw a0, 8(sp) 868; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 869; RV32-NEXT: addi a0, sp, 8 870; RV32-NEXT: vlse64.v v16, (a0), zero 871; RV32-NEXT: vmul.vv v8, v8, v16 872; RV32-NEXT: addi sp, sp, 16 873; RV32-NEXT: ret 874; 875; RV64-LABEL: vmul_vx_nxv8i64: 876; RV64: # %bb.0: 877; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 878; RV64-NEXT: vmul.vx v8, v8, a0 879; RV64-NEXT: ret 880 %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0 881 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 882 %vc = mul <vscale x 8 x i64> %va, %splat 883 ret <vscale x 8 x i64> %vc 884} 885 886define <vscale x 8 x i64> @vmul_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 887; CHECK-LABEL: vmul_vi_nxv8i64_0: 888; CHECK: # %bb.0: 889; CHECK-NEXT: li a0, -7 890; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu 891; CHECK-NEXT: vmul.vx v8, v8, a0 892; CHECK-NEXT: ret 893 %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0 894 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 895 %vc = mul <vscale x 8 x i64> %va, %splat 896 ret <vscale x 8 x i64> %vc 897} 898 899define <vscale x 8 x i64> @vmul_vi_nxv8i64_1(<vscale x 8 x i64> %va) { 900; CHECK-LABEL: vmul_vi_nxv8i64_1: 901; CHECK: # %bb.0: 902; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 903; CHECK-NEXT: vadd.vv v8, v8, v8 904; CHECK-NEXT: ret 905 %head = insertelement <vscale x 8 x i64> undef, i64 2, i32 0 906 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 907 %vc = mul <vscale x 8 x i64> %va, %splat 908 ret <vscale x 8 x i64> %vc 909} 910 911define <vscale x 8 x i64> @vmul_vi_nxv8i64_2(<vscale x 8 x i64> %va) { 912; CHECK-LABEL: vmul_vi_nxv8i64_2: 913; CHECK: # %bb.0: 914; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 915; CHECK-NEXT: vsll.vi v8, v8, 4 916; CHECK-NEXT: ret 917 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 918 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 919 %vc = mul <vscale x 8 x i64> %va, %splat 920 ret <vscale x 8 x i64> %vc 921} 922