1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \
3; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
5; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
6declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
7  <vscale x 1 x half>,
8  <vscale x 1 x half>,
9  iXLen);
10
11define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
12; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16:
13; CHECK:       # %bb.0: # %entry
14; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
15; CHECK-NEXT:    vmfle.vv v0, v8, v9
16; CHECK-NEXT:    ret
17entry:
18  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
19    <vscale x 1 x half> %0,
20    <vscale x 1 x half> %1,
21    iXLen %2)
22
23  ret <vscale x 1 x i1> %a
24}
25
26declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
27  <vscale x 1 x i1>,
28  <vscale x 1 x half>,
29  <vscale x 1 x half>,
30  <vscale x 1 x i1>,
31  iXLen);
32
33define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
34; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16:
35; CHECK:       # %bb.0: # %entry
36; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
37; CHECK-NEXT:    vmfle.vv v8, v8, v9
38; CHECK-NEXT:    vmv1r.v v11, v0
39; CHECK-NEXT:    vmv1r.v v0, v8
40; CHECK-NEXT:    vmfle.vv v11, v9, v10, v0.t
41; CHECK-NEXT:    vmv1r.v v0, v11
42; CHECK-NEXT:    ret
43entry:
44  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
45    <vscale x 1 x half> %1,
46    <vscale x 1 x half> %2,
47    iXLen %4)
48  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
49    <vscale x 1 x i1> %0,
50    <vscale x 1 x half> %2,
51    <vscale x 1 x half> %3,
52    <vscale x 1 x i1> %mask,
53    iXLen %4)
54
55  ret <vscale x 1 x i1> %a
56}
57
58declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
59  <vscale x 2 x half>,
60  <vscale x 2 x half>,
61  iXLen);
62
63define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {
64; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f16_nxv2f16:
65; CHECK:       # %bb.0: # %entry
66; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
67; CHECK-NEXT:    vmfle.vv v0, v8, v9
68; CHECK-NEXT:    ret
69entry:
70  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
71    <vscale x 2 x half> %0,
72    <vscale x 2 x half> %1,
73    iXLen %2)
74
75  ret <vscale x 2 x i1> %a
76}
77
78declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
79  <vscale x 2 x i1>,
80  <vscale x 2 x half>,
81  <vscale x 2 x half>,
82  <vscale x 2 x i1>,
83  iXLen);
84
85define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
86; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16:
87; CHECK:       # %bb.0: # %entry
88; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
89; CHECK-NEXT:    vmfle.vv v8, v8, v9
90; CHECK-NEXT:    vmv1r.v v11, v0
91; CHECK-NEXT:    vmv1r.v v0, v8
92; CHECK-NEXT:    vmfle.vv v11, v9, v10, v0.t
93; CHECK-NEXT:    vmv1r.v v0, v11
94; CHECK-NEXT:    ret
95entry:
96  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
97    <vscale x 2 x half> %1,
98    <vscale x 2 x half> %2,
99    iXLen %4)
100  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
101    <vscale x 2 x i1> %0,
102    <vscale x 2 x half> %2,
103    <vscale x 2 x half> %3,
104    <vscale x 2 x i1> %mask,
105    iXLen %4)
106
107  ret <vscale x 2 x i1> %a
108}
109
110declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
111  <vscale x 4 x half>,
112  <vscale x 4 x half>,
113  iXLen);
114
115define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {
116; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f16_nxv4f16:
117; CHECK:       # %bb.0: # %entry
118; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
119; CHECK-NEXT:    vmfle.vv v0, v8, v9
120; CHECK-NEXT:    ret
121entry:
122  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
123    <vscale x 4 x half> %0,
124    <vscale x 4 x half> %1,
125    iXLen %2)
126
127  ret <vscale x 4 x i1> %a
128}
129
130declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
131  <vscale x 4 x i1>,
132  <vscale x 4 x half>,
133  <vscale x 4 x half>,
134  <vscale x 4 x i1>,
135  iXLen);
136
137define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
138; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16:
139; CHECK:       # %bb.0: # %entry
140; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
141; CHECK-NEXT:    vmfle.vv v8, v8, v9
142; CHECK-NEXT:    vmv1r.v v11, v0
143; CHECK-NEXT:    vmv.v.v v0, v8
144; CHECK-NEXT:    vmfle.vv v11, v9, v10, v0.t
145; CHECK-NEXT:    vmv.v.v v0, v11
146; CHECK-NEXT:    ret
147entry:
148  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
149    <vscale x 4 x half> %1,
150    <vscale x 4 x half> %2,
151    iXLen %4)
152  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
153    <vscale x 4 x i1> %0,
154    <vscale x 4 x half> %2,
155    <vscale x 4 x half> %3,
156    <vscale x 4 x i1> %mask,
157    iXLen %4)
158
159  ret <vscale x 4 x i1> %a
160}
161
162declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
163  <vscale x 8 x half>,
164  <vscale x 8 x half>,
165  iXLen);
166
167define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {
168; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f16_nxv8f16:
169; CHECK:       # %bb.0: # %entry
170; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
171; CHECK-NEXT:    vmfle.vv v0, v8, v10
172; CHECK-NEXT:    ret
173entry:
174  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
175    <vscale x 8 x half> %0,
176    <vscale x 8 x half> %1,
177    iXLen %2)
178
179  ret <vscale x 8 x i1> %a
180}
181
182declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
183  <vscale x 8 x i1>,
184  <vscale x 8 x half>,
185  <vscale x 8 x half>,
186  <vscale x 8 x i1>,
187  iXLen);
188
189define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
190; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16:
191; CHECK:       # %bb.0: # %entry
192; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
193; CHECK-NEXT:    vmfle.vv v14, v8, v10
194; CHECK-NEXT:    vmv1r.v v8, v0
195; CHECK-NEXT:    vmv1r.v v0, v14
196; CHECK-NEXT:    vmfle.vv v8, v10, v12, v0.t
197; CHECK-NEXT:    vmv1r.v v0, v8
198; CHECK-NEXT:    ret
199entry:
200  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
201    <vscale x 8 x half> %1,
202    <vscale x 8 x half> %2,
203    iXLen %4)
204  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
205    <vscale x 8 x i1> %0,
206    <vscale x 8 x half> %2,
207    <vscale x 8 x half> %3,
208    <vscale x 8 x i1> %mask,
209    iXLen %4)
210
211  ret <vscale x 8 x i1> %a
212}
213
214declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
215  <vscale x 16 x half>,
216  <vscale x 16 x half>,
217  iXLen);
218
219define <vscale x 16 x i1> @intrinsic_vmfle_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {
220; CHECK-LABEL: intrinsic_vmfle_vv_nxv16f16_nxv16f16:
221; CHECK:       # %bb.0: # %entry
222; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu
223; CHECK-NEXT:    vmfle.vv v0, v8, v12
224; CHECK-NEXT:    ret
225entry:
226  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
227    <vscale x 16 x half> %0,
228    <vscale x 16 x half> %1,
229    iXLen %2)
230
231  ret <vscale x 16 x i1> %a
232}
233
234declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
235  <vscale x 16 x i1>,
236  <vscale x 16 x half>,
237  <vscale x 16 x half>,
238  <vscale x 16 x i1>,
239  iXLen);
240
241define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
242; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16:
243; CHECK:       # %bb.0: # %entry
244; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu
245; CHECK-NEXT:    vmfle.vv v20, v8, v12
246; CHECK-NEXT:    vmv1r.v v8, v0
247; CHECK-NEXT:    vmv1r.v v0, v20
248; CHECK-NEXT:    vmfle.vv v8, v12, v16, v0.t
249; CHECK-NEXT:    vmv1r.v v0, v8
250; CHECK-NEXT:    ret
251entry:
252  %mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
253    <vscale x 16 x half> %1,
254    <vscale x 16 x half> %2,
255    iXLen %4)
256  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
257    <vscale x 16 x i1> %0,
258    <vscale x 16 x half> %2,
259    <vscale x 16 x half> %3,
260    <vscale x 16 x i1> %mask,
261    iXLen %4)
262
263  ret <vscale x 16 x i1> %a
264}
265
266declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
267  <vscale x 1 x float>,
268  <vscale x 1 x float>,
269  iXLen);
270
271define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {
272; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f32_nxv1f32:
273; CHECK:       # %bb.0: # %entry
274; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
275; CHECK-NEXT:    vmfle.vv v0, v8, v9
276; CHECK-NEXT:    ret
277entry:
278  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
279    <vscale x 1 x float> %0,
280    <vscale x 1 x float> %1,
281    iXLen %2)
282
283  ret <vscale x 1 x i1> %a
284}
285
286declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
287  <vscale x 1 x i1>,
288  <vscale x 1 x float>,
289  <vscale x 1 x float>,
290  <vscale x 1 x i1>,
291  iXLen);
292
293define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
294; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32:
295; CHECK:       # %bb.0: # %entry
296; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
297; CHECK-NEXT:    vmfle.vv v8, v8, v9
298; CHECK-NEXT:    vmv1r.v v11, v0
299; CHECK-NEXT:    vmv1r.v v0, v8
300; CHECK-NEXT:    vmfle.vv v11, v9, v10, v0.t
301; CHECK-NEXT:    vmv1r.v v0, v11
302; CHECK-NEXT:    ret
303entry:
304  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
305    <vscale x 1 x float> %1,
306    <vscale x 1 x float> %2,
307    iXLen %4)
308  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
309    <vscale x 1 x i1> %0,
310    <vscale x 1 x float> %2,
311    <vscale x 1 x float> %3,
312    <vscale x 1 x i1> %mask,
313    iXLen %4)
314
315  ret <vscale x 1 x i1> %a
316}
317
318declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
319  <vscale x 2 x float>,
320  <vscale x 2 x float>,
321  iXLen);
322
323define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {
324; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f32_nxv2f32:
325; CHECK:       # %bb.0: # %entry
326; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
327; CHECK-NEXT:    vmfle.vv v0, v8, v9
328; CHECK-NEXT:    ret
329entry:
330  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
331    <vscale x 2 x float> %0,
332    <vscale x 2 x float> %1,
333    iXLen %2)
334
335  ret <vscale x 2 x i1> %a
336}
337
338declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
339  <vscale x 2 x i1>,
340  <vscale x 2 x float>,
341  <vscale x 2 x float>,
342  <vscale x 2 x i1>,
343  iXLen);
344
345define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
346; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32:
347; CHECK:       # %bb.0: # %entry
348; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
349; CHECK-NEXT:    vmfle.vv v8, v8, v9
350; CHECK-NEXT:    vmv1r.v v11, v0
351; CHECK-NEXT:    vmv.v.v v0, v8
352; CHECK-NEXT:    vmfle.vv v11, v9, v10, v0.t
353; CHECK-NEXT:    vmv.v.v v0, v11
354; CHECK-NEXT:    ret
355entry:
356  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
357    <vscale x 2 x float> %1,
358    <vscale x 2 x float> %2,
359    iXLen %4)
360  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
361    <vscale x 2 x i1> %0,
362    <vscale x 2 x float> %2,
363    <vscale x 2 x float> %3,
364    <vscale x 2 x i1> %mask,
365    iXLen %4)
366
367  ret <vscale x 2 x i1> %a
368}
369
370declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
371  <vscale x 4 x float>,
372  <vscale x 4 x float>,
373  iXLen);
374
375define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {
376; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f32_nxv4f32:
377; CHECK:       # %bb.0: # %entry
378; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
379; CHECK-NEXT:    vmfle.vv v0, v8, v10
380; CHECK-NEXT:    ret
381entry:
382  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
383    <vscale x 4 x float> %0,
384    <vscale x 4 x float> %1,
385    iXLen %2)
386
387  ret <vscale x 4 x i1> %a
388}
389
390declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
391  <vscale x 4 x i1>,
392  <vscale x 4 x float>,
393  <vscale x 4 x float>,
394  <vscale x 4 x i1>,
395  iXLen);
396
397define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
398; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32:
399; CHECK:       # %bb.0: # %entry
400; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
401; CHECK-NEXT:    vmfle.vv v14, v8, v10
402; CHECK-NEXT:    vmv1r.v v8, v0
403; CHECK-NEXT:    vmv1r.v v0, v14
404; CHECK-NEXT:    vmfle.vv v8, v10, v12, v0.t
405; CHECK-NEXT:    vmv1r.v v0, v8
406; CHECK-NEXT:    ret
407entry:
408  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
409    <vscale x 4 x float> %1,
410    <vscale x 4 x float> %2,
411    iXLen %4)
412  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
413    <vscale x 4 x i1> %0,
414    <vscale x 4 x float> %2,
415    <vscale x 4 x float> %3,
416    <vscale x 4 x i1> %mask,
417    iXLen %4)
418
419  ret <vscale x 4 x i1> %a
420}
421
422declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
423  <vscale x 8 x float>,
424  <vscale x 8 x float>,
425  iXLen);
426
427define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {
428; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f32_nxv8f32:
429; CHECK:       # %bb.0: # %entry
430; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
431; CHECK-NEXT:    vmfle.vv v0, v8, v12
432; CHECK-NEXT:    ret
433entry:
434  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
435    <vscale x 8 x float> %0,
436    <vscale x 8 x float> %1,
437    iXLen %2)
438
439  ret <vscale x 8 x i1> %a
440}
441
442declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
443  <vscale x 8 x i1>,
444  <vscale x 8 x float>,
445  <vscale x 8 x float>,
446  <vscale x 8 x i1>,
447  iXLen);
448
449define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
450; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32:
451; CHECK:       # %bb.0: # %entry
452; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
453; CHECK-NEXT:    vmfle.vv v20, v8, v12
454; CHECK-NEXT:    vmv1r.v v8, v0
455; CHECK-NEXT:    vmv1r.v v0, v20
456; CHECK-NEXT:    vmfle.vv v8, v12, v16, v0.t
457; CHECK-NEXT:    vmv1r.v v0, v8
458; CHECK-NEXT:    ret
459entry:
460  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
461    <vscale x 8 x float> %1,
462    <vscale x 8 x float> %2,
463    iXLen %4)
464  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
465    <vscale x 8 x i1> %0,
466    <vscale x 8 x float> %2,
467    <vscale x 8 x float> %3,
468    <vscale x 8 x i1> %mask,
469    iXLen %4)
470
471  ret <vscale x 8 x i1> %a
472}
473
474declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
475  <vscale x 1 x double>,
476  <vscale x 1 x double>,
477  iXLen);
478
479define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {
480; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f64_nxv1f64:
481; CHECK:       # %bb.0: # %entry
482; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
483; CHECK-NEXT:    vmfle.vv v0, v8, v9
484; CHECK-NEXT:    ret
485entry:
486  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
487    <vscale x 1 x double> %0,
488    <vscale x 1 x double> %1,
489    iXLen %2)
490
491  ret <vscale x 1 x i1> %a
492}
493
494declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
495  <vscale x 1 x i1>,
496  <vscale x 1 x double>,
497  <vscale x 1 x double>,
498  <vscale x 1 x i1>,
499  iXLen);
500
501define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
502; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64:
503; CHECK:       # %bb.0: # %entry
504; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
505; CHECK-NEXT:    vmfle.vv v8, v8, v9
506; CHECK-NEXT:    vmv1r.v v11, v0
507; CHECK-NEXT:    vmv.v.v v0, v8
508; CHECK-NEXT:    vmfle.vv v11, v9, v10, v0.t
509; CHECK-NEXT:    vmv.v.v v0, v11
510; CHECK-NEXT:    ret
511entry:
512  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
513    <vscale x 1 x double> %1,
514    <vscale x 1 x double> %2,
515    iXLen %4)
516  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
517    <vscale x 1 x i1> %0,
518    <vscale x 1 x double> %2,
519    <vscale x 1 x double> %3,
520    <vscale x 1 x i1> %mask,
521    iXLen %4)
522
523  ret <vscale x 1 x i1> %a
524}
525
526declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
527  <vscale x 2 x double>,
528  <vscale x 2 x double>,
529  iXLen);
530
531define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {
532; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f64_nxv2f64:
533; CHECK:       # %bb.0: # %entry
534; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
535; CHECK-NEXT:    vmfle.vv v0, v8, v10
536; CHECK-NEXT:    ret
537entry:
538  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
539    <vscale x 2 x double> %0,
540    <vscale x 2 x double> %1,
541    iXLen %2)
542
543  ret <vscale x 2 x i1> %a
544}
545
546declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
547  <vscale x 2 x i1>,
548  <vscale x 2 x double>,
549  <vscale x 2 x double>,
550  <vscale x 2 x i1>,
551  iXLen);
552
553define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
554; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64:
555; CHECK:       # %bb.0: # %entry
556; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
557; CHECK-NEXT:    vmfle.vv v14, v8, v10
558; CHECK-NEXT:    vmv1r.v v8, v0
559; CHECK-NEXT:    vmv1r.v v0, v14
560; CHECK-NEXT:    vmfle.vv v8, v10, v12, v0.t
561; CHECK-NEXT:    vmv1r.v v0, v8
562; CHECK-NEXT:    ret
563entry:
564  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
565    <vscale x 2 x double> %1,
566    <vscale x 2 x double> %2,
567    iXLen %4)
568  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
569    <vscale x 2 x i1> %0,
570    <vscale x 2 x double> %2,
571    <vscale x 2 x double> %3,
572    <vscale x 2 x i1> %mask,
573    iXLen %4)
574
575  ret <vscale x 2 x i1> %a
576}
577
578declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
579  <vscale x 4 x double>,
580  <vscale x 4 x double>,
581  iXLen);
582
583define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {
584; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f64_nxv4f64:
585; CHECK:       # %bb.0: # %entry
586; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
587; CHECK-NEXT:    vmfle.vv v0, v8, v12
588; CHECK-NEXT:    ret
589entry:
590  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
591    <vscale x 4 x double> %0,
592    <vscale x 4 x double> %1,
593    iXLen %2)
594
595  ret <vscale x 4 x i1> %a
596}
597
598declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
599  <vscale x 4 x i1>,
600  <vscale x 4 x double>,
601  <vscale x 4 x double>,
602  <vscale x 4 x i1>,
603  iXLen);
604
605define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
606; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64:
607; CHECK:       # %bb.0: # %entry
608; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
609; CHECK-NEXT:    vmfle.vv v20, v8, v12
610; CHECK-NEXT:    vmv1r.v v8, v0
611; CHECK-NEXT:    vmv1r.v v0, v20
612; CHECK-NEXT:    vmfle.vv v8, v12, v16, v0.t
613; CHECK-NEXT:    vmv1r.v v0, v8
614; CHECK-NEXT:    ret
615entry:
616  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
617    <vscale x 4 x double> %1,
618    <vscale x 4 x double> %2,
619    iXLen %4)
620  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
621    <vscale x 4 x i1> %0,
622    <vscale x 4 x double> %2,
623    <vscale x 4 x double> %3,
624    <vscale x 4 x i1> %mask,
625    iXLen %4)
626
627  ret <vscale x 4 x i1> %a
628}
629
630declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
631  <vscale x 1 x half>,
632  half,
633  iXLen);
634
635define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {
636; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16:
637; CHECK:       # %bb.0: # %entry
638; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
639; CHECK-NEXT:    vmfle.vf v0, v8, fa0
640; CHECK-NEXT:    ret
641entry:
642  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
643    <vscale x 1 x half> %0,
644    half %1,
645    iXLen %2)
646
647  ret <vscale x 1 x i1> %a
648}
649
650declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
651  <vscale x 1 x i1>,
652  <vscale x 1 x half>,
653  half,
654  <vscale x 1 x i1>,
655  iXLen);
656
657define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
658; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16:
659; CHECK:       # %bb.0: # %entry
660; CHECK-NEXT:    vmv1r.v v10, v0
661; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
662; CHECK-NEXT:    vmv1r.v v0, v9
663; CHECK-NEXT:    vmfle.vf v10, v8, fa0, v0.t
664; CHECK-NEXT:    vmv1r.v v0, v10
665; CHECK-NEXT:    ret
666entry:
667  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
668    <vscale x 1 x i1> %0,
669    <vscale x 1 x half> %1,
670    half %2,
671    <vscale x 1 x i1> %3,
672    iXLen %4)
673
674  ret <vscale x 1 x i1> %a
675}
676
677declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
678  <vscale x 2 x half>,
679  half,
680  iXLen);
681
682define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {
683; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16:
684; CHECK:       # %bb.0: # %entry
685; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
686; CHECK-NEXT:    vmfle.vf v0, v8, fa0
687; CHECK-NEXT:    ret
688entry:
689  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
690    <vscale x 2 x half> %0,
691    half %1,
692    iXLen %2)
693
694  ret <vscale x 2 x i1> %a
695}
696
697declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
698  <vscale x 2 x i1>,
699  <vscale x 2 x half>,
700  half,
701  <vscale x 2 x i1>,
702  iXLen);
703
704define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
705; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16:
706; CHECK:       # %bb.0: # %entry
707; CHECK-NEXT:    vmv1r.v v10, v0
708; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
709; CHECK-NEXT:    vmv1r.v v0, v9
710; CHECK-NEXT:    vmfle.vf v10, v8, fa0, v0.t
711; CHECK-NEXT:    vmv1r.v v0, v10
712; CHECK-NEXT:    ret
713entry:
714  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
715    <vscale x 2 x i1> %0,
716    <vscale x 2 x half> %1,
717    half %2,
718    <vscale x 2 x i1> %3,
719    iXLen %4)
720
721  ret <vscale x 2 x i1> %a
722}
723
724declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
725  <vscale x 4 x half>,
726  half,
727  iXLen);
728
729define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {
730; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16:
731; CHECK:       # %bb.0: # %entry
732; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
733; CHECK-NEXT:    vmfle.vf v0, v8, fa0
734; CHECK-NEXT:    ret
735entry:
736  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
737    <vscale x 4 x half> %0,
738    half %1,
739    iXLen %2)
740
741  ret <vscale x 4 x i1> %a
742}
743
744declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
745  <vscale x 4 x i1>,
746  <vscale x 4 x half>,
747  half,
748  <vscale x 4 x i1>,
749  iXLen);
750
751define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
752; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16:
753; CHECK:       # %bb.0: # %entry
754; CHECK-NEXT:    vmv1r.v v10, v0
755; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
756; CHECK-NEXT:    vmv1r.v v0, v9
757; CHECK-NEXT:    vmfle.vf v10, v8, fa0, v0.t
758; CHECK-NEXT:    vmv.v.v v0, v10
759; CHECK-NEXT:    ret
760entry:
761  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
762    <vscale x 4 x i1> %0,
763    <vscale x 4 x half> %1,
764    half %2,
765    <vscale x 4 x i1> %3,
766    iXLen %4)
767
768  ret <vscale x 4 x i1> %a
769}
770
771declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
772  <vscale x 8 x half>,
773  half,
774  iXLen);
775
776define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {
777; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16:
778; CHECK:       # %bb.0: # %entry
779; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
780; CHECK-NEXT:    vmfle.vf v0, v8, fa0
781; CHECK-NEXT:    ret
782entry:
783  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
784    <vscale x 8 x half> %0,
785    half %1,
786    iXLen %2)
787
788  ret <vscale x 8 x i1> %a
789}
790
791declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
792  <vscale x 8 x i1>,
793  <vscale x 8 x half>,
794  half,
795  <vscale x 8 x i1>,
796  iXLen);
797
798define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
799; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16:
800; CHECK:       # %bb.0: # %entry
801; CHECK-NEXT:    vmv1r.v v11, v0
802; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
803; CHECK-NEXT:    vmv1r.v v0, v10
804; CHECK-NEXT:    vmfle.vf v11, v8, fa0, v0.t
805; CHECK-NEXT:    vmv1r.v v0, v11
806; CHECK-NEXT:    ret
807entry:
808  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
809    <vscale x 8 x i1> %0,
810    <vscale x 8 x half> %1,
811    half %2,
812    <vscale x 8 x i1> %3,
813    iXLen %4)
814
815  ret <vscale x 8 x i1> %a
816}
817
818declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
819  <vscale x 16 x half>,
820  half,
821  iXLen);
822
823define <vscale x 16 x i1> @intrinsic_vmfle_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {
824; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16:
825; CHECK:       # %bb.0: # %entry
826; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu
827; CHECK-NEXT:    vmfle.vf v0, v8, fa0
828; CHECK-NEXT:    ret
829entry:
830  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
831    <vscale x 16 x half> %0,
832    half %1,
833    iXLen %2)
834
835  ret <vscale x 16 x i1> %a
836}
837
838declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
839  <vscale x 16 x i1>,
840  <vscale x 16 x half>,
841  half,
842  <vscale x 16 x i1>,
843  iXLen);
844
845define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
846; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16:
847; CHECK:       # %bb.0: # %entry
848; CHECK-NEXT:    vmv1r.v v13, v0
849; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu
850; CHECK-NEXT:    vmv1r.v v0, v12
851; CHECK-NEXT:    vmfle.vf v13, v8, fa0, v0.t
852; CHECK-NEXT:    vmv1r.v v0, v13
853; CHECK-NEXT:    ret
854entry:
855  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
856    <vscale x 16 x i1> %0,
857    <vscale x 16 x half> %1,
858    half %2,
859    <vscale x 16 x i1> %3,
860    iXLen %4)
861
862  ret <vscale x 16 x i1> %a
863}
864
865declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
866  <vscale x 1 x float>,
867  float,
868  iXLen);
869
870define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
871; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32:
872; CHECK:       # %bb.0: # %entry
873; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
874; CHECK-NEXT:    vmfle.vf v0, v8, fa0
875; CHECK-NEXT:    ret
876entry:
877  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
878    <vscale x 1 x float> %0,
879    float %1,
880    iXLen %2)
881
882  ret <vscale x 1 x i1> %a
883}
884
885declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
886  <vscale x 1 x i1>,
887  <vscale x 1 x float>,
888  float,
889  <vscale x 1 x i1>,
890  iXLen);
891
892define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
893; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32:
894; CHECK:       # %bb.0: # %entry
895; CHECK-NEXT:    vmv1r.v v10, v0
896; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
897; CHECK-NEXT:    vmv1r.v v0, v9
898; CHECK-NEXT:    vmfle.vf v10, v8, fa0, v0.t
899; CHECK-NEXT:    vmv1r.v v0, v10
900; CHECK-NEXT:    ret
901entry:
902  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
903    <vscale x 1 x i1> %0,
904    <vscale x 1 x float> %1,
905    float %2,
906    <vscale x 1 x i1> %3,
907    iXLen %4)
908
909  ret <vscale x 1 x i1> %a
910}
911
912declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
913  <vscale x 2 x float>,
914  float,
915  iXLen);
916
917define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {
918; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32:
919; CHECK:       # %bb.0: # %entry
920; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
921; CHECK-NEXT:    vmfle.vf v0, v8, fa0
922; CHECK-NEXT:    ret
923entry:
924  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
925    <vscale x 2 x float> %0,
926    float %1,
927    iXLen %2)
928
929  ret <vscale x 2 x i1> %a
930}
931
932declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
933  <vscale x 2 x i1>,
934  <vscale x 2 x float>,
935  float,
936  <vscale x 2 x i1>,
937  iXLen);
938
939define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
940; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32:
941; CHECK:       # %bb.0: # %entry
942; CHECK-NEXT:    vmv1r.v v10, v0
943; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
944; CHECK-NEXT:    vmv1r.v v0, v9
945; CHECK-NEXT:    vmfle.vf v10, v8, fa0, v0.t
946; CHECK-NEXT:    vmv.v.v v0, v10
947; CHECK-NEXT:    ret
948entry:
949  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
950    <vscale x 2 x i1> %0,
951    <vscale x 2 x float> %1,
952    float %2,
953    <vscale x 2 x i1> %3,
954    iXLen %4)
955
956  ret <vscale x 2 x i1> %a
957}
958
959declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
960  <vscale x 4 x float>,
961  float,
962  iXLen);
963
964define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {
965; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32:
966; CHECK:       # %bb.0: # %entry
967; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
968; CHECK-NEXT:    vmfle.vf v0, v8, fa0
969; CHECK-NEXT:    ret
970entry:
971  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
972    <vscale x 4 x float> %0,
973    float %1,
974    iXLen %2)
975
976  ret <vscale x 4 x i1> %a
977}
978
979declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
980  <vscale x 4 x i1>,
981  <vscale x 4 x float>,
982  float,
983  <vscale x 4 x i1>,
984  iXLen);
985
986define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
987; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32:
988; CHECK:       # %bb.0: # %entry
989; CHECK-NEXT:    vmv1r.v v11, v0
990; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
991; CHECK-NEXT:    vmv1r.v v0, v10
992; CHECK-NEXT:    vmfle.vf v11, v8, fa0, v0.t
993; CHECK-NEXT:    vmv1r.v v0, v11
994; CHECK-NEXT:    ret
995entry:
996  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
997    <vscale x 4 x i1> %0,
998    <vscale x 4 x float> %1,
999    float %2,
1000    <vscale x 4 x i1> %3,
1001    iXLen %4)
1002
1003  ret <vscale x 4 x i1> %a
1004}
1005
1006declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
1007  <vscale x 8 x float>,
1008  float,
1009  iXLen);
1010
1011define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {
1012; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32:
1013; CHECK:       # %bb.0: # %entry
1014; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
1015; CHECK-NEXT:    vmfle.vf v0, v8, fa0
1016; CHECK-NEXT:    ret
1017entry:
1018  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
1019    <vscale x 8 x float> %0,
1020    float %1,
1021    iXLen %2)
1022
1023  ret <vscale x 8 x i1> %a
1024}
1025
1026declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
1027  <vscale x 8 x i1>,
1028  <vscale x 8 x float>,
1029  float,
1030  <vscale x 8 x i1>,
1031  iXLen);
1032
1033define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
1034; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32:
1035; CHECK:       # %bb.0: # %entry
1036; CHECK-NEXT:    vmv1r.v v13, v0
1037; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
1038; CHECK-NEXT:    vmv1r.v v0, v12
1039; CHECK-NEXT:    vmfle.vf v13, v8, fa0, v0.t
1040; CHECK-NEXT:    vmv1r.v v0, v13
1041; CHECK-NEXT:    ret
1042entry:
1043  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
1044    <vscale x 8 x i1> %0,
1045    <vscale x 8 x float> %1,
1046    float %2,
1047    <vscale x 8 x i1> %3,
1048    iXLen %4)
1049
1050  ret <vscale x 8 x i1> %a
1051}
1052
1053declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
1054  <vscale x 1 x double>,
1055  double,
1056  iXLen);
1057
1058define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {
1059; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f64_f64:
1060; CHECK:       # %bb.0: # %entry
1061; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
1062; CHECK-NEXT:    vmfle.vf v0, v8, fa0
1063; CHECK-NEXT:    ret
1064entry:
1065  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
1066    <vscale x 1 x double> %0,
1067    double %1,
1068    iXLen %2)
1069
1070  ret <vscale x 1 x i1> %a
1071}
1072
1073declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
1074  <vscale x 1 x i1>,
1075  <vscale x 1 x double>,
1076  double,
1077  <vscale x 1 x i1>,
1078  iXLen);
1079
1080define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
1081; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64:
1082; CHECK:       # %bb.0: # %entry
1083; CHECK-NEXT:    vmv1r.v v10, v0
1084; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
1085; CHECK-NEXT:    vmv1r.v v0, v9
1086; CHECK-NEXT:    vmfle.vf v10, v8, fa0, v0.t
1087; CHECK-NEXT:    vmv.v.v v0, v10
1088; CHECK-NEXT:    ret
1089entry:
1090  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
1091    <vscale x 1 x i1> %0,
1092    <vscale x 1 x double> %1,
1093    double %2,
1094    <vscale x 1 x i1> %3,
1095    iXLen %4)
1096
1097  ret <vscale x 1 x i1> %a
1098}
1099
1100declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
1101  <vscale x 2 x double>,
1102  double,
1103  iXLen);
1104
1105define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {
1106; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f64_f64:
1107; CHECK:       # %bb.0: # %entry
1108; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
1109; CHECK-NEXT:    vmfle.vf v0, v8, fa0
1110; CHECK-NEXT:    ret
1111entry:
1112  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
1113    <vscale x 2 x double> %0,
1114    double %1,
1115    iXLen %2)
1116
1117  ret <vscale x 2 x i1> %a
1118}
1119
1120declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
1121  <vscale x 2 x i1>,
1122  <vscale x 2 x double>,
1123  double,
1124  <vscale x 2 x i1>,
1125  iXLen);
1126
1127define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
1128; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64:
1129; CHECK:       # %bb.0: # %entry
1130; CHECK-NEXT:    vmv1r.v v11, v0
1131; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
1132; CHECK-NEXT:    vmv1r.v v0, v10
1133; CHECK-NEXT:    vmfle.vf v11, v8, fa0, v0.t
1134; CHECK-NEXT:    vmv1r.v v0, v11
1135; CHECK-NEXT:    ret
1136entry:
1137  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
1138    <vscale x 2 x i1> %0,
1139    <vscale x 2 x double> %1,
1140    double %2,
1141    <vscale x 2 x i1> %3,
1142    iXLen %4)
1143
1144  ret <vscale x 2 x i1> %a
1145}
1146
1147declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
1148  <vscale x 4 x double>,
1149  double,
1150  iXLen);
1151
1152define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {
1153; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f64_f64:
1154; CHECK:       # %bb.0: # %entry
1155; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
1156; CHECK-NEXT:    vmfle.vf v0, v8, fa0
1157; CHECK-NEXT:    ret
1158entry:
1159  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
1160    <vscale x 4 x double> %0,
1161    double %1,
1162    iXLen %2)
1163
1164  ret <vscale x 4 x i1> %a
1165}
1166
1167declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
1168  <vscale x 4 x i1>,
1169  <vscale x 4 x double>,
1170  double,
1171  <vscale x 4 x i1>,
1172  iXLen);
1173
1174define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
1175; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64:
1176; CHECK:       # %bb.0: # %entry
1177; CHECK-NEXT:    vmv1r.v v13, v0
1178; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
1179; CHECK-NEXT:    vmv1r.v v0, v12
1180; CHECK-NEXT:    vmfle.vf v13, v8, fa0, v0.t
1181; CHECK-NEXT:    vmv1r.v v0, v13
1182; CHECK-NEXT:    ret
1183entry:
1184  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
1185    <vscale x 4 x i1> %0,
1186    <vscale x 4 x double> %1,
1187    double %2,
1188    <vscale x 4 x i1> %3,
1189    iXLen %4)
1190
1191  ret <vscale x 4 x i1> %a
1192}
1193