1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 1 x i8> @vmax_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
6; CHECK-LABEL: vmax_vv_nxv1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
9; CHECK-NEXT:    vmax.vv v8, v8, v9
10; CHECK-NEXT:    ret
11  %cmp = icmp sgt <vscale x 1 x i8> %va, %vb
12  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb
13  ret <vscale x 1 x i8> %vc
14}
15
16define <vscale x 1 x i8> @vmax_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
17; CHECK-LABEL: vmax_vx_nxv1i8:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
20; CHECK-NEXT:    vmax.vx v8, v8, a0
21; CHECK-NEXT:    ret
22  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
23  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
24  %cmp = icmp sgt <vscale x 1 x i8> %va, %splat
25  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
26  ret <vscale x 1 x i8> %vc
27}
28
29define <vscale x 1 x i8> @vmax_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
30; CHECK-LABEL: vmax_vi_nxv1i8_0:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    li a0, -3
33; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
34; CHECK-NEXT:    vmax.vx v8, v8, a0
35; CHECK-NEXT:    ret
36  %head = insertelement <vscale x 1 x i8> poison, i8 -3, i32 0
37  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
38  %cmp = icmp sgt <vscale x 1 x i8> %va, %splat
39  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
40  ret <vscale x 1 x i8> %vc
41}
42
43define <vscale x 2 x i8> @vmax_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
44; CHECK-LABEL: vmax_vv_nxv2i8:
45; CHECK:       # %bb.0:
46; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
47; CHECK-NEXT:    vmax.vv v8, v8, v9
48; CHECK-NEXT:    ret
49  %cmp = icmp sgt <vscale x 2 x i8> %va, %vb
50  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb
51  ret <vscale x 2 x i8> %vc
52}
53
54define <vscale x 2 x i8> @vmax_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
55; CHECK-LABEL: vmax_vx_nxv2i8:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
58; CHECK-NEXT:    vmax.vx v8, v8, a0
59; CHECK-NEXT:    ret
60  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
61  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
62  %cmp = icmp sgt <vscale x 2 x i8> %va, %splat
63  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
64  ret <vscale x 2 x i8> %vc
65}
66
67define <vscale x 2 x i8> @vmax_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
68; CHECK-LABEL: vmax_vi_nxv2i8_0:
69; CHECK:       # %bb.0:
70; CHECK-NEXT:    li a0, -3
71; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
72; CHECK-NEXT:    vmax.vx v8, v8, a0
73; CHECK-NEXT:    ret
74  %head = insertelement <vscale x 2 x i8> poison, i8 -3, i32 0
75  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
76  %cmp = icmp sgt <vscale x 2 x i8> %va, %splat
77  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
78  ret <vscale x 2 x i8> %vc
79}
80
81define <vscale x 4 x i8> @vmax_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
82; CHECK-LABEL: vmax_vv_nxv4i8:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
85; CHECK-NEXT:    vmax.vv v8, v8, v9
86; CHECK-NEXT:    ret
87  %cmp = icmp sgt <vscale x 4 x i8> %va, %vb
88  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb
89  ret <vscale x 4 x i8> %vc
90}
91
92define <vscale x 4 x i8> @vmax_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
93; CHECK-LABEL: vmax_vx_nxv4i8:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
96; CHECK-NEXT:    vmax.vx v8, v8, a0
97; CHECK-NEXT:    ret
98  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
99  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
100  %cmp = icmp sgt <vscale x 4 x i8> %va, %splat
101  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
102  ret <vscale x 4 x i8> %vc
103}
104
105define <vscale x 4 x i8> @vmax_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
106; CHECK-LABEL: vmax_vi_nxv4i8_0:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    li a0, -3
109; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
110; CHECK-NEXT:    vmax.vx v8, v8, a0
111; CHECK-NEXT:    ret
112  %head = insertelement <vscale x 4 x i8> poison, i8 -3, i32 0
113  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
114  %cmp = icmp sgt <vscale x 4 x i8> %va, %splat
115  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
116  ret <vscale x 4 x i8> %vc
117}
118
119define <vscale x 8 x i8> @vmax_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
120; CHECK-LABEL: vmax_vv_nxv8i8:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
123; CHECK-NEXT:    vmax.vv v8, v8, v9
124; CHECK-NEXT:    ret
125  %cmp = icmp sgt <vscale x 8 x i8> %va, %vb
126  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb
127  ret <vscale x 8 x i8> %vc
128}
129
130define <vscale x 8 x i8> @vmax_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
131; CHECK-LABEL: vmax_vx_nxv8i8:
132; CHECK:       # %bb.0:
133; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
134; CHECK-NEXT:    vmax.vx v8, v8, a0
135; CHECK-NEXT:    ret
136  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
137  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
138  %cmp = icmp sgt <vscale x 8 x i8> %va, %splat
139  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
140  ret <vscale x 8 x i8> %vc
141}
142
143define <vscale x 8 x i8> @vmax_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
144; CHECK-LABEL: vmax_vi_nxv8i8_0:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    li a0, -3
147; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
148; CHECK-NEXT:    vmax.vx v8, v8, a0
149; CHECK-NEXT:    ret
150  %head = insertelement <vscale x 8 x i8> poison, i8 -3, i32 0
151  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
152  %cmp = icmp sgt <vscale x 8 x i8> %va, %splat
153  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
154  ret <vscale x 8 x i8> %vc
155}
156
157define <vscale x 16 x i8> @vmax_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
158; CHECK-LABEL: vmax_vv_nxv16i8:
159; CHECK:       # %bb.0:
160; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
161; CHECK-NEXT:    vmax.vv v8, v8, v10
162; CHECK-NEXT:    ret
163  %cmp = icmp sgt <vscale x 16 x i8> %va, %vb
164  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb
165  ret <vscale x 16 x i8> %vc
166}
167
168define <vscale x 16 x i8> @vmax_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
169; CHECK-LABEL: vmax_vx_nxv16i8:
170; CHECK:       # %bb.0:
171; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
172; CHECK-NEXT:    vmax.vx v8, v8, a0
173; CHECK-NEXT:    ret
174  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
175  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
176  %cmp = icmp sgt <vscale x 16 x i8> %va, %splat
177  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
178  ret <vscale x 16 x i8> %vc
179}
180
181define <vscale x 16 x i8> @vmax_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
182; CHECK-LABEL: vmax_vi_nxv16i8_0:
183; CHECK:       # %bb.0:
184; CHECK-NEXT:    li a0, -3
185; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
186; CHECK-NEXT:    vmax.vx v8, v8, a0
187; CHECK-NEXT:    ret
188  %head = insertelement <vscale x 16 x i8> poison, i8 -3, i32 0
189  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
190  %cmp = icmp sgt <vscale x 16 x i8> %va, %splat
191  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
192  ret <vscale x 16 x i8> %vc
193}
194
195define <vscale x 32 x i8> @vmax_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
196; CHECK-LABEL: vmax_vv_nxv32i8:
197; CHECK:       # %bb.0:
198; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
199; CHECK-NEXT:    vmax.vv v8, v8, v12
200; CHECK-NEXT:    ret
201  %cmp = icmp sgt <vscale x 32 x i8> %va, %vb
202  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb
203  ret <vscale x 32 x i8> %vc
204}
205
206define <vscale x 32 x i8> @vmax_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
207; CHECK-LABEL: vmax_vx_nxv32i8:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
210; CHECK-NEXT:    vmax.vx v8, v8, a0
211; CHECK-NEXT:    ret
212  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
213  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
214  %cmp = icmp sgt <vscale x 32 x i8> %va, %splat
215  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
216  ret <vscale x 32 x i8> %vc
217}
218
219define <vscale x 32 x i8> @vmax_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
220; CHECK-LABEL: vmax_vi_nxv32i8_0:
221; CHECK:       # %bb.0:
222; CHECK-NEXT:    li a0, -3
223; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
224; CHECK-NEXT:    vmax.vx v8, v8, a0
225; CHECK-NEXT:    ret
226  %head = insertelement <vscale x 32 x i8> poison, i8 -3, i32 0
227  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
228  %cmp = icmp sgt <vscale x 32 x i8> %va, %splat
229  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
230  ret <vscale x 32 x i8> %vc
231}
232
233define <vscale x 64 x i8> @vmax_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
234; CHECK-LABEL: vmax_vv_nxv64i8:
235; CHECK:       # %bb.0:
236; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
237; CHECK-NEXT:    vmax.vv v8, v8, v16
238; CHECK-NEXT:    ret
239  %cmp = icmp sgt <vscale x 64 x i8> %va, %vb
240  %vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb
241  ret <vscale x 64 x i8> %vc
242}
243
244define <vscale x 64 x i8> @vmax_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
245; CHECK-LABEL: vmax_vx_nxv64i8:
246; CHECK:       # %bb.0:
247; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
248; CHECK-NEXT:    vmax.vx v8, v8, a0
249; CHECK-NEXT:    ret
250  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
251  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
252  %cmp = icmp sgt <vscale x 64 x i8> %va, %splat
253  %vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
254  ret <vscale x 64 x i8> %vc
255}
256
257define <vscale x 64 x i8> @vmax_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
258; CHECK-LABEL: vmax_vi_nxv64i8_0:
259; CHECK:       # %bb.0:
260; CHECK-NEXT:    li a0, -3
261; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
262; CHECK-NEXT:    vmax.vx v8, v8, a0
263; CHECK-NEXT:    ret
264  %head = insertelement <vscale x 64 x i8> poison, i8 -3, i32 0
265  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
266  %cmp = icmp sgt <vscale x 64 x i8> %va, %splat
267  %vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
268  ret <vscale x 64 x i8> %vc
269}
270
271define <vscale x 1 x i16> @vmax_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
272; CHECK-LABEL: vmax_vv_nxv1i16:
273; CHECK:       # %bb.0:
274; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
275; CHECK-NEXT:    vmax.vv v8, v8, v9
276; CHECK-NEXT:    ret
277  %cmp = icmp sgt <vscale x 1 x i16> %va, %vb
278  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb
279  ret <vscale x 1 x i16> %vc
280}
281
282define <vscale x 1 x i16> @vmax_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
283; CHECK-LABEL: vmax_vx_nxv1i16:
284; CHECK:       # %bb.0:
285; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
286; CHECK-NEXT:    vmax.vx v8, v8, a0
287; CHECK-NEXT:    ret
288  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
289  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
290  %cmp = icmp sgt <vscale x 1 x i16> %va, %splat
291  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
292  ret <vscale x 1 x i16> %vc
293}
294
295define <vscale x 1 x i16> @vmax_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
296; CHECK-LABEL: vmax_vi_nxv1i16_0:
297; CHECK:       # %bb.0:
298; CHECK-NEXT:    li a0, -3
299; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
300; CHECK-NEXT:    vmax.vx v8, v8, a0
301; CHECK-NEXT:    ret
302  %head = insertelement <vscale x 1 x i16> poison, i16 -3, i32 0
303  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
304  %cmp = icmp sgt <vscale x 1 x i16> %va, %splat
305  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
306  ret <vscale x 1 x i16> %vc
307}
308
309define <vscale x 2 x i16> @vmax_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
310; CHECK-LABEL: vmax_vv_nxv2i16:
311; CHECK:       # %bb.0:
312; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
313; CHECK-NEXT:    vmax.vv v8, v8, v9
314; CHECK-NEXT:    ret
315  %cmp = icmp sgt <vscale x 2 x i16> %va, %vb
316  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb
317  ret <vscale x 2 x i16> %vc
318}
319
320define <vscale x 2 x i16> @vmax_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
321; CHECK-LABEL: vmax_vx_nxv2i16:
322; CHECK:       # %bb.0:
323; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
324; CHECK-NEXT:    vmax.vx v8, v8, a0
325; CHECK-NEXT:    ret
326  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
327  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
328  %cmp = icmp sgt <vscale x 2 x i16> %va, %splat
329  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
330  ret <vscale x 2 x i16> %vc
331}
332
333define <vscale x 2 x i16> @vmax_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
334; CHECK-LABEL: vmax_vi_nxv2i16_0:
335; CHECK:       # %bb.0:
336; CHECK-NEXT:    li a0, -3
337; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
338; CHECK-NEXT:    vmax.vx v8, v8, a0
339; CHECK-NEXT:    ret
340  %head = insertelement <vscale x 2 x i16> poison, i16 -3, i32 0
341  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
342  %cmp = icmp sgt <vscale x 2 x i16> %va, %splat
343  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
344  ret <vscale x 2 x i16> %vc
345}
346
347define <vscale x 4 x i16> @vmax_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
348; CHECK-LABEL: vmax_vv_nxv4i16:
349; CHECK:       # %bb.0:
350; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
351; CHECK-NEXT:    vmax.vv v8, v8, v9
352; CHECK-NEXT:    ret
353  %cmp = icmp sgt <vscale x 4 x i16> %va, %vb
354  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb
355  ret <vscale x 4 x i16> %vc
356}
357
358define <vscale x 4 x i16> @vmax_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
359; CHECK-LABEL: vmax_vx_nxv4i16:
360; CHECK:       # %bb.0:
361; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
362; CHECK-NEXT:    vmax.vx v8, v8, a0
363; CHECK-NEXT:    ret
364  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
365  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
366  %cmp = icmp sgt <vscale x 4 x i16> %va, %splat
367  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
368  ret <vscale x 4 x i16> %vc
369}
370
371define <vscale x 4 x i16> @vmax_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
372; CHECK-LABEL: vmax_vi_nxv4i16_0:
373; CHECK:       # %bb.0:
374; CHECK-NEXT:    li a0, -3
375; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
376; CHECK-NEXT:    vmax.vx v8, v8, a0
377; CHECK-NEXT:    ret
378  %head = insertelement <vscale x 4 x i16> poison, i16 -3, i32 0
379  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
380  %cmp = icmp sgt <vscale x 4 x i16> %va, %splat
381  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
382  ret <vscale x 4 x i16> %vc
383}
384
385define <vscale x 8 x i16> @vmax_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
386; CHECK-LABEL: vmax_vv_nxv8i16:
387; CHECK:       # %bb.0:
388; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
389; CHECK-NEXT:    vmax.vv v8, v8, v10
390; CHECK-NEXT:    ret
391  %cmp = icmp sgt <vscale x 8 x i16> %va, %vb
392  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb
393  ret <vscale x 8 x i16> %vc
394}
395
396define <vscale x 8 x i16> @vmax_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
397; CHECK-LABEL: vmax_vx_nxv8i16:
398; CHECK:       # %bb.0:
399; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
400; CHECK-NEXT:    vmax.vx v8, v8, a0
401; CHECK-NEXT:    ret
402  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
403  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
404  %cmp = icmp sgt <vscale x 8 x i16> %va, %splat
405  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
406  ret <vscale x 8 x i16> %vc
407}
408
409define <vscale x 8 x i16> @vmax_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
410; CHECK-LABEL: vmax_vi_nxv8i16_0:
411; CHECK:       # %bb.0:
412; CHECK-NEXT:    li a0, -3
413; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
414; CHECK-NEXT:    vmax.vx v8, v8, a0
415; CHECK-NEXT:    ret
416  %head = insertelement <vscale x 8 x i16> poison, i16 -3, i32 0
417  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
418  %cmp = icmp sgt <vscale x 8 x i16> %va, %splat
419  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
420  ret <vscale x 8 x i16> %vc
421}
422
423define <vscale x 16 x i16> @vmax_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
424; CHECK-LABEL: vmax_vv_nxv16i16:
425; CHECK:       # %bb.0:
426; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
427; CHECK-NEXT:    vmax.vv v8, v8, v12
428; CHECK-NEXT:    ret
429  %cmp = icmp sgt <vscale x 16 x i16> %va, %vb
430  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb
431  ret <vscale x 16 x i16> %vc
432}
433
434define <vscale x 16 x i16> @vmax_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
435; CHECK-LABEL: vmax_vx_nxv16i16:
436; CHECK:       # %bb.0:
437; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
438; CHECK-NEXT:    vmax.vx v8, v8, a0
439; CHECK-NEXT:    ret
440  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
441  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
442  %cmp = icmp sgt <vscale x 16 x i16> %va, %splat
443  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
444  ret <vscale x 16 x i16> %vc
445}
446
447define <vscale x 16 x i16> @vmax_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
448; CHECK-LABEL: vmax_vi_nxv16i16_0:
449; CHECK:       # %bb.0:
450; CHECK-NEXT:    li a0, -3
451; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
452; CHECK-NEXT:    vmax.vx v8, v8, a0
453; CHECK-NEXT:    ret
454  %head = insertelement <vscale x 16 x i16> poison, i16 -3, i32 0
455  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
456  %cmp = icmp sgt <vscale x 16 x i16> %va, %splat
457  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
458  ret <vscale x 16 x i16> %vc
459}
460
461define <vscale x 32 x i16> @vmax_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
462; CHECK-LABEL: vmax_vv_nxv32i16:
463; CHECK:       # %bb.0:
464; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
465; CHECK-NEXT:    vmax.vv v8, v8, v16
466; CHECK-NEXT:    ret
467  %cmp = icmp sgt <vscale x 32 x i16> %va, %vb
468  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb
469  ret <vscale x 32 x i16> %vc
470}
471
472define <vscale x 32 x i16> @vmax_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
473; CHECK-LABEL: vmax_vx_nxv32i16:
474; CHECK:       # %bb.0:
475; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
476; CHECK-NEXT:    vmax.vx v8, v8, a0
477; CHECK-NEXT:    ret
478  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
479  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
480  %cmp = icmp sgt <vscale x 32 x i16> %va, %splat
481  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
482  ret <vscale x 32 x i16> %vc
483}
484
485define <vscale x 32 x i16> @vmax_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
486; CHECK-LABEL: vmax_vi_nxv32i16_0:
487; CHECK:       # %bb.0:
488; CHECK-NEXT:    li a0, -3
489; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
490; CHECK-NEXT:    vmax.vx v8, v8, a0
491; CHECK-NEXT:    ret
492  %head = insertelement <vscale x 32 x i16> poison, i16 -3, i32 0
493  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
494  %cmp = icmp sgt <vscale x 32 x i16> %va, %splat
495  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
496  ret <vscale x 32 x i16> %vc
497}
498
499define <vscale x 1 x i32> @vmax_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
500; CHECK-LABEL: vmax_vv_nxv1i32:
501; CHECK:       # %bb.0:
502; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
503; CHECK-NEXT:    vmax.vv v8, v8, v9
504; CHECK-NEXT:    ret
505  %cmp = icmp sgt <vscale x 1 x i32> %va, %vb
506  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb
507  ret <vscale x 1 x i32> %vc
508}
509
510define <vscale x 1 x i32> @vmax_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
511; CHECK-LABEL: vmax_vx_nxv1i32:
512; CHECK:       # %bb.0:
513; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
514; CHECK-NEXT:    vmax.vx v8, v8, a0
515; CHECK-NEXT:    ret
516  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
517  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
518  %cmp = icmp sgt <vscale x 1 x i32> %va, %splat
519  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
520  ret <vscale x 1 x i32> %vc
521}
522
523define <vscale x 1 x i32> @vmax_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
524; CHECK-LABEL: vmax_vi_nxv1i32_0:
525; CHECK:       # %bb.0:
526; CHECK-NEXT:    li a0, -3
527; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
528; CHECK-NEXT:    vmax.vx v8, v8, a0
529; CHECK-NEXT:    ret
530  %head = insertelement <vscale x 1 x i32> poison, i32 -3, i32 0
531  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
532  %cmp = icmp sgt <vscale x 1 x i32> %va, %splat
533  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
534  ret <vscale x 1 x i32> %vc
535}
536
537define <vscale x 2 x i32> @vmax_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
538; CHECK-LABEL: vmax_vv_nxv2i32:
539; CHECK:       # %bb.0:
540; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
541; CHECK-NEXT:    vmax.vv v8, v8, v9
542; CHECK-NEXT:    ret
543  %cmp = icmp sgt <vscale x 2 x i32> %va, %vb
544  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb
545  ret <vscale x 2 x i32> %vc
546}
547
548define <vscale x 2 x i32> @vmax_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
549; CHECK-LABEL: vmax_vx_nxv2i32:
550; CHECK:       # %bb.0:
551; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
552; CHECK-NEXT:    vmax.vx v8, v8, a0
553; CHECK-NEXT:    ret
554  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
555  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
556  %cmp = icmp sgt <vscale x 2 x i32> %va, %splat
557  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
558  ret <vscale x 2 x i32> %vc
559}
560
561define <vscale x 2 x i32> @vmax_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
562; CHECK-LABEL: vmax_vi_nxv2i32_0:
563; CHECK:       # %bb.0:
564; CHECK-NEXT:    li a0, -3
565; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
566; CHECK-NEXT:    vmax.vx v8, v8, a0
567; CHECK-NEXT:    ret
568  %head = insertelement <vscale x 2 x i32> poison, i32 -3, i32 0
569  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
570  %cmp = icmp sgt <vscale x 2 x i32> %va, %splat
571  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
572  ret <vscale x 2 x i32> %vc
573}
574
575define <vscale x 4 x i32> @vmax_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
576; CHECK-LABEL: vmax_vv_nxv4i32:
577; CHECK:       # %bb.0:
578; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
579; CHECK-NEXT:    vmax.vv v8, v8, v10
580; CHECK-NEXT:    ret
581  %cmp = icmp sgt <vscale x 4 x i32> %va, %vb
582  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb
583  ret <vscale x 4 x i32> %vc
584}
585
586define <vscale x 4 x i32> @vmax_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
587; CHECK-LABEL: vmax_vx_nxv4i32:
588; CHECK:       # %bb.0:
589; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
590; CHECK-NEXT:    vmax.vx v8, v8, a0
591; CHECK-NEXT:    ret
592  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
593  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
594  %cmp = icmp sgt <vscale x 4 x i32> %va, %splat
595  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
596  ret <vscale x 4 x i32> %vc
597}
598
599define <vscale x 4 x i32> @vmax_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
600; CHECK-LABEL: vmax_vi_nxv4i32_0:
601; CHECK:       # %bb.0:
602; CHECK-NEXT:    li a0, -3
603; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
604; CHECK-NEXT:    vmax.vx v8, v8, a0
605; CHECK-NEXT:    ret
606  %head = insertelement <vscale x 4 x i32> poison, i32 -3, i32 0
607  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
608  %cmp = icmp sgt <vscale x 4 x i32> %va, %splat
609  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
610  ret <vscale x 4 x i32> %vc
611}
612
613define <vscale x 8 x i32> @vmax_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
614; CHECK-LABEL: vmax_vv_nxv8i32:
615; CHECK:       # %bb.0:
616; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
617; CHECK-NEXT:    vmax.vv v8, v8, v12
618; CHECK-NEXT:    ret
619  %cmp = icmp sgt <vscale x 8 x i32> %va, %vb
620  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb
621  ret <vscale x 8 x i32> %vc
622}
623
624define <vscale x 8 x i32> @vmax_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
625; CHECK-LABEL: vmax_vx_nxv8i32:
626; CHECK:       # %bb.0:
627; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
628; CHECK-NEXT:    vmax.vx v8, v8, a0
629; CHECK-NEXT:    ret
630  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
631  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
632  %cmp = icmp sgt <vscale x 8 x i32> %va, %splat
633  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
634  ret <vscale x 8 x i32> %vc
635}
636
637define <vscale x 8 x i32> @vmax_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
638; CHECK-LABEL: vmax_vi_nxv8i32_0:
639; CHECK:       # %bb.0:
640; CHECK-NEXT:    li a0, -3
641; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
642; CHECK-NEXT:    vmax.vx v8, v8, a0
643; CHECK-NEXT:    ret
644  %head = insertelement <vscale x 8 x i32> poison, i32 -3, i32 0
645  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
646  %cmp = icmp sgt <vscale x 8 x i32> %va, %splat
647  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
648  ret <vscale x 8 x i32> %vc
649}
650
651define <vscale x 16 x i32> @vmax_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
652; CHECK-LABEL: vmax_vv_nxv16i32:
653; CHECK:       # %bb.0:
654; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
655; CHECK-NEXT:    vmax.vv v8, v8, v16
656; CHECK-NEXT:    ret
657  %cmp = icmp sgt <vscale x 16 x i32> %va, %vb
658  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb
659  ret <vscale x 16 x i32> %vc
660}
661
662define <vscale x 16 x i32> @vmax_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
663; CHECK-LABEL: vmax_vx_nxv16i32:
664; CHECK:       # %bb.0:
665; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
666; CHECK-NEXT:    vmax.vx v8, v8, a0
667; CHECK-NEXT:    ret
668  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
669  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
670  %cmp = icmp sgt <vscale x 16 x i32> %va, %splat
671  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
672  ret <vscale x 16 x i32> %vc
673}
674
675define <vscale x 16 x i32> @vmax_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
676; CHECK-LABEL: vmax_vi_nxv16i32_0:
677; CHECK:       # %bb.0:
678; CHECK-NEXT:    li a0, -3
679; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
680; CHECK-NEXT:    vmax.vx v8, v8, a0
681; CHECK-NEXT:    ret
682  %head = insertelement <vscale x 16 x i32> poison, i32 -3, i32 0
683  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
684  %cmp = icmp sgt <vscale x 16 x i32> %va, %splat
685  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
686  ret <vscale x 16 x i32> %vc
687}
688
689define <vscale x 1 x i64> @vmax_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
690; CHECK-LABEL: vmax_vv_nxv1i64:
691; CHECK:       # %bb.0:
692; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
693; CHECK-NEXT:    vmax.vv v8, v8, v9
694; CHECK-NEXT:    ret
695  %cmp = icmp sgt <vscale x 1 x i64> %va, %vb
696  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb
697  ret <vscale x 1 x i64> %vc
698}
699
700define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
701; RV32-LABEL: vmax_vx_nxv1i64:
702; RV32:       # %bb.0:
703; RV32-NEXT:    addi sp, sp, -16
704; RV32-NEXT:    .cfi_def_cfa_offset 16
705; RV32-NEXT:    sw a1, 12(sp)
706; RV32-NEXT:    sw a0, 8(sp)
707; RV32-NEXT:    addi a0, sp, 8
708; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
709; RV32-NEXT:    vlse64.v v9, (a0), zero
710; RV32-NEXT:    vmax.vv v8, v8, v9
711; RV32-NEXT:    addi sp, sp, 16
712; RV32-NEXT:    ret
713;
714; RV64-LABEL: vmax_vx_nxv1i64:
715; RV64:       # %bb.0:
716; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
717; RV64-NEXT:    vmax.vx v8, v8, a0
718; RV64-NEXT:    ret
719  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
720  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
721  %cmp = icmp sgt <vscale x 1 x i64> %va, %splat
722  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
723  ret <vscale x 1 x i64> %vc
724}
725
726define <vscale x 1 x i64> @vmax_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
727; CHECK-LABEL: vmax_vi_nxv1i64_0:
728; CHECK:       # %bb.0:
729; CHECK-NEXT:    li a0, -3
730; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
731; CHECK-NEXT:    vmax.vx v8, v8, a0
732; CHECK-NEXT:    ret
733  %head = insertelement <vscale x 1 x i64> poison, i64 -3, i32 0
734  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
735  %cmp = icmp sgt <vscale x 1 x i64> %va, %splat
736  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
737  ret <vscale x 1 x i64> %vc
738}
739
740define <vscale x 2 x i64> @vmax_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
741; CHECK-LABEL: vmax_vv_nxv2i64:
742; CHECK:       # %bb.0:
743; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
744; CHECK-NEXT:    vmax.vv v8, v8, v10
745; CHECK-NEXT:    ret
746  %cmp = icmp sgt <vscale x 2 x i64> %va, %vb
747  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb
748  ret <vscale x 2 x i64> %vc
749}
750
751define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
752; RV32-LABEL: vmax_vx_nxv2i64:
753; RV32:       # %bb.0:
754; RV32-NEXT:    addi sp, sp, -16
755; RV32-NEXT:    .cfi_def_cfa_offset 16
756; RV32-NEXT:    sw a1, 12(sp)
757; RV32-NEXT:    sw a0, 8(sp)
758; RV32-NEXT:    addi a0, sp, 8
759; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
760; RV32-NEXT:    vlse64.v v10, (a0), zero
761; RV32-NEXT:    vmax.vv v8, v8, v10
762; RV32-NEXT:    addi sp, sp, 16
763; RV32-NEXT:    ret
764;
765; RV64-LABEL: vmax_vx_nxv2i64:
766; RV64:       # %bb.0:
767; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
768; RV64-NEXT:    vmax.vx v8, v8, a0
769; RV64-NEXT:    ret
770  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
771  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
772  %cmp = icmp sgt <vscale x 2 x i64> %va, %splat
773  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
774  ret <vscale x 2 x i64> %vc
775}
776
777define <vscale x 2 x i64> @vmax_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
778; CHECK-LABEL: vmax_vi_nxv2i64_0:
779; CHECK:       # %bb.0:
780; CHECK-NEXT:    li a0, -3
781; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
782; CHECK-NEXT:    vmax.vx v8, v8, a0
783; CHECK-NEXT:    ret
784  %head = insertelement <vscale x 2 x i64> poison, i64 -3, i32 0
785  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
786  %cmp = icmp sgt <vscale x 2 x i64> %va, %splat
787  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
788  ret <vscale x 2 x i64> %vc
789}
790
791define <vscale x 4 x i64> @vmax_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
792; CHECK-LABEL: vmax_vv_nxv4i64:
793; CHECK:       # %bb.0:
794; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
795; CHECK-NEXT:    vmax.vv v8, v8, v12
796; CHECK-NEXT:    ret
797  %cmp = icmp sgt <vscale x 4 x i64> %va, %vb
798  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb
799  ret <vscale x 4 x i64> %vc
800}
801
802define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
803; RV32-LABEL: vmax_vx_nxv4i64:
804; RV32:       # %bb.0:
805; RV32-NEXT:    addi sp, sp, -16
806; RV32-NEXT:    .cfi_def_cfa_offset 16
807; RV32-NEXT:    sw a1, 12(sp)
808; RV32-NEXT:    sw a0, 8(sp)
809; RV32-NEXT:    addi a0, sp, 8
810; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
811; RV32-NEXT:    vlse64.v v12, (a0), zero
812; RV32-NEXT:    vmax.vv v8, v8, v12
813; RV32-NEXT:    addi sp, sp, 16
814; RV32-NEXT:    ret
815;
816; RV64-LABEL: vmax_vx_nxv4i64:
817; RV64:       # %bb.0:
818; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
819; RV64-NEXT:    vmax.vx v8, v8, a0
820; RV64-NEXT:    ret
821  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
822  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
823  %cmp = icmp sgt <vscale x 4 x i64> %va, %splat
824  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
825  ret <vscale x 4 x i64> %vc
826}
827
828define <vscale x 4 x i64> @vmax_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
829; CHECK-LABEL: vmax_vi_nxv4i64_0:
830; CHECK:       # %bb.0:
831; CHECK-NEXT:    li a0, -3
832; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
833; CHECK-NEXT:    vmax.vx v8, v8, a0
834; CHECK-NEXT:    ret
835  %head = insertelement <vscale x 4 x i64> poison, i64 -3, i32 0
836  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
837  %cmp = icmp sgt <vscale x 4 x i64> %va, %splat
838  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
839  ret <vscale x 4 x i64> %vc
840}
841
842define <vscale x 8 x i64> @vmax_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
843; CHECK-LABEL: vmax_vv_nxv8i64:
844; CHECK:       # %bb.0:
845; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
846; CHECK-NEXT:    vmax.vv v8, v8, v16
847; CHECK-NEXT:    ret
848  %cmp = icmp sgt <vscale x 8 x i64> %va, %vb
849  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
850  ret <vscale x 8 x i64> %vc
851}
852
853define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
854; RV32-LABEL: vmax_vx_nxv8i64:
855; RV32:       # %bb.0:
856; RV32-NEXT:    addi sp, sp, -16
857; RV32-NEXT:    .cfi_def_cfa_offset 16
858; RV32-NEXT:    sw a1, 12(sp)
859; RV32-NEXT:    sw a0, 8(sp)
860; RV32-NEXT:    addi a0, sp, 8
861; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
862; RV32-NEXT:    vlse64.v v16, (a0), zero
863; RV32-NEXT:    vmax.vv v8, v8, v16
864; RV32-NEXT:    addi sp, sp, 16
865; RV32-NEXT:    ret
866;
867; RV64-LABEL: vmax_vx_nxv8i64:
868; RV64:       # %bb.0:
869; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
870; RV64-NEXT:    vmax.vx v8, v8, a0
871; RV64-NEXT:    ret
872  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
873  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
874  %cmp = icmp sgt <vscale x 8 x i64> %va, %splat
875  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
876  ret <vscale x 8 x i64> %vc
877}
878
879define <vscale x 8 x i64> @vmax_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
880; CHECK-LABEL: vmax_vi_nxv8i64_0:
881; CHECK:       # %bb.0:
882; CHECK-NEXT:    li a0, -3
883; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
884; CHECK-NEXT:    vmax.vx v8, v8, a0
885; CHECK-NEXT:    ret
886  %head = insertelement <vscale x 8 x i64> poison, i64 -3, i32 0
887  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
888  %cmp = icmp sgt <vscale x 8 x i64> %va, %splat
889  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
890  ret <vscale x 8 x i64> %vc
891}
892
893