1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
4; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
6
7define <vscale x 1 x float> @vfpext_nxv1f16_nxv1f32(<vscale x 1 x half> %va) {
8;
9; RV32-LABEL: vfpext_nxv1f16_nxv1f32:
10; RV32:       # %bb.0:
11; RV32-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
12; RV32-NEXT:    vfwcvt.f.f.v v9, v8
13; RV32-NEXT:    vmv1r.v v8, v9
14; RV32-NEXT:    ret
15;
16; RV64-LABEL: vfpext_nxv1f16_nxv1f32:
17; RV64:       # %bb.0:
18; RV64-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
19; RV64-NEXT:    vfwcvt.f.f.v v9, v8
20; RV64-NEXT:    vmv1r.v v8, v9
21; RV64-NEXT:    ret
22  %evec = fpext <vscale x 1 x half> %va to <vscale x 1 x float>
23  ret <vscale x 1 x float> %evec
24}
25
26define <vscale x 1 x double> @vfpext_nxv1f16_nxv1f64(<vscale x 1 x half> %va) {
27;
28; RV32-LABEL: vfpext_nxv1f16_nxv1f64:
29; RV32:       # %bb.0:
30; RV32-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
31; RV32-NEXT:    vfwcvt.f.f.v v9, v8
32; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
33; RV32-NEXT:    vfwcvt.f.f.v v8, v9
34; RV32-NEXT:    ret
35;
36; RV64-LABEL: vfpext_nxv1f16_nxv1f64:
37; RV64:       # %bb.0:
38; RV64-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
39; RV64-NEXT:    vfwcvt.f.f.v v9, v8
40; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
41; RV64-NEXT:    vfwcvt.f.f.v v8, v9
42; RV64-NEXT:    ret
43  %evec = fpext <vscale x 1 x half> %va to <vscale x 1 x double>
44  ret <vscale x 1 x double> %evec
45}
46
47define <vscale x 2 x float> @vfpext_nxv2f16_nxv2f32(<vscale x 2 x half> %va) {
48;
49; RV32-LABEL: vfpext_nxv2f16_nxv2f32:
50; RV32:       # %bb.0:
51; RV32-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
52; RV32-NEXT:    vfwcvt.f.f.v v9, v8
53; RV32-NEXT:    vmv1r.v v8, v9
54; RV32-NEXT:    ret
55;
56; RV64-LABEL: vfpext_nxv2f16_nxv2f32:
57; RV64:       # %bb.0:
58; RV64-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
59; RV64-NEXT:    vfwcvt.f.f.v v9, v8
60; RV64-NEXT:    vmv1r.v v8, v9
61; RV64-NEXT:    ret
62  %evec = fpext <vscale x 2 x half> %va to <vscale x 2 x float>
63  ret <vscale x 2 x float> %evec
64}
65
66define <vscale x 2 x double> @vfpext_nxv2f16_nxv2f64(<vscale x 2 x half> %va) {
67;
68; RV32-LABEL: vfpext_nxv2f16_nxv2f64:
69; RV32:       # %bb.0:
70; RV32-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
71; RV32-NEXT:    vfwcvt.f.f.v v10, v8
72; RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
73; RV32-NEXT:    vfwcvt.f.f.v v8, v10
74; RV32-NEXT:    ret
75;
76; RV64-LABEL: vfpext_nxv2f16_nxv2f64:
77; RV64:       # %bb.0:
78; RV64-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
79; RV64-NEXT:    vfwcvt.f.f.v v10, v8
80; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
81; RV64-NEXT:    vfwcvt.f.f.v v8, v10
82; RV64-NEXT:    ret
83  %evec = fpext <vscale x 2 x half> %va to <vscale x 2 x double>
84  ret <vscale x 2 x double> %evec
85}
86
87define <vscale x 4 x float> @vfpext_nxv4f16_nxv4f32(<vscale x 4 x half> %va) {
88;
89; RV32-LABEL: vfpext_nxv4f16_nxv4f32:
90; RV32:       # %bb.0:
91; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
92; RV32-NEXT:    vfwcvt.f.f.v v10, v8
93; RV32-NEXT:    vmv2r.v v8, v10
94; RV32-NEXT:    ret
95;
96; RV64-LABEL: vfpext_nxv4f16_nxv4f32:
97; RV64:       # %bb.0:
98; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
99; RV64-NEXT:    vfwcvt.f.f.v v10, v8
100; RV64-NEXT:    vmv2r.v v8, v10
101; RV64-NEXT:    ret
102  %evec = fpext <vscale x 4 x half> %va to <vscale x 4 x float>
103  ret <vscale x 4 x float> %evec
104}
105
106define <vscale x 4 x double> @vfpext_nxv4f16_nxv4f64(<vscale x 4 x half> %va) {
107;
108; RV32-LABEL: vfpext_nxv4f16_nxv4f64:
109; RV32:       # %bb.0:
110; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
111; RV32-NEXT:    vfwcvt.f.f.v v12, v8
112; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
113; RV32-NEXT:    vfwcvt.f.f.v v8, v12
114; RV32-NEXT:    ret
115;
116; RV64-LABEL: vfpext_nxv4f16_nxv4f64:
117; RV64:       # %bb.0:
118; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
119; RV64-NEXT:    vfwcvt.f.f.v v12, v8
120; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
121; RV64-NEXT:    vfwcvt.f.f.v v8, v12
122; RV64-NEXT:    ret
123  %evec = fpext <vscale x 4 x half> %va to <vscale x 4 x double>
124  ret <vscale x 4 x double> %evec
125}
126
127define <vscale x 8 x float> @vfpext_nxv8f16_nxv8f32(<vscale x 8 x half> %va) {
128;
129; RV32-LABEL: vfpext_nxv8f16_nxv8f32:
130; RV32:       # %bb.0:
131; RV32-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
132; RV32-NEXT:    vfwcvt.f.f.v v12, v8
133; RV32-NEXT:    vmv4r.v v8, v12
134; RV32-NEXT:    ret
135;
136; RV64-LABEL: vfpext_nxv8f16_nxv8f32:
137; RV64:       # %bb.0:
138; RV64-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
139; RV64-NEXT:    vfwcvt.f.f.v v12, v8
140; RV64-NEXT:    vmv4r.v v8, v12
141; RV64-NEXT:    ret
142  %evec = fpext <vscale x 8 x half> %va to <vscale x 8 x float>
143  ret <vscale x 8 x float> %evec
144}
145
146define <vscale x 8 x double> @vfpext_nxv8f16_nxv8f64(<vscale x 8 x half> %va) {
147;
148; RV32-LABEL: vfpext_nxv8f16_nxv8f64:
149; RV32:       # %bb.0:
150; RV32-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
151; RV32-NEXT:    vfwcvt.f.f.v v16, v8
152; RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
153; RV32-NEXT:    vfwcvt.f.f.v v8, v16
154; RV32-NEXT:    ret
155;
156; RV64-LABEL: vfpext_nxv8f16_nxv8f64:
157; RV64:       # %bb.0:
158; RV64-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
159; RV64-NEXT:    vfwcvt.f.f.v v16, v8
160; RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
161; RV64-NEXT:    vfwcvt.f.f.v v8, v16
162; RV64-NEXT:    ret
163  %evec = fpext <vscale x 8 x half> %va to <vscale x 8 x double>
164  ret <vscale x 8 x double> %evec
165}
166
167define <vscale x 16 x float> @vfpext_nxv16f16_nxv16f32(<vscale x 16 x half> %va) {
168;
169; RV32-LABEL: vfpext_nxv16f16_nxv16f32:
170; RV32:       # %bb.0:
171; RV32-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
172; RV32-NEXT:    vfwcvt.f.f.v v16, v8
173; RV32-NEXT:    vmv8r.v v8, v16
174; RV32-NEXT:    ret
175;
176; RV64-LABEL: vfpext_nxv16f16_nxv16f32:
177; RV64:       # %bb.0:
178; RV64-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
179; RV64-NEXT:    vfwcvt.f.f.v v16, v8
180; RV64-NEXT:    vmv8r.v v8, v16
181; RV64-NEXT:    ret
182  %evec = fpext <vscale x 16 x half> %va to <vscale x 16 x float>
183  ret <vscale x 16 x float> %evec
184}
185
186define <vscale x 1 x double> @vfpext_nxv1f32_nxv1f64(<vscale x 1 x float> %va) {
187;
188; RV32-LABEL: vfpext_nxv1f32_nxv1f64:
189; RV32:       # %bb.0:
190; RV32-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
191; RV32-NEXT:    vfwcvt.f.f.v v9, v8
192; RV32-NEXT:    vmv1r.v v8, v9
193; RV32-NEXT:    ret
194;
195; RV64-LABEL: vfpext_nxv1f32_nxv1f64:
196; RV64:       # %bb.0:
197; RV64-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
198; RV64-NEXT:    vfwcvt.f.f.v v9, v8
199; RV64-NEXT:    vmv1r.v v8, v9
200; RV64-NEXT:    ret
201  %evec = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
202  ret <vscale x 1 x double> %evec
203}
204
205define <vscale x 2 x double> @vfpext_nxv2f32_nxv2f64(<vscale x 2 x float> %va) {
206;
207; RV32-LABEL: vfpext_nxv2f32_nxv2f64:
208; RV32:       # %bb.0:
209; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
210; RV32-NEXT:    vfwcvt.f.f.v v10, v8
211; RV32-NEXT:    vmv2r.v v8, v10
212; RV32-NEXT:    ret
213;
214; RV64-LABEL: vfpext_nxv2f32_nxv2f64:
215; RV64:       # %bb.0:
216; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
217; RV64-NEXT:    vfwcvt.f.f.v v10, v8
218; RV64-NEXT:    vmv2r.v v8, v10
219; RV64-NEXT:    ret
220  %evec = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
221  ret <vscale x 2 x double> %evec
222}
223
224define <vscale x 4 x double> @vfpext_nxv4f32_nxv4f64(<vscale x 4 x float> %va) {
225;
226; RV32-LABEL: vfpext_nxv4f32_nxv4f64:
227; RV32:       # %bb.0:
228; RV32-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
229; RV32-NEXT:    vfwcvt.f.f.v v12, v8
230; RV32-NEXT:    vmv4r.v v8, v12
231; RV32-NEXT:    ret
232;
233; RV64-LABEL: vfpext_nxv4f32_nxv4f64:
234; RV64:       # %bb.0:
235; RV64-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
236; RV64-NEXT:    vfwcvt.f.f.v v12, v8
237; RV64-NEXT:    vmv4r.v v8, v12
238; RV64-NEXT:    ret
239  %evec = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
240  ret <vscale x 4 x double> %evec
241}
242
243define <vscale x 8 x double> @vfpext_nxv8f32_nxv8f64(<vscale x 8 x float> %va) {
244;
245; RV32-LABEL: vfpext_nxv8f32_nxv8f64:
246; RV32:       # %bb.0:
247; RV32-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
248; RV32-NEXT:    vfwcvt.f.f.v v16, v8
249; RV32-NEXT:    vmv8r.v v8, v16
250; RV32-NEXT:    ret
251;
252; RV64-LABEL: vfpext_nxv8f32_nxv8f64:
253; RV64:       # %bb.0:
254; RV64-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
255; RV64-NEXT:    vfwcvt.f.f.v v16, v8
256; RV64-NEXT:    vmv8r.v v8, v16
257; RV64-NEXT:    ret
258  %evec = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
259  ret <vscale x 8 x double> %evec
260}
261
262