1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6
7define <vscale x 1 x float> @vfpext_nxv1f16_nxv1f32(<vscale x 1 x half> %va) {
8;
9; CHECK-LABEL: vfpext_nxv1f16_nxv1f32:
10; CHECK:       # %bb.0:
11; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
12; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
13; CHECK-NEXT:    vmv1r.v v8, v9
14; CHECK-NEXT:    ret
15  %evec = fpext <vscale x 1 x half> %va to <vscale x 1 x float>
16  ret <vscale x 1 x float> %evec
17}
18
19define <vscale x 1 x double> @vfpext_nxv1f16_nxv1f64(<vscale x 1 x half> %va) {
20;
21; CHECK-LABEL: vfpext_nxv1f16_nxv1f64:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
24; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
25; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
26; CHECK-NEXT:    vfwcvt.f.f.v v8, v9
27; CHECK-NEXT:    ret
28  %evec = fpext <vscale x 1 x half> %va to <vscale x 1 x double>
29  ret <vscale x 1 x double> %evec
30}
31
32define <vscale x 2 x float> @vfpext_nxv2f16_nxv2f32(<vscale x 2 x half> %va) {
33;
34; CHECK-LABEL: vfpext_nxv2f16_nxv2f32:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
37; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
38; CHECK-NEXT:    vmv1r.v v8, v9
39; CHECK-NEXT:    ret
40  %evec = fpext <vscale x 2 x half> %va to <vscale x 2 x float>
41  ret <vscale x 2 x float> %evec
42}
43
44define <vscale x 2 x double> @vfpext_nxv2f16_nxv2f64(<vscale x 2 x half> %va) {
45;
46; CHECK-LABEL: vfpext_nxv2f16_nxv2f64:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
49; CHECK-NEXT:    vfwcvt.f.f.v v10, v8
50; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
51; CHECK-NEXT:    vfwcvt.f.f.v v8, v10
52; CHECK-NEXT:    ret
53  %evec = fpext <vscale x 2 x half> %va to <vscale x 2 x double>
54  ret <vscale x 2 x double> %evec
55}
56
57define <vscale x 4 x float> @vfpext_nxv4f16_nxv4f32(<vscale x 4 x half> %va) {
58;
59; CHECK-LABEL: vfpext_nxv4f16_nxv4f32:
60; CHECK:       # %bb.0:
61; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
62; CHECK-NEXT:    vfwcvt.f.f.v v10, v8
63; CHECK-NEXT:    vmv2r.v v8, v10
64; CHECK-NEXT:    ret
65  %evec = fpext <vscale x 4 x half> %va to <vscale x 4 x float>
66  ret <vscale x 4 x float> %evec
67}
68
69define <vscale x 4 x double> @vfpext_nxv4f16_nxv4f64(<vscale x 4 x half> %va) {
70;
71; CHECK-LABEL: vfpext_nxv4f16_nxv4f64:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
74; CHECK-NEXT:    vfwcvt.f.f.v v12, v8
75; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
76; CHECK-NEXT:    vfwcvt.f.f.v v8, v12
77; CHECK-NEXT:    ret
78  %evec = fpext <vscale x 4 x half> %va to <vscale x 4 x double>
79  ret <vscale x 4 x double> %evec
80}
81
82define <vscale x 8 x float> @vfpext_nxv8f16_nxv8f32(<vscale x 8 x half> %va) {
83;
84; CHECK-LABEL: vfpext_nxv8f16_nxv8f32:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
87; CHECK-NEXT:    vfwcvt.f.f.v v12, v8
88; CHECK-NEXT:    vmv4r.v v8, v12
89; CHECK-NEXT:    ret
90  %evec = fpext <vscale x 8 x half> %va to <vscale x 8 x float>
91  ret <vscale x 8 x float> %evec
92}
93
94define <vscale x 8 x double> @vfpext_nxv8f16_nxv8f64(<vscale x 8 x half> %va) {
95;
96; CHECK-LABEL: vfpext_nxv8f16_nxv8f64:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
99; CHECK-NEXT:    vfwcvt.f.f.v v16, v8
100; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
101; CHECK-NEXT:    vfwcvt.f.f.v v8, v16
102; CHECK-NEXT:    ret
103  %evec = fpext <vscale x 8 x half> %va to <vscale x 8 x double>
104  ret <vscale x 8 x double> %evec
105}
106
107define <vscale x 16 x float> @vfpext_nxv16f16_nxv16f32(<vscale x 16 x half> %va) {
108;
109; CHECK-LABEL: vfpext_nxv16f16_nxv16f32:
110; CHECK:       # %bb.0:
111; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
112; CHECK-NEXT:    vfwcvt.f.f.v v16, v8
113; CHECK-NEXT:    vmv8r.v v8, v16
114; CHECK-NEXT:    ret
115  %evec = fpext <vscale x 16 x half> %va to <vscale x 16 x float>
116  ret <vscale x 16 x float> %evec
117}
118
119define <vscale x 1 x double> @vfpext_nxv1f32_nxv1f64(<vscale x 1 x float> %va) {
120;
121; CHECK-LABEL: vfpext_nxv1f32_nxv1f64:
122; CHECK:       # %bb.0:
123; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
124; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
125; CHECK-NEXT:    vmv1r.v v8, v9
126; CHECK-NEXT:    ret
127  %evec = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
128  ret <vscale x 1 x double> %evec
129}
130
131define <vscale x 2 x double> @vfpext_nxv2f32_nxv2f64(<vscale x 2 x float> %va) {
132;
133; CHECK-LABEL: vfpext_nxv2f32_nxv2f64:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
136; CHECK-NEXT:    vfwcvt.f.f.v v10, v8
137; CHECK-NEXT:    vmv2r.v v8, v10
138; CHECK-NEXT:    ret
139  %evec = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
140  ret <vscale x 2 x double> %evec
141}
142
143define <vscale x 4 x double> @vfpext_nxv4f32_nxv4f64(<vscale x 4 x float> %va) {
144;
145; CHECK-LABEL: vfpext_nxv4f32_nxv4f64:
146; CHECK:       # %bb.0:
147; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
148; CHECK-NEXT:    vfwcvt.f.f.v v12, v8
149; CHECK-NEXT:    vmv4r.v v8, v12
150; CHECK-NEXT:    ret
151  %evec = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
152  ret <vscale x 4 x double> %evec
153}
154
155define <vscale x 8 x double> @vfpext_nxv8f32_nxv8f64(<vscale x 8 x float> %va) {
156;
157; CHECK-LABEL: vfpext_nxv8f32_nxv8f64:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
160; CHECK-NEXT:    vfwcvt.f.f.v v16, v8
161; CHECK-NEXT:    vmv8r.v v8, v16
162; CHECK-NEXT:    ret
163  %evec = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
164  ret <vscale x 8 x double> %evec
165}
166