1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple riscv32 -mattr=+m,+f,+d,+v,+zfh,+experimental-zvfh < %s | FileCheck %s 3; RUN: llc -mtriple riscv64 -mattr=+m,+f,+d,+v,+zfh,+experimental-zvfh < %s | FileCheck %s 4 5; Tests assume VLEN=128 or vscale_range_min=2. 6 7declare <vscale x 1 x i1> @llvm.experimental.vector.splice.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>, i32) 8 9define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) #0 { 10; CHECK-LABEL: splice_nxv1i1_offset_negone: 11; CHECK: # %bb.0: 12; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 13; CHECK-NEXT: vmv.v.i v9, 0 14; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 15; CHECK-NEXT: csrr a0, vlenb 16; CHECK-NEXT: srli a0, a0, 3 17; CHECK-NEXT: addi a0, a0, -1 18; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu 19; CHECK-NEXT: vslidedown.vx v10, v10, a0 20; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 21; CHECK-NEXT: vmv1r.v v0, v8 22; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 23; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu 24; CHECK-NEXT: vslideup.vi v10, v8, 1 25; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu 26; CHECK-NEXT: vand.vi v8, v10, 1 27; CHECK-NEXT: vmsne.vi v0, v8, 0 28; CHECK-NEXT: ret 29 %res = call <vscale x 1 x i1> @llvm.experimental.vector.splice.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i32 -1) 30 ret <vscale x 1 x i1> %res 31} 32 33define <vscale x 1 x i1> @splice_nxv1i1_offset_max(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) #0 { 34; CHECK-LABEL: splice_nxv1i1_offset_max: 35; CHECK: # %bb.0: 36; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 37; CHECK-NEXT: vmv.v.i v9, 0 38; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 39; CHECK-NEXT: csrr a0, vlenb 40; CHECK-NEXT: srli a0, a0, 3 41; CHECK-NEXT: addi a0, a0, -1 42; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu 43; CHECK-NEXT: vslidedown.vi v10, v10, 1 44; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 45; CHECK-NEXT: vmv1r.v v0, v8 46; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 47; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu 48; CHECK-NEXT: vslideup.vx v10, v8, a0 49; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu 50; CHECK-NEXT: vand.vi v8, v10, 1 51; CHECK-NEXT: vmsne.vi v0, v8, 0 52; CHECK-NEXT: ret 53 %res = call <vscale x 1 x i1> @llvm.experimental.vector.splice.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i32 1) 54 ret <vscale x 1 x i1> %res 55} 56 57declare <vscale x 2 x i1> @llvm.experimental.vector.splice.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, i32) 58 59define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) #0 { 60; CHECK-LABEL: splice_nxv2i1_offset_negone: 61; CHECK: # %bb.0: 62; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu 63; CHECK-NEXT: vmv.v.i v9, 0 64; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 65; CHECK-NEXT: csrr a0, vlenb 66; CHECK-NEXT: srli a0, a0, 2 67; CHECK-NEXT: addi a0, a0, -1 68; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu 69; CHECK-NEXT: vslidedown.vx v10, v10, a0 70; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu 71; CHECK-NEXT: vmv1r.v v0, v8 72; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 73; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, mu 74; CHECK-NEXT: vslideup.vi v10, v8, 1 75; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu 76; CHECK-NEXT: vand.vi v8, v10, 1 77; CHECK-NEXT: vmsne.vi v0, v8, 0 78; CHECK-NEXT: ret 79 %res = call <vscale x 2 x i1> @llvm.experimental.vector.splice.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, i32 -1) 80 ret <vscale x 2 x i1> %res 81} 82 83define <vscale x 2 x i1> @splice_nxv2i1_offset_max(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) #0 { 84; CHECK-LABEL: splice_nxv2i1_offset_max: 85; CHECK: # %bb.0: 86; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu 87; CHECK-NEXT: vmv.v.i v9, 0 88; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 89; CHECK-NEXT: csrr a0, vlenb 90; CHECK-NEXT: srli a0, a0, 2 91; CHECK-NEXT: addi a0, a0, -3 92; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu 93; CHECK-NEXT: vslidedown.vi v10, v10, 3 94; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 95; CHECK-NEXT: vmv1r.v v0, v8 96; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 97; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, mu 98; CHECK-NEXT: vslideup.vx v10, v8, a0 99; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu 100; CHECK-NEXT: vand.vi v8, v10, 1 101; CHECK-NEXT: vmsne.vi v0, v8, 0 102; CHECK-NEXT: ret 103 %res = call <vscale x 2 x i1> @llvm.experimental.vector.splice.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, i32 3) 104 ret <vscale x 2 x i1> %res 105} 106 107declare <vscale x 4 x i1> @llvm.experimental.vector.splice.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, i32) 108 109define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) #0 { 110; CHECK-LABEL: splice_nxv4i1_offset_negone: 111; CHECK: # %bb.0: 112; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 113; CHECK-NEXT: vmv.v.i v9, 0 114; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 115; CHECK-NEXT: csrr a0, vlenb 116; CHECK-NEXT: srli a0, a0, 1 117; CHECK-NEXT: addi a0, a0, -1 118; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu 119; CHECK-NEXT: vslidedown.vx v10, v10, a0 120; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 121; CHECK-NEXT: vmv1r.v v0, v8 122; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 123; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, mu 124; CHECK-NEXT: vslideup.vi v10, v8, 1 125; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu 126; CHECK-NEXT: vand.vi v8, v10, 1 127; CHECK-NEXT: vmsne.vi v0, v8, 0 128; CHECK-NEXT: ret 129 %res = call <vscale x 4 x i1> @llvm.experimental.vector.splice.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, i32 -1) 130 ret <vscale x 4 x i1> %res 131} 132 133define <vscale x 4 x i1> @splice_nxv4i1_offset_max(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) #0 { 134; CHECK-LABEL: splice_nxv4i1_offset_max: 135; CHECK: # %bb.0: 136; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 137; CHECK-NEXT: vmv.v.i v9, 0 138; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 139; CHECK-NEXT: csrr a0, vlenb 140; CHECK-NEXT: srli a0, a0, 1 141; CHECK-NEXT: addi a0, a0, -7 142; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu 143; CHECK-NEXT: vslidedown.vi v10, v10, 7 144; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 145; CHECK-NEXT: vmv1r.v v0, v8 146; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 147; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, mu 148; CHECK-NEXT: vslideup.vx v10, v8, a0 149; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu 150; CHECK-NEXT: vand.vi v8, v10, 1 151; CHECK-NEXT: vmsne.vi v0, v8, 0 152; CHECK-NEXT: ret 153 %res = call <vscale x 4 x i1> @llvm.experimental.vector.splice.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, i32 7) 154 ret <vscale x 4 x i1> %res 155} 156 157declare <vscale x 8 x i1> @llvm.experimental.vector.splice.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, i32) 158 159define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) #0 { 160; CHECK-LABEL: splice_nxv8i1_offset_negone: 161; CHECK: # %bb.0: 162; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 163; CHECK-NEXT: vmv.v.i v9, 0 164; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 165; CHECK-NEXT: csrr a0, vlenb 166; CHECK-NEXT: addi a0, a0, -1 167; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu 168; CHECK-NEXT: vslidedown.vx v10, v10, a0 169; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 170; CHECK-NEXT: vmv1r.v v0, v8 171; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 172; CHECK-NEXT: vsetvli zero, zero, e8, m1, tu, mu 173; CHECK-NEXT: vslideup.vi v10, v8, 1 174; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu 175; CHECK-NEXT: vand.vi v8, v10, 1 176; CHECK-NEXT: vmsne.vi v0, v8, 0 177; CHECK-NEXT: ret 178 %res = call <vscale x 8 x i1> @llvm.experimental.vector.splice.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, i32 -1) 179 ret <vscale x 8 x i1> %res 180} 181 182define <vscale x 8 x i1> @splice_nxv8i1_offset_max(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) #0 { 183; CHECK-LABEL: splice_nxv8i1_offset_max: 184; CHECK: # %bb.0: 185; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 186; CHECK-NEXT: vmv.v.i v9, 0 187; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 188; CHECK-NEXT: csrr a0, vlenb 189; CHECK-NEXT: addi a0, a0, -15 190; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu 191; CHECK-NEXT: vslidedown.vi v10, v10, 15 192; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 193; CHECK-NEXT: vmv1r.v v0, v8 194; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 195; CHECK-NEXT: vsetvli zero, zero, e8, m1, tu, mu 196; CHECK-NEXT: vslideup.vx v10, v8, a0 197; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu 198; CHECK-NEXT: vand.vi v8, v10, 1 199; CHECK-NEXT: vmsne.vi v0, v8, 0 200; CHECK-NEXT: ret 201 %res = call <vscale x 8 x i1> @llvm.experimental.vector.splice.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, i32 15) 202 ret <vscale x 8 x i1> %res 203} 204 205declare <vscale x 16 x i1> @llvm.experimental.vector.splice.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, i32) 206 207define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 { 208; CHECK-LABEL: splice_nxv16i1_offset_negone: 209; CHECK: # %bb.0: 210; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu 211; CHECK-NEXT: vmv.v.i v10, 0 212; CHECK-NEXT: vmerge.vim v12, v10, 1, v0 213; CHECK-NEXT: csrr a0, vlenb 214; CHECK-NEXT: slli a0, a0, 1 215; CHECK-NEXT: addi a0, a0, -1 216; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu 217; CHECK-NEXT: vslidedown.vx v12, v12, a0 218; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu 219; CHECK-NEXT: vmv1r.v v0, v8 220; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 221; CHECK-NEXT: vsetvli zero, zero, e8, m2, tu, mu 222; CHECK-NEXT: vslideup.vi v12, v8, 1 223; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu 224; CHECK-NEXT: vand.vi v8, v12, 1 225; CHECK-NEXT: vmsne.vi v0, v8, 0 226; CHECK-NEXT: ret 227 %res = call <vscale x 16 x i1> @llvm.experimental.vector.splice.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, i32 -1) 228 ret <vscale x 16 x i1> %res 229} 230 231define <vscale x 16 x i1> @splice_nxv16i1_offset_max(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 { 232; CHECK-LABEL: splice_nxv16i1_offset_max: 233; CHECK: # %bb.0: 234; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu 235; CHECK-NEXT: vmv.v.i v10, 0 236; CHECK-NEXT: vmerge.vim v12, v10, 1, v0 237; CHECK-NEXT: csrr a0, vlenb 238; CHECK-NEXT: slli a0, a0, 1 239; CHECK-NEXT: addi a0, a0, -31 240; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu 241; CHECK-NEXT: vslidedown.vi v12, v12, 31 242; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 243; CHECK-NEXT: vmv1r.v v0, v8 244; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 245; CHECK-NEXT: vsetvli zero, zero, e8, m2, tu, mu 246; CHECK-NEXT: vslideup.vx v12, v8, a0 247; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu 248; CHECK-NEXT: vand.vi v8, v12, 1 249; CHECK-NEXT: vmsne.vi v0, v8, 0 250; CHECK-NEXT: ret 251 %res = call <vscale x 16 x i1> @llvm.experimental.vector.splice.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, i32 31) 252 ret <vscale x 16 x i1> %res 253} 254 255declare <vscale x 32 x i1> @llvm.experimental.vector.splice.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>, i32) 256 257define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b) #0 { 258; CHECK-LABEL: splice_nxv32i1_offset_negone: 259; CHECK: # %bb.0: 260; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu 261; CHECK-NEXT: vmv.v.i v12, 0 262; CHECK-NEXT: vmerge.vim v16, v12, 1, v0 263; CHECK-NEXT: csrr a0, vlenb 264; CHECK-NEXT: slli a0, a0, 2 265; CHECK-NEXT: addi a0, a0, -1 266; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu 267; CHECK-NEXT: vslidedown.vx v16, v16, a0 268; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu 269; CHECK-NEXT: vmv1r.v v0, v8 270; CHECK-NEXT: vmerge.vim v8, v12, 1, v0 271; CHECK-NEXT: vsetvli zero, zero, e8, m4, tu, mu 272; CHECK-NEXT: vslideup.vi v16, v8, 1 273; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, mu 274; CHECK-NEXT: vand.vi v8, v16, 1 275; CHECK-NEXT: vmsne.vi v0, v8, 0 276; CHECK-NEXT: ret 277 %res = call <vscale x 32 x i1> @llvm.experimental.vector.splice.nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, i32 -1) 278 ret <vscale x 32 x i1> %res 279} 280 281define <vscale x 32 x i1> @splice_nxv32i1_offset_max(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b) #0 { 282; CHECK-LABEL: splice_nxv32i1_offset_max: 283; CHECK: # %bb.0: 284; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu 285; CHECK-NEXT: vmv.v.i v12, 0 286; CHECK-NEXT: vmerge.vim v16, v12, 1, v0 287; CHECK-NEXT: csrr a0, vlenb 288; CHECK-NEXT: slli a0, a0, 2 289; CHECK-NEXT: addi a0, a0, -63 290; CHECK-NEXT: li a1, 63 291; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu 292; CHECK-NEXT: vslidedown.vx v16, v16, a1 293; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 294; CHECK-NEXT: vmv1r.v v0, v8 295; CHECK-NEXT: vmerge.vim v8, v12, 1, v0 296; CHECK-NEXT: vsetvli zero, zero, e8, m4, tu, mu 297; CHECK-NEXT: vslideup.vx v16, v8, a0 298; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, mu 299; CHECK-NEXT: vand.vi v8, v16, 1 300; CHECK-NEXT: vmsne.vi v0, v8, 0 301; CHECK-NEXT: ret 302 %res = call <vscale x 32 x i1> @llvm.experimental.vector.splice.nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, i32 63) 303 ret <vscale x 32 x i1> %res 304} 305 306declare <vscale x 64 x i1> @llvm.experimental.vector.splice.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>, i32) 307 308define <vscale x 64 x i1> @splice_nxv64i1_offset_negone(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) #0 { 309; CHECK-LABEL: splice_nxv64i1_offset_negone: 310; CHECK: # %bb.0: 311; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu 312; CHECK-NEXT: vmv.v.i v16, 0 313; CHECK-NEXT: vmerge.vim v24, v16, 1, v0 314; CHECK-NEXT: csrr a0, vlenb 315; CHECK-NEXT: slli a0, a0, 3 316; CHECK-NEXT: addi a0, a0, -1 317; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu 318; CHECK-NEXT: vslidedown.vx v24, v24, a0 319; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu 320; CHECK-NEXT: vmv1r.v v0, v8 321; CHECK-NEXT: vmerge.vim v8, v16, 1, v0 322; CHECK-NEXT: vsetvli zero, zero, e8, m8, tu, mu 323; CHECK-NEXT: vslideup.vi v24, v8, 1 324; CHECK-NEXT: vsetvli zero, zero, e8, m8, ta, mu 325; CHECK-NEXT: vand.vi v8, v24, 1 326; CHECK-NEXT: vmsne.vi v0, v8, 0 327; CHECK-NEXT: ret 328 %res = call <vscale x 64 x i1> @llvm.experimental.vector.splice.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, i32 -1) 329 ret <vscale x 64 x i1> %res 330} 331 332define <vscale x 64 x i1> @splice_nxv64i1_offset_max(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) #0 { 333; CHECK-LABEL: splice_nxv64i1_offset_max: 334; CHECK: # %bb.0: 335; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu 336; CHECK-NEXT: vmv.v.i v16, 0 337; CHECK-NEXT: vmerge.vim v24, v16, 1, v0 338; CHECK-NEXT: csrr a0, vlenb 339; CHECK-NEXT: slli a0, a0, 3 340; CHECK-NEXT: addi a0, a0, -127 341; CHECK-NEXT: li a1, 127 342; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu 343; CHECK-NEXT: vslidedown.vx v24, v24, a1 344; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 345; CHECK-NEXT: vmv1r.v v0, v8 346; CHECK-NEXT: vmerge.vim v8, v16, 1, v0 347; CHECK-NEXT: vsetvli zero, zero, e8, m8, tu, mu 348; CHECK-NEXT: vslideup.vx v24, v8, a0 349; CHECK-NEXT: vsetvli zero, zero, e8, m8, ta, mu 350; CHECK-NEXT: vand.vi v8, v24, 1 351; CHECK-NEXT: vmsne.vi v0, v8, 0 352; CHECK-NEXT: ret 353 %res = call <vscale x 64 x i1> @llvm.experimental.vector.splice.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, i32 127) 354 ret <vscale x 64 x i1> %res 355} 356 357declare <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, i32) 358 359define <vscale x 1 x i8> @splice_nxv1i8_offset_zero(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 { 360; CHECK-LABEL: splice_nxv1i8_offset_zero: 361; CHECK: # %bb.0: 362; CHECK-NEXT: ret 363 %res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 0) 364 ret <vscale x 1 x i8> %res 365} 366 367define <vscale x 1 x i8> @splice_nxv1i8_offset_negone(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 { 368; CHECK-LABEL: splice_nxv1i8_offset_negone: 369; CHECK: # %bb.0: 370; CHECK-NEXT: csrr a0, vlenb 371; CHECK-NEXT: srli a0, a0, 3 372; CHECK-NEXT: addi a0, a0, -1 373; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu 374; CHECK-NEXT: vslidedown.vx v8, v8, a0 375; CHECK-NEXT: vsetvli a0, zero, e8, mf8, tu, mu 376; CHECK-NEXT: vslideup.vi v8, v9, 1 377; CHECK-NEXT: ret 378 %res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 -1) 379 ret <vscale x 1 x i8> %res 380} 381 382define <vscale x 1 x i8> @splice_nxv1i8_offset_min(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 { 383; CHECK-LABEL: splice_nxv1i8_offset_min: 384; CHECK: # %bb.0: 385; CHECK-NEXT: csrr a0, vlenb 386; CHECK-NEXT: srli a0, a0, 3 387; CHECK-NEXT: addi a0, a0, -2 388; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu 389; CHECK-NEXT: vslidedown.vx v8, v8, a0 390; CHECK-NEXT: vsetvli a0, zero, e8, mf8, tu, mu 391; CHECK-NEXT: vslideup.vi v8, v9, 2 392; CHECK-NEXT: ret 393 %res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 -2) 394 ret <vscale x 1 x i8> %res 395} 396 397define <vscale x 1 x i8> @splice_nxv1i8_offset_max(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 { 398; CHECK-LABEL: splice_nxv1i8_offset_max: 399; CHECK: # %bb.0: 400; CHECK-NEXT: csrr a0, vlenb 401; CHECK-NEXT: srli a0, a0, 3 402; CHECK-NEXT: addi a0, a0, -1 403; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu 404; CHECK-NEXT: vslidedown.vi v8, v8, 1 405; CHECK-NEXT: vsetvli a1, zero, e8, mf8, tu, mu 406; CHECK-NEXT: vslideup.vx v8, v9, a0 407; CHECK-NEXT: ret 408 %res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 1) 409 ret <vscale x 1 x i8> %res 410} 411 412declare <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, i32) 413 414define <vscale x 2 x i8> @splice_nxv2i8_offset_zero(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 { 415; CHECK-LABEL: splice_nxv2i8_offset_zero: 416; CHECK: # %bb.0: 417; CHECK-NEXT: ret 418 %res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 0) 419 ret <vscale x 2 x i8> %res 420} 421 422define <vscale x 2 x i8> @splice_nxv2i8_offset_negone(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 { 423; CHECK-LABEL: splice_nxv2i8_offset_negone: 424; CHECK: # %bb.0: 425; CHECK-NEXT: csrr a0, vlenb 426; CHECK-NEXT: srli a0, a0, 2 427; CHECK-NEXT: addi a0, a0, -1 428; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu 429; CHECK-NEXT: vslidedown.vx v8, v8, a0 430; CHECK-NEXT: vsetvli a0, zero, e8, mf4, tu, mu 431; CHECK-NEXT: vslideup.vi v8, v9, 1 432; CHECK-NEXT: ret 433 %res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 -1) 434 ret <vscale x 2 x i8> %res 435} 436 437define <vscale x 2 x i8> @splice_nxv2i8_offset_min(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 { 438; CHECK-LABEL: splice_nxv2i8_offset_min: 439; CHECK: # %bb.0: 440; CHECK-NEXT: csrr a0, vlenb 441; CHECK-NEXT: srli a0, a0, 2 442; CHECK-NEXT: addi a0, a0, -4 443; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu 444; CHECK-NEXT: vslidedown.vx v8, v8, a0 445; CHECK-NEXT: vsetvli a0, zero, e8, mf4, tu, mu 446; CHECK-NEXT: vslideup.vi v8, v9, 4 447; CHECK-NEXT: ret 448 %res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 -4) 449 ret <vscale x 2 x i8> %res 450} 451 452define <vscale x 2 x i8> @splice_nxv2i8_offset_max(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 { 453; CHECK-LABEL: splice_nxv2i8_offset_max: 454; CHECK: # %bb.0: 455; CHECK-NEXT: csrr a0, vlenb 456; CHECK-NEXT: srli a0, a0, 2 457; CHECK-NEXT: addi a0, a0, -3 458; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu 459; CHECK-NEXT: vslidedown.vi v8, v8, 3 460; CHECK-NEXT: vsetvli a1, zero, e8, mf4, tu, mu 461; CHECK-NEXT: vslideup.vx v8, v9, a0 462; CHECK-NEXT: ret 463 %res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 3) 464 ret <vscale x 2 x i8> %res 465} 466 467declare <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, i32) 468 469define <vscale x 4 x i8> @splice_nxv4i8_offset_zero(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 { 470; CHECK-LABEL: splice_nxv4i8_offset_zero: 471; CHECK: # %bb.0: 472; CHECK-NEXT: ret 473 %res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 0) 474 ret <vscale x 4 x i8> %res 475} 476 477define <vscale x 4 x i8> @splice_nxv4i8_offset_negone(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 { 478; CHECK-LABEL: splice_nxv4i8_offset_negone: 479; CHECK: # %bb.0: 480; CHECK-NEXT: csrr a0, vlenb 481; CHECK-NEXT: srli a0, a0, 1 482; CHECK-NEXT: addi a0, a0, -1 483; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu 484; CHECK-NEXT: vslidedown.vx v8, v8, a0 485; CHECK-NEXT: vsetvli a0, zero, e8, mf2, tu, mu 486; CHECK-NEXT: vslideup.vi v8, v9, 1 487; CHECK-NEXT: ret 488 %res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 -1) 489 ret <vscale x 4 x i8> %res 490} 491 492define <vscale x 4 x i8> @splice_nxv4i8_offset_min(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 { 493; CHECK-LABEL: splice_nxv4i8_offset_min: 494; CHECK: # %bb.0: 495; CHECK-NEXT: csrr a0, vlenb 496; CHECK-NEXT: srli a0, a0, 1 497; CHECK-NEXT: addi a0, a0, -8 498; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 499; CHECK-NEXT: vslidedown.vx v8, v8, a0 500; CHECK-NEXT: vsetvli a0, zero, e8, mf2, tu, mu 501; CHECK-NEXT: vslideup.vi v8, v9, 8 502; CHECK-NEXT: ret 503 %res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 -8) 504 ret <vscale x 4 x i8> %res 505} 506 507define <vscale x 4 x i8> @splice_nxv4i8_offset_max(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 { 508; CHECK-LABEL: splice_nxv4i8_offset_max: 509; CHECK: # %bb.0: 510; CHECK-NEXT: csrr a0, vlenb 511; CHECK-NEXT: srli a0, a0, 1 512; CHECK-NEXT: addi a0, a0, -7 513; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu 514; CHECK-NEXT: vslidedown.vi v8, v8, 7 515; CHECK-NEXT: vsetvli a1, zero, e8, mf2, tu, mu 516; CHECK-NEXT: vslideup.vx v8, v9, a0 517; CHECK-NEXT: ret 518 %res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 7) 519 ret <vscale x 4 x i8> %res 520} 521 522declare <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, i32) 523 524define <vscale x 8 x i8> @splice_nxv8i8_offset_zero(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 { 525; CHECK-LABEL: splice_nxv8i8_offset_zero: 526; CHECK: # %bb.0: 527; CHECK-NEXT: ret 528 %res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 0) 529 ret <vscale x 8 x i8> %res 530} 531 532define <vscale x 8 x i8> @splice_nxv8i8_offset_negone(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 { 533; CHECK-LABEL: splice_nxv8i8_offset_negone: 534; CHECK: # %bb.0: 535; CHECK-NEXT: csrr a0, vlenb 536; CHECK-NEXT: addi a0, a0, -1 537; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu 538; CHECK-NEXT: vslidedown.vx v8, v8, a0 539; CHECK-NEXT: vsetvli a0, zero, e8, m1, tu, mu 540; CHECK-NEXT: vslideup.vi v8, v9, 1 541; CHECK-NEXT: ret 542 %res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 -1) 543 ret <vscale x 8 x i8> %res 544} 545 546define <vscale x 8 x i8> @splice_nxv8i8_offset_min(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 { 547; CHECK-LABEL: splice_nxv8i8_offset_min: 548; CHECK: # %bb.0: 549; CHECK-NEXT: csrr a0, vlenb 550; CHECK-NEXT: addi a0, a0, -16 551; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu 552; CHECK-NEXT: vslidedown.vx v8, v8, a0 553; CHECK-NEXT: vsetvli a0, zero, e8, m1, tu, mu 554; CHECK-NEXT: vslideup.vi v8, v9, 16 555; CHECK-NEXT: ret 556 %res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 -16) 557 ret <vscale x 8 x i8> %res 558} 559 560define <vscale x 8 x i8> @splice_nxv8i8_offset_max(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 { 561; CHECK-LABEL: splice_nxv8i8_offset_max: 562; CHECK: # %bb.0: 563; CHECK-NEXT: csrr a0, vlenb 564; CHECK-NEXT: addi a0, a0, -15 565; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu 566; CHECK-NEXT: vslidedown.vi v8, v8, 15 567; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, mu 568; CHECK-NEXT: vslideup.vx v8, v9, a0 569; CHECK-NEXT: ret 570 %res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 15) 571 ret <vscale x 8 x i8> %res 572} 573 574declare <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32) 575 576define <vscale x 16 x i8> @splice_nxv16i8_offset_zero(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 { 577; CHECK-LABEL: splice_nxv16i8_offset_zero: 578; CHECK: # %bb.0: 579; CHECK-NEXT: ret 580 %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 0) 581 ret <vscale x 16 x i8> %res 582} 583 584define <vscale x 16 x i8> @splice_nxv16i8_offset_negone(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 { 585; CHECK-LABEL: splice_nxv16i8_offset_negone: 586; CHECK: # %bb.0: 587; CHECK-NEXT: csrr a0, vlenb 588; CHECK-NEXT: slli a0, a0, 1 589; CHECK-NEXT: addi a0, a0, -1 590; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu 591; CHECK-NEXT: vslidedown.vx v8, v8, a0 592; CHECK-NEXT: vsetvli a0, zero, e8, m2, tu, mu 593; CHECK-NEXT: vslideup.vi v8, v10, 1 594; CHECK-NEXT: ret 595 %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -1) 596 ret <vscale x 16 x i8> %res 597} 598 599define <vscale x 16 x i8> @splice_nxv16i8_offset_min(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 { 600; CHECK-LABEL: splice_nxv16i8_offset_min: 601; CHECK: # %bb.0: 602; CHECK-NEXT: csrr a0, vlenb 603; CHECK-NEXT: slli a0, a0, 1 604; CHECK-NEXT: addi a0, a0, -32 605; CHECK-NEXT: li a1, 32 606; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu 607; CHECK-NEXT: vslidedown.vx v8, v8, a0 608; CHECK-NEXT: vsetvli a0, zero, e8, m2, tu, mu 609; CHECK-NEXT: vslideup.vx v8, v10, a1 610; CHECK-NEXT: ret 611 %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -32) 612 ret <vscale x 16 x i8> %res 613} 614 615define <vscale x 16 x i8> @splice_nxv16i8_offset_max(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 { 616; CHECK-LABEL: splice_nxv16i8_offset_max: 617; CHECK: # %bb.0: 618; CHECK-NEXT: csrr a0, vlenb 619; CHECK-NEXT: slli a0, a0, 1 620; CHECK-NEXT: addi a0, a0, -31 621; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu 622; CHECK-NEXT: vslidedown.vi v8, v8, 31 623; CHECK-NEXT: vsetvli a1, zero, e8, m2, tu, mu 624; CHECK-NEXT: vslideup.vx v8, v10, a0 625; CHECK-NEXT: ret 626 %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 31) 627 ret <vscale x 16 x i8> %res 628} 629 630declare <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, i32) 631 632define <vscale x 32 x i8> @splice_nxv32i8_offset_zero(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 { 633; CHECK-LABEL: splice_nxv32i8_offset_zero: 634; CHECK: # %bb.0: 635; CHECK-NEXT: ret 636 %res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 0) 637 ret <vscale x 32 x i8> %res 638} 639 640define <vscale x 32 x i8> @splice_nxv32i8_offset_negone(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 { 641; CHECK-LABEL: splice_nxv32i8_offset_negone: 642; CHECK: # %bb.0: 643; CHECK-NEXT: csrr a0, vlenb 644; CHECK-NEXT: slli a0, a0, 2 645; CHECK-NEXT: addi a0, a0, -1 646; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu 647; CHECK-NEXT: vslidedown.vx v8, v8, a0 648; CHECK-NEXT: vsetvli a0, zero, e8, m4, tu, mu 649; CHECK-NEXT: vslideup.vi v8, v12, 1 650; CHECK-NEXT: ret 651 %res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 -1) 652 ret <vscale x 32 x i8> %res 653} 654 655define <vscale x 32 x i8> @splice_nxv32i8_offset_min(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 { 656; CHECK-LABEL: splice_nxv32i8_offset_min: 657; CHECK: # %bb.0: 658; CHECK-NEXT: csrr a0, vlenb 659; CHECK-NEXT: slli a0, a0, 2 660; CHECK-NEXT: addi a0, a0, -64 661; CHECK-NEXT: li a1, 64 662; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu 663; CHECK-NEXT: vslidedown.vx v8, v8, a0 664; CHECK-NEXT: vsetvli a0, zero, e8, m4, tu, mu 665; CHECK-NEXT: vslideup.vx v8, v12, a1 666; CHECK-NEXT: ret 667 %res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 -64) 668 ret <vscale x 32 x i8> %res 669} 670 671define <vscale x 32 x i8> @splice_nxv32i8_offset_max(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 { 672; CHECK-LABEL: splice_nxv32i8_offset_max: 673; CHECK: # %bb.0: 674; CHECK-NEXT: csrr a0, vlenb 675; CHECK-NEXT: slli a0, a0, 2 676; CHECK-NEXT: addi a0, a0, -63 677; CHECK-NEXT: li a1, 63 678; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu 679; CHECK-NEXT: vslidedown.vx v8, v8, a1 680; CHECK-NEXT: vsetvli a1, zero, e8, m4, tu, mu 681; CHECK-NEXT: vslideup.vx v8, v12, a0 682; CHECK-NEXT: ret 683 %res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 63) 684 ret <vscale x 32 x i8> %res 685} 686 687declare <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, i32) 688 689define <vscale x 64 x i8> @splice_nxv64i8_offset_zero(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 { 690; CHECK-LABEL: splice_nxv64i8_offset_zero: 691; CHECK: # %bb.0: 692; CHECK-NEXT: ret 693 %res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 0) 694 ret <vscale x 64 x i8> %res 695} 696 697define <vscale x 64 x i8> @splice_nxv64i8_offset_negone(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 { 698; CHECK-LABEL: splice_nxv64i8_offset_negone: 699; CHECK: # %bb.0: 700; CHECK-NEXT: csrr a0, vlenb 701; CHECK-NEXT: slli a0, a0, 3 702; CHECK-NEXT: addi a0, a0, -1 703; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu 704; CHECK-NEXT: vslidedown.vx v8, v8, a0 705; CHECK-NEXT: vsetvli a0, zero, e8, m8, tu, mu 706; CHECK-NEXT: vslideup.vi v8, v16, 1 707; CHECK-NEXT: ret 708 %res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 -1) 709 ret <vscale x 64 x i8> %res 710} 711 712define <vscale x 64 x i8> @splice_nxv64i8_offset_min(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 { 713; CHECK-LABEL: splice_nxv64i8_offset_min: 714; CHECK: # %bb.0: 715; CHECK-NEXT: csrr a0, vlenb 716; CHECK-NEXT: slli a0, a0, 3 717; CHECK-NEXT: addi a0, a0, -128 718; CHECK-NEXT: li a1, 128 719; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu 720; CHECK-NEXT: vslidedown.vx v8, v8, a0 721; CHECK-NEXT: vsetvli a0, zero, e8, m8, tu, mu 722; CHECK-NEXT: vslideup.vx v8, v16, a1 723; CHECK-NEXT: ret 724 %res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 -128) 725 ret <vscale x 64 x i8> %res 726} 727 728define <vscale x 64 x i8> @splice_nxv64i8_offset_max(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 { 729; CHECK-LABEL: splice_nxv64i8_offset_max: 730; CHECK: # %bb.0: 731; CHECK-NEXT: csrr a0, vlenb 732; CHECK-NEXT: slli a0, a0, 3 733; CHECK-NEXT: addi a0, a0, -127 734; CHECK-NEXT: li a1, 127 735; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu 736; CHECK-NEXT: vslidedown.vx v8, v8, a1 737; CHECK-NEXT: vsetvli a1, zero, e8, m8, tu, mu 738; CHECK-NEXT: vslideup.vx v8, v16, a0 739; CHECK-NEXT: ret 740 %res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 127) 741 ret <vscale x 64 x i8> %res 742} 743 744declare <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, i32) 745 746define <vscale x 1 x i16> @splice_nxv1i16_offset_zero(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 { 747; CHECK-LABEL: splice_nxv1i16_offset_zero: 748; CHECK: # %bb.0: 749; CHECK-NEXT: ret 750 %res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 0) 751 ret <vscale x 1 x i16> %res 752} 753 754define <vscale x 1 x i16> @splice_nxv1i16_offset_negone(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 { 755; CHECK-LABEL: splice_nxv1i16_offset_negone: 756; CHECK: # %bb.0: 757; CHECK-NEXT: csrr a0, vlenb 758; CHECK-NEXT: srli a0, a0, 3 759; CHECK-NEXT: addi a0, a0, -1 760; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu 761; CHECK-NEXT: vslidedown.vx v8, v8, a0 762; CHECK-NEXT: vsetvli a0, zero, e16, mf4, tu, mu 763; CHECK-NEXT: vslideup.vi v8, v9, 1 764; CHECK-NEXT: ret 765 %res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 -1) 766 ret <vscale x 1 x i16> %res 767} 768 769define <vscale x 1 x i16> @splice_nxv1i16_offset_min(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 { 770; CHECK-LABEL: splice_nxv1i16_offset_min: 771; CHECK: # %bb.0: 772; CHECK-NEXT: csrr a0, vlenb 773; CHECK-NEXT: srli a0, a0, 3 774; CHECK-NEXT: addi a0, a0, -2 775; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu 776; CHECK-NEXT: vslidedown.vx v8, v8, a0 777; CHECK-NEXT: vsetvli a0, zero, e16, mf4, tu, mu 778; CHECK-NEXT: vslideup.vi v8, v9, 2 779; CHECK-NEXT: ret 780 %res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 -2) 781 ret <vscale x 1 x i16> %res 782} 783 784define <vscale x 1 x i16> @splice_nxv1i16_offset_max(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 { 785; CHECK-LABEL: splice_nxv1i16_offset_max: 786; CHECK: # %bb.0: 787; CHECK-NEXT: csrr a0, vlenb 788; CHECK-NEXT: srli a0, a0, 3 789; CHECK-NEXT: addi a0, a0, -1 790; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu 791; CHECK-NEXT: vslidedown.vi v8, v8, 1 792; CHECK-NEXT: vsetvli a1, zero, e16, mf4, tu, mu 793; CHECK-NEXT: vslideup.vx v8, v9, a0 794; CHECK-NEXT: ret 795 %res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 1) 796 ret <vscale x 1 x i16> %res 797} 798 799declare <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, i32) 800 801define <vscale x 2 x i16> @splice_nxv2i16_offset_zero(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 { 802; CHECK-LABEL: splice_nxv2i16_offset_zero: 803; CHECK: # %bb.0: 804; CHECK-NEXT: ret 805 %res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 0) 806 ret <vscale x 2 x i16> %res 807} 808 809define <vscale x 2 x i16> @splice_nxv2i16_offset_negone(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 { 810; CHECK-LABEL: splice_nxv2i16_offset_negone: 811; CHECK: # %bb.0: 812; CHECK-NEXT: csrr a0, vlenb 813; CHECK-NEXT: srli a0, a0, 2 814; CHECK-NEXT: addi a0, a0, -1 815; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu 816; CHECK-NEXT: vslidedown.vx v8, v8, a0 817; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu 818; CHECK-NEXT: vslideup.vi v8, v9, 1 819; CHECK-NEXT: ret 820 %res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 -1) 821 ret <vscale x 2 x i16> %res 822} 823 824define <vscale x 2 x i16> @splice_nxv2i16_offset_min(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 { 825; CHECK-LABEL: splice_nxv2i16_offset_min: 826; CHECK: # %bb.0: 827; CHECK-NEXT: csrr a0, vlenb 828; CHECK-NEXT: srli a0, a0, 2 829; CHECK-NEXT: addi a0, a0, -4 830; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu 831; CHECK-NEXT: vslidedown.vx v8, v8, a0 832; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu 833; CHECK-NEXT: vslideup.vi v8, v9, 4 834; CHECK-NEXT: ret 835 %res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 -4) 836 ret <vscale x 2 x i16> %res 837} 838 839define <vscale x 2 x i16> @splice_nxv2i16_offset_max(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 { 840; CHECK-LABEL: splice_nxv2i16_offset_max: 841; CHECK: # %bb.0: 842; CHECK-NEXT: csrr a0, vlenb 843; CHECK-NEXT: srli a0, a0, 2 844; CHECK-NEXT: addi a0, a0, -3 845; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu 846; CHECK-NEXT: vslidedown.vi v8, v8, 3 847; CHECK-NEXT: vsetvli a1, zero, e16, mf2, tu, mu 848; CHECK-NEXT: vslideup.vx v8, v9, a0 849; CHECK-NEXT: ret 850 %res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 3) 851 ret <vscale x 2 x i16> %res 852} 853 854declare <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, i32) 855 856define <vscale x 4 x i16> @splice_nxv4i16_offset_zero(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 { 857; CHECK-LABEL: splice_nxv4i16_offset_zero: 858; CHECK: # %bb.0: 859; CHECK-NEXT: ret 860 %res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 0) 861 ret <vscale x 4 x i16> %res 862} 863 864define <vscale x 4 x i16> @splice_nxv4i16_offset_negone(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 { 865; CHECK-LABEL: splice_nxv4i16_offset_negone: 866; CHECK: # %bb.0: 867; CHECK-NEXT: csrr a0, vlenb 868; CHECK-NEXT: srli a0, a0, 1 869; CHECK-NEXT: addi a0, a0, -1 870; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu 871; CHECK-NEXT: vslidedown.vx v8, v8, a0 872; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu 873; CHECK-NEXT: vslideup.vi v8, v9, 1 874; CHECK-NEXT: ret 875 %res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 -1) 876 ret <vscale x 4 x i16> %res 877} 878 879define <vscale x 4 x i16> @splice_nxv4i16_offset_min(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 { 880; CHECK-LABEL: splice_nxv4i16_offset_min: 881; CHECK: # %bb.0: 882; CHECK-NEXT: csrr a0, vlenb 883; CHECK-NEXT: srli a0, a0, 1 884; CHECK-NEXT: addi a0, a0, -8 885; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu 886; CHECK-NEXT: vslidedown.vx v8, v8, a0 887; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu 888; CHECK-NEXT: vslideup.vi v8, v9, 8 889; CHECK-NEXT: ret 890 %res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 -8) 891 ret <vscale x 4 x i16> %res 892} 893 894define <vscale x 4 x i16> @splice_nxv4i16_offset_max(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 { 895; CHECK-LABEL: splice_nxv4i16_offset_max: 896; CHECK: # %bb.0: 897; CHECK-NEXT: csrr a0, vlenb 898; CHECK-NEXT: srli a0, a0, 1 899; CHECK-NEXT: addi a0, a0, -7 900; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu 901; CHECK-NEXT: vslidedown.vi v8, v8, 7 902; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, mu 903; CHECK-NEXT: vslideup.vx v8, v9, a0 904; CHECK-NEXT: ret 905 %res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 7) 906 ret <vscale x 4 x i16> %res 907} 908 909declare <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32) 910 911define <vscale x 8 x i16> @splice_nxv8i16_offset_zero(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 { 912; CHECK-LABEL: splice_nxv8i16_offset_zero: 913; CHECK: # %bb.0: 914; CHECK-NEXT: ret 915 %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 0) 916 ret <vscale x 8 x i16> %res 917} 918 919define <vscale x 8 x i16> @splice_nxv8i16_offset_negone(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 { 920; CHECK-LABEL: splice_nxv8i16_offset_negone: 921; CHECK: # %bb.0: 922; CHECK-NEXT: csrr a0, vlenb 923; CHECK-NEXT: addi a0, a0, -1 924; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu 925; CHECK-NEXT: vslidedown.vx v8, v8, a0 926; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu 927; CHECK-NEXT: vslideup.vi v8, v10, 1 928; CHECK-NEXT: ret 929 %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -1) 930 ret <vscale x 8 x i16> %res 931} 932 933define <vscale x 8 x i16> @splice_nxv8i16_offset_min(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 { 934; CHECK-LABEL: splice_nxv8i16_offset_min: 935; CHECK: # %bb.0: 936; CHECK-NEXT: csrr a0, vlenb 937; CHECK-NEXT: addi a0, a0, -16 938; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu 939; CHECK-NEXT: vslidedown.vx v8, v8, a0 940; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu 941; CHECK-NEXT: vslideup.vi v8, v10, 16 942; CHECK-NEXT: ret 943 %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -16) 944 ret <vscale x 8 x i16> %res 945} 946 947define <vscale x 8 x i16> @splice_nxv8i16_offset_max(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 { 948; CHECK-LABEL: splice_nxv8i16_offset_max: 949; CHECK: # %bb.0: 950; CHECK-NEXT: csrr a0, vlenb 951; CHECK-NEXT: addi a0, a0, -15 952; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu 953; CHECK-NEXT: vslidedown.vi v8, v8, 15 954; CHECK-NEXT: vsetvli a1, zero, e16, m2, tu, mu 955; CHECK-NEXT: vslideup.vx v8, v10, a0 956; CHECK-NEXT: ret 957 %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 15) 958 ret <vscale x 8 x i16> %res 959} 960 961declare <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, i32) 962 963define <vscale x 16 x i16> @splice_nxv16i16_offset_zero(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 { 964; CHECK-LABEL: splice_nxv16i16_offset_zero: 965; CHECK: # %bb.0: 966; CHECK-NEXT: ret 967 %res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 0) 968 ret <vscale x 16 x i16> %res 969} 970 971define <vscale x 16 x i16> @splice_nxv16i16_offset_negone(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 { 972; CHECK-LABEL: splice_nxv16i16_offset_negone: 973; CHECK: # %bb.0: 974; CHECK-NEXT: csrr a0, vlenb 975; CHECK-NEXT: slli a0, a0, 1 976; CHECK-NEXT: addi a0, a0, -1 977; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu 978; CHECK-NEXT: vslidedown.vx v8, v8, a0 979; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu 980; CHECK-NEXT: vslideup.vi v8, v12, 1 981; CHECK-NEXT: ret 982 %res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 -1) 983 ret <vscale x 16 x i16> %res 984} 985 986define <vscale x 16 x i16> @splice_nxv16i16_offset_min(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 { 987; CHECK-LABEL: splice_nxv16i16_offset_min: 988; CHECK: # %bb.0: 989; CHECK-NEXT: csrr a0, vlenb 990; CHECK-NEXT: slli a0, a0, 1 991; CHECK-NEXT: addi a0, a0, -32 992; CHECK-NEXT: li a1, 32 993; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu 994; CHECK-NEXT: vslidedown.vx v8, v8, a0 995; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu 996; CHECK-NEXT: vslideup.vx v8, v12, a1 997; CHECK-NEXT: ret 998 %res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 -32) 999 ret <vscale x 16 x i16> %res 1000} 1001 1002define <vscale x 16 x i16> @splice_nxv16i16_offset_max(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 { 1003; CHECK-LABEL: splice_nxv16i16_offset_max: 1004; CHECK: # %bb.0: 1005; CHECK-NEXT: csrr a0, vlenb 1006; CHECK-NEXT: slli a0, a0, 1 1007; CHECK-NEXT: addi a0, a0, -31 1008; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu 1009; CHECK-NEXT: vslidedown.vi v8, v8, 31 1010; CHECK-NEXT: vsetvli a1, zero, e16, m4, tu, mu 1011; CHECK-NEXT: vslideup.vx v8, v12, a0 1012; CHECK-NEXT: ret 1013 %res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 31) 1014 ret <vscale x 16 x i16> %res 1015} 1016 1017declare <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, i32) 1018 1019define <vscale x 32 x i16> @splice_nxv32i16_offset_zero(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 { 1020; CHECK-LABEL: splice_nxv32i16_offset_zero: 1021; CHECK: # %bb.0: 1022; CHECK-NEXT: ret 1023 %res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 0) 1024 ret <vscale x 32 x i16> %res 1025} 1026 1027define <vscale x 32 x i16> @splice_nxv32i16_offset_negone(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 { 1028; CHECK-LABEL: splice_nxv32i16_offset_negone: 1029; CHECK: # %bb.0: 1030; CHECK-NEXT: csrr a0, vlenb 1031; CHECK-NEXT: slli a0, a0, 2 1032; CHECK-NEXT: addi a0, a0, -1 1033; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu 1034; CHECK-NEXT: vslidedown.vx v8, v8, a0 1035; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu 1036; CHECK-NEXT: vslideup.vi v8, v16, 1 1037; CHECK-NEXT: ret 1038 %res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 -1) 1039 ret <vscale x 32 x i16> %res 1040} 1041 1042define <vscale x 32 x i16> @splice_nxv32i16_offset_min(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 { 1043; CHECK-LABEL: splice_nxv32i16_offset_min: 1044; CHECK: # %bb.0: 1045; CHECK-NEXT: csrr a0, vlenb 1046; CHECK-NEXT: slli a0, a0, 2 1047; CHECK-NEXT: addi a0, a0, -64 1048; CHECK-NEXT: li a1, 64 1049; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu 1050; CHECK-NEXT: vslidedown.vx v8, v8, a0 1051; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu 1052; CHECK-NEXT: vslideup.vx v8, v16, a1 1053; CHECK-NEXT: ret 1054 %res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 -64) 1055 ret <vscale x 32 x i16> %res 1056} 1057 1058define <vscale x 32 x i16> @splice_nxv32i16_offset_max(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 { 1059; CHECK-LABEL: splice_nxv32i16_offset_max: 1060; CHECK: # %bb.0: 1061; CHECK-NEXT: csrr a0, vlenb 1062; CHECK-NEXT: slli a0, a0, 2 1063; CHECK-NEXT: addi a0, a0, -63 1064; CHECK-NEXT: li a1, 63 1065; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu 1066; CHECK-NEXT: vslidedown.vx v8, v8, a1 1067; CHECK-NEXT: vsetvli a1, zero, e16, m8, tu, mu 1068; CHECK-NEXT: vslideup.vx v8, v16, a0 1069; CHECK-NEXT: ret 1070 %res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 63) 1071 ret <vscale x 32 x i16> %res 1072} 1073 1074declare <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, i32) 1075 1076define <vscale x 1 x i32> @splice_nxv1i32_offset_zero(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 { 1077; CHECK-LABEL: splice_nxv1i32_offset_zero: 1078; CHECK: # %bb.0: 1079; CHECK-NEXT: ret 1080 %res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 0) 1081 ret <vscale x 1 x i32> %res 1082} 1083 1084define <vscale x 1 x i32> @splice_nxv1i32_offset_negone(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 { 1085; CHECK-LABEL: splice_nxv1i32_offset_negone: 1086; CHECK: # %bb.0: 1087; CHECK-NEXT: csrr a0, vlenb 1088; CHECK-NEXT: srli a0, a0, 3 1089; CHECK-NEXT: addi a0, a0, -1 1090; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu 1091; CHECK-NEXT: vslidedown.vx v8, v8, a0 1092; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu 1093; CHECK-NEXT: vslideup.vi v8, v9, 1 1094; CHECK-NEXT: ret 1095 %res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 -1) 1096 ret <vscale x 1 x i32> %res 1097} 1098 1099define <vscale x 1 x i32> @splice_nxv1i32_offset_min(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 { 1100; CHECK-LABEL: splice_nxv1i32_offset_min: 1101; CHECK: # %bb.0: 1102; CHECK-NEXT: csrr a0, vlenb 1103; CHECK-NEXT: srli a0, a0, 3 1104; CHECK-NEXT: addi a0, a0, -2 1105; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu 1106; CHECK-NEXT: vslidedown.vx v8, v8, a0 1107; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu 1108; CHECK-NEXT: vslideup.vi v8, v9, 2 1109; CHECK-NEXT: ret 1110 %res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 -2) 1111 ret <vscale x 1 x i32> %res 1112} 1113 1114define <vscale x 1 x i32> @splice_nxv1i32_offset_max(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 { 1115; CHECK-LABEL: splice_nxv1i32_offset_max: 1116; CHECK: # %bb.0: 1117; CHECK-NEXT: csrr a0, vlenb 1118; CHECK-NEXT: srli a0, a0, 3 1119; CHECK-NEXT: addi a0, a0, -1 1120; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu 1121; CHECK-NEXT: vslidedown.vi v8, v8, 1 1122; CHECK-NEXT: vsetvli a1, zero, e32, mf2, tu, mu 1123; CHECK-NEXT: vslideup.vx v8, v9, a0 1124; CHECK-NEXT: ret 1125 %res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 1) 1126 ret <vscale x 1 x i32> %res 1127} 1128 1129declare <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, i32) 1130 1131define <vscale x 2 x i32> @splice_nxv2i32_offset_zero(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 { 1132; CHECK-LABEL: splice_nxv2i32_offset_zero: 1133; CHECK: # %bb.0: 1134; CHECK-NEXT: ret 1135 %res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 0) 1136 ret <vscale x 2 x i32> %res 1137} 1138 1139define <vscale x 2 x i32> @splice_nxv2i32_offset_negone(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 { 1140; CHECK-LABEL: splice_nxv2i32_offset_negone: 1141; CHECK: # %bb.0: 1142; CHECK-NEXT: csrr a0, vlenb 1143; CHECK-NEXT: srli a0, a0, 2 1144; CHECK-NEXT: addi a0, a0, -1 1145; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu 1146; CHECK-NEXT: vslidedown.vx v8, v8, a0 1147; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu 1148; CHECK-NEXT: vslideup.vi v8, v9, 1 1149; CHECK-NEXT: ret 1150 %res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 -1) 1151 ret <vscale x 2 x i32> %res 1152} 1153 1154define <vscale x 2 x i32> @splice_nxv2i32_offset_min(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 { 1155; CHECK-LABEL: splice_nxv2i32_offset_min: 1156; CHECK: # %bb.0: 1157; CHECK-NEXT: csrr a0, vlenb 1158; CHECK-NEXT: srli a0, a0, 2 1159; CHECK-NEXT: addi a0, a0, -4 1160; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu 1161; CHECK-NEXT: vslidedown.vx v8, v8, a0 1162; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu 1163; CHECK-NEXT: vslideup.vi v8, v9, 4 1164; CHECK-NEXT: ret 1165 %res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 -4) 1166 ret <vscale x 2 x i32> %res 1167} 1168 1169define <vscale x 2 x i32> @splice_nxv2i32_offset_max(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 { 1170; CHECK-LABEL: splice_nxv2i32_offset_max: 1171; CHECK: # %bb.0: 1172; CHECK-NEXT: csrr a0, vlenb 1173; CHECK-NEXT: srli a0, a0, 2 1174; CHECK-NEXT: addi a0, a0, -3 1175; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu 1176; CHECK-NEXT: vslidedown.vi v8, v8, 3 1177; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, mu 1178; CHECK-NEXT: vslideup.vx v8, v9, a0 1179; CHECK-NEXT: ret 1180 %res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 3) 1181 ret <vscale x 2 x i32> %res 1182} 1183 1184declare <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32) 1185 1186define <vscale x 4 x i32> @splice_nxv4i32_offset_zero(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 { 1187; CHECK-LABEL: splice_nxv4i32_offset_zero: 1188; CHECK: # %bb.0: 1189; CHECK-NEXT: ret 1190 %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 0) 1191 ret <vscale x 4 x i32> %res 1192} 1193 1194define <vscale x 4 x i32> @splice_nxv4i32_offset_negone(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 { 1195; CHECK-LABEL: splice_nxv4i32_offset_negone: 1196; CHECK: # %bb.0: 1197; CHECK-NEXT: csrr a0, vlenb 1198; CHECK-NEXT: srli a0, a0, 1 1199; CHECK-NEXT: addi a0, a0, -1 1200; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu 1201; CHECK-NEXT: vslidedown.vx v8, v8, a0 1202; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu 1203; CHECK-NEXT: vslideup.vi v8, v10, 1 1204; CHECK-NEXT: ret 1205 %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -1) 1206 ret <vscale x 4 x i32> %res 1207} 1208 1209define <vscale x 4 x i32> @splice_nxv4i32_offset_min(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 { 1210; CHECK-LABEL: splice_nxv4i32_offset_min: 1211; CHECK: # %bb.0: 1212; CHECK-NEXT: csrr a0, vlenb 1213; CHECK-NEXT: srli a0, a0, 1 1214; CHECK-NEXT: addi a0, a0, -8 1215; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu 1216; CHECK-NEXT: vslidedown.vx v8, v8, a0 1217; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu 1218; CHECK-NEXT: vslideup.vi v8, v10, 8 1219; CHECK-NEXT: ret 1220 %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -8) 1221 ret <vscale x 4 x i32> %res 1222} 1223 1224define <vscale x 4 x i32> @splice_nxv4i32_offset_max(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 { 1225; CHECK-LABEL: splice_nxv4i32_offset_max: 1226; CHECK: # %bb.0: 1227; CHECK-NEXT: csrr a0, vlenb 1228; CHECK-NEXT: srli a0, a0, 1 1229; CHECK-NEXT: addi a0, a0, -7 1230; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu 1231; CHECK-NEXT: vslidedown.vi v8, v8, 7 1232; CHECK-NEXT: vsetvli a1, zero, e32, m2, tu, mu 1233; CHECK-NEXT: vslideup.vx v8, v10, a0 1234; CHECK-NEXT: ret 1235 %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 7) 1236 ret <vscale x 4 x i32> %res 1237} 1238 1239declare <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, i32) 1240 1241define <vscale x 8 x i32> @splice_nxv8i32_offset_zero(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 { 1242; CHECK-LABEL: splice_nxv8i32_offset_zero: 1243; CHECK: # %bb.0: 1244; CHECK-NEXT: ret 1245 %res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 0) 1246 ret <vscale x 8 x i32> %res 1247} 1248 1249define <vscale x 8 x i32> @splice_nxv8i32_offset_negone(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 { 1250; CHECK-LABEL: splice_nxv8i32_offset_negone: 1251; CHECK: # %bb.0: 1252; CHECK-NEXT: csrr a0, vlenb 1253; CHECK-NEXT: addi a0, a0, -1 1254; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu 1255; CHECK-NEXT: vslidedown.vx v8, v8, a0 1256; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu 1257; CHECK-NEXT: vslideup.vi v8, v12, 1 1258; CHECK-NEXT: ret 1259 %res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -1) 1260 ret <vscale x 8 x i32> %res 1261} 1262 1263define <vscale x 8 x i32> @splice_nxv8i32_offset_min(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 { 1264; CHECK-LABEL: splice_nxv8i32_offset_min: 1265; CHECK: # %bb.0: 1266; CHECK-NEXT: csrr a0, vlenb 1267; CHECK-NEXT: addi a0, a0, -16 1268; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu 1269; CHECK-NEXT: vslidedown.vx v8, v8, a0 1270; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu 1271; CHECK-NEXT: vslideup.vi v8, v12, 16 1272; CHECK-NEXT: ret 1273 %res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -16) 1274 ret <vscale x 8 x i32> %res 1275} 1276 1277define <vscale x 8 x i32> @splice_nxv8i32_offset_max(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 { 1278; CHECK-LABEL: splice_nxv8i32_offset_max: 1279; CHECK: # %bb.0: 1280; CHECK-NEXT: csrr a0, vlenb 1281; CHECK-NEXT: addi a0, a0, -15 1282; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu 1283; CHECK-NEXT: vslidedown.vi v8, v8, 15 1284; CHECK-NEXT: vsetvli a1, zero, e32, m4, tu, mu 1285; CHECK-NEXT: vslideup.vx v8, v12, a0 1286; CHECK-NEXT: ret 1287 %res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 15) 1288 ret <vscale x 8 x i32> %res 1289} 1290 1291declare <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, i32) 1292 1293define <vscale x 16 x i32> @splice_nxv16i32_offset_zero(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 { 1294; CHECK-LABEL: splice_nxv16i32_offset_zero: 1295; CHECK: # %bb.0: 1296; CHECK-NEXT: ret 1297 %res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 0) 1298 ret <vscale x 16 x i32> %res 1299} 1300 1301define <vscale x 16 x i32> @splice_nxv16i32_offset_negone(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 { 1302; CHECK-LABEL: splice_nxv16i32_offset_negone: 1303; CHECK: # %bb.0: 1304; CHECK-NEXT: csrr a0, vlenb 1305; CHECK-NEXT: slli a0, a0, 1 1306; CHECK-NEXT: addi a0, a0, -1 1307; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu 1308; CHECK-NEXT: vslidedown.vx v8, v8, a0 1309; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu 1310; CHECK-NEXT: vslideup.vi v8, v16, 1 1311; CHECK-NEXT: ret 1312 %res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 -1) 1313 ret <vscale x 16 x i32> %res 1314} 1315 1316define <vscale x 16 x i32> @splice_nxv16i32_offset_min(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 { 1317; CHECK-LABEL: splice_nxv16i32_offset_min: 1318; CHECK: # %bb.0: 1319; CHECK-NEXT: csrr a0, vlenb 1320; CHECK-NEXT: slli a0, a0, 1 1321; CHECK-NEXT: addi a0, a0, -32 1322; CHECK-NEXT: li a1, 32 1323; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu 1324; CHECK-NEXT: vslidedown.vx v8, v8, a0 1325; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu 1326; CHECK-NEXT: vslideup.vx v8, v16, a1 1327; CHECK-NEXT: ret 1328 %res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 -32) 1329 ret <vscale x 16 x i32> %res 1330} 1331 1332define <vscale x 16 x i32> @splice_nxv16i32_offset_max(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 { 1333; CHECK-LABEL: splice_nxv16i32_offset_max: 1334; CHECK: # %bb.0: 1335; CHECK-NEXT: csrr a0, vlenb 1336; CHECK-NEXT: slli a0, a0, 1 1337; CHECK-NEXT: addi a0, a0, -31 1338; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu 1339; CHECK-NEXT: vslidedown.vi v8, v8, 31 1340; CHECK-NEXT: vsetvli a1, zero, e32, m8, tu, mu 1341; CHECK-NEXT: vslideup.vx v8, v16, a0 1342; CHECK-NEXT: ret 1343 %res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 31) 1344 ret <vscale x 16 x i32> %res 1345} 1346 1347declare <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i32) 1348 1349define <vscale x 1 x i64> @splice_nxv1i64_offset_zero(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 { 1350; CHECK-LABEL: splice_nxv1i64_offset_zero: 1351; CHECK: # %bb.0: 1352; CHECK-NEXT: ret 1353 %res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 0) 1354 ret <vscale x 1 x i64> %res 1355} 1356 1357define <vscale x 1 x i64> @splice_nxv1i64_offset_negone(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 { 1358; CHECK-LABEL: splice_nxv1i64_offset_negone: 1359; CHECK: # %bb.0: 1360; CHECK-NEXT: csrr a0, vlenb 1361; CHECK-NEXT: srli a0, a0, 3 1362; CHECK-NEXT: addi a0, a0, -1 1363; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu 1364; CHECK-NEXT: vslidedown.vx v8, v8, a0 1365; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu 1366; CHECK-NEXT: vslideup.vi v8, v9, 1 1367; CHECK-NEXT: ret 1368 %res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 -1) 1369 ret <vscale x 1 x i64> %res 1370} 1371 1372define <vscale x 1 x i64> @splice_nxv1i64_offset_min(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 { 1373; CHECK-LABEL: splice_nxv1i64_offset_min: 1374; CHECK: # %bb.0: 1375; CHECK-NEXT: csrr a0, vlenb 1376; CHECK-NEXT: srli a0, a0, 3 1377; CHECK-NEXT: addi a0, a0, -2 1378; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu 1379; CHECK-NEXT: vslidedown.vx v8, v8, a0 1380; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu 1381; CHECK-NEXT: vslideup.vi v8, v9, 2 1382; CHECK-NEXT: ret 1383 %res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 -2) 1384 ret <vscale x 1 x i64> %res 1385} 1386 1387define <vscale x 1 x i64> @splice_nxv1i64_offset_max(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 { 1388; CHECK-LABEL: splice_nxv1i64_offset_max: 1389; CHECK: # %bb.0: 1390; CHECK-NEXT: csrr a0, vlenb 1391; CHECK-NEXT: srli a0, a0, 3 1392; CHECK-NEXT: addi a0, a0, -1 1393; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu 1394; CHECK-NEXT: vslidedown.vi v8, v8, 1 1395; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, mu 1396; CHECK-NEXT: vslideup.vx v8, v9, a0 1397; CHECK-NEXT: ret 1398 %res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 1) 1399 ret <vscale x 1 x i64> %res 1400} 1401 1402declare <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32) 1403 1404define <vscale x 2 x i64> @splice_nxv2i64_offset_zero(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 { 1405; CHECK-LABEL: splice_nxv2i64_offset_zero: 1406; CHECK: # %bb.0: 1407; CHECK-NEXT: ret 1408 %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 0) 1409 ret <vscale x 2 x i64> %res 1410} 1411 1412define <vscale x 2 x i64> @splice_nxv2i64_offset_negone(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 { 1413; CHECK-LABEL: splice_nxv2i64_offset_negone: 1414; CHECK: # %bb.0: 1415; CHECK-NEXT: csrr a0, vlenb 1416; CHECK-NEXT: srli a0, a0, 2 1417; CHECK-NEXT: addi a0, a0, -1 1418; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu 1419; CHECK-NEXT: vslidedown.vx v8, v8, a0 1420; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu 1421; CHECK-NEXT: vslideup.vi v8, v10, 1 1422; CHECK-NEXT: ret 1423 %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -1) 1424 ret <vscale x 2 x i64> %res 1425} 1426 1427define <vscale x 2 x i64> @splice_nxv2i64_offset_min(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 { 1428; CHECK-LABEL: splice_nxv2i64_offset_min: 1429; CHECK: # %bb.0: 1430; CHECK-NEXT: csrr a0, vlenb 1431; CHECK-NEXT: srli a0, a0, 2 1432; CHECK-NEXT: addi a0, a0, -4 1433; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu 1434; CHECK-NEXT: vslidedown.vx v8, v8, a0 1435; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu 1436; CHECK-NEXT: vslideup.vi v8, v10, 4 1437; CHECK-NEXT: ret 1438 %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -4) 1439 ret <vscale x 2 x i64> %res 1440} 1441 1442define <vscale x 2 x i64> @splice_nxv2i64_offset_max(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 { 1443; CHECK-LABEL: splice_nxv2i64_offset_max: 1444; CHECK: # %bb.0: 1445; CHECK-NEXT: csrr a0, vlenb 1446; CHECK-NEXT: srli a0, a0, 2 1447; CHECK-NEXT: addi a0, a0, -3 1448; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu 1449; CHECK-NEXT: vslidedown.vi v8, v8, 3 1450; CHECK-NEXT: vsetvli a1, zero, e64, m2, tu, mu 1451; CHECK-NEXT: vslideup.vx v8, v10, a0 1452; CHECK-NEXT: ret 1453 %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 3) 1454 ret <vscale x 2 x i64> %res 1455} 1456 1457declare <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i32) 1458 1459define <vscale x 4 x i64> @splice_nxv4i64_offset_zero(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 { 1460; CHECK-LABEL: splice_nxv4i64_offset_zero: 1461; CHECK: # %bb.0: 1462; CHECK-NEXT: ret 1463 %res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 0) 1464 ret <vscale x 4 x i64> %res 1465} 1466 1467define <vscale x 4 x i64> @splice_nxv4i64_offset_negone(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 { 1468; CHECK-LABEL: splice_nxv4i64_offset_negone: 1469; CHECK: # %bb.0: 1470; CHECK-NEXT: csrr a0, vlenb 1471; CHECK-NEXT: srli a0, a0, 1 1472; CHECK-NEXT: addi a0, a0, -1 1473; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu 1474; CHECK-NEXT: vslidedown.vx v8, v8, a0 1475; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu 1476; CHECK-NEXT: vslideup.vi v8, v12, 1 1477; CHECK-NEXT: ret 1478 %res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 -1) 1479 ret <vscale x 4 x i64> %res 1480} 1481 1482define <vscale x 4 x i64> @splice_nxv4i64_offset_min(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 { 1483; CHECK-LABEL: splice_nxv4i64_offset_min: 1484; CHECK: # %bb.0: 1485; CHECK-NEXT: csrr a0, vlenb 1486; CHECK-NEXT: srli a0, a0, 1 1487; CHECK-NEXT: addi a0, a0, -8 1488; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu 1489; CHECK-NEXT: vslidedown.vx v8, v8, a0 1490; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu 1491; CHECK-NEXT: vslideup.vi v8, v12, 8 1492; CHECK-NEXT: ret 1493 %res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 -8) 1494 ret <vscale x 4 x i64> %res 1495} 1496 1497define <vscale x 4 x i64> @splice_nxv4i64_offset_max(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 { 1498; CHECK-LABEL: splice_nxv4i64_offset_max: 1499; CHECK: # %bb.0: 1500; CHECK-NEXT: csrr a0, vlenb 1501; CHECK-NEXT: srli a0, a0, 1 1502; CHECK-NEXT: addi a0, a0, -7 1503; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu 1504; CHECK-NEXT: vslidedown.vi v8, v8, 7 1505; CHECK-NEXT: vsetvli a1, zero, e64, m4, tu, mu 1506; CHECK-NEXT: vslideup.vx v8, v12, a0 1507; CHECK-NEXT: ret 1508 %res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 7) 1509 ret <vscale x 4 x i64> %res 1510} 1511 1512declare <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i32) 1513 1514define <vscale x 8 x i64> @splice_nxv8i64_offset_zero(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 { 1515; CHECK-LABEL: splice_nxv8i64_offset_zero: 1516; CHECK: # %bb.0: 1517; CHECK-NEXT: ret 1518 %res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 0) 1519 ret <vscale x 8 x i64> %res 1520} 1521 1522define <vscale x 8 x i64> @splice_nxv8i64_offset_negone(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 { 1523; CHECK-LABEL: splice_nxv8i64_offset_negone: 1524; CHECK: # %bb.0: 1525; CHECK-NEXT: csrr a0, vlenb 1526; CHECK-NEXT: addi a0, a0, -1 1527; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu 1528; CHECK-NEXT: vslidedown.vx v8, v8, a0 1529; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu 1530; CHECK-NEXT: vslideup.vi v8, v16, 1 1531; CHECK-NEXT: ret 1532 %res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 -1) 1533 ret <vscale x 8 x i64> %res 1534} 1535 1536define <vscale x 8 x i64> @splice_nxv8i64_offset_min(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 { 1537; CHECK-LABEL: splice_nxv8i64_offset_min: 1538; CHECK: # %bb.0: 1539; CHECK-NEXT: csrr a0, vlenb 1540; CHECK-NEXT: addi a0, a0, -16 1541; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu 1542; CHECK-NEXT: vslidedown.vx v8, v8, a0 1543; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu 1544; CHECK-NEXT: vslideup.vi v8, v16, 16 1545; CHECK-NEXT: ret 1546 %res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 -16) 1547 ret <vscale x 8 x i64> %res 1548} 1549 1550define <vscale x 8 x i64> @splice_nxv8i64_offset_max(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 { 1551; CHECK-LABEL: splice_nxv8i64_offset_max: 1552; CHECK: # %bb.0: 1553; CHECK-NEXT: csrr a0, vlenb 1554; CHECK-NEXT: addi a0, a0, -15 1555; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu 1556; CHECK-NEXT: vslidedown.vi v8, v8, 15 1557; CHECK-NEXT: vsetvli a1, zero, e64, m8, tu, mu 1558; CHECK-NEXT: vslideup.vx v8, v16, a0 1559; CHECK-NEXT: ret 1560 %res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 15) 1561 ret <vscale x 8 x i64> %res 1562} 1563 1564declare <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half>, <vscale x 1 x half>, i32) 1565 1566define <vscale x 1 x half> @splice_nxv1f16_offset_zero(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 { 1567; CHECK-LABEL: splice_nxv1f16_offset_zero: 1568; CHECK: # %bb.0: 1569; CHECK-NEXT: ret 1570 %res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 0) 1571 ret <vscale x 1 x half> %res 1572} 1573 1574define <vscale x 1 x half> @splice_nxv1f16_offset_negone(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 { 1575; CHECK-LABEL: splice_nxv1f16_offset_negone: 1576; CHECK: # %bb.0: 1577; CHECK-NEXT: csrr a0, vlenb 1578; CHECK-NEXT: srli a0, a0, 3 1579; CHECK-NEXT: addi a0, a0, -1 1580; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu 1581; CHECK-NEXT: vslidedown.vx v8, v8, a0 1582; CHECK-NEXT: vsetvli a0, zero, e16, mf4, tu, mu 1583; CHECK-NEXT: vslideup.vi v8, v9, 1 1584; CHECK-NEXT: ret 1585 %res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 -1) 1586 ret <vscale x 1 x half> %res 1587} 1588 1589define <vscale x 1 x half> @splice_nxv1f16_offset_min(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 { 1590; CHECK-LABEL: splice_nxv1f16_offset_min: 1591; CHECK: # %bb.0: 1592; CHECK-NEXT: csrr a0, vlenb 1593; CHECK-NEXT: srli a0, a0, 3 1594; CHECK-NEXT: addi a0, a0, -2 1595; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu 1596; CHECK-NEXT: vslidedown.vx v8, v8, a0 1597; CHECK-NEXT: vsetvli a0, zero, e16, mf4, tu, mu 1598; CHECK-NEXT: vslideup.vi v8, v9, 2 1599; CHECK-NEXT: ret 1600 %res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 -2) 1601 ret <vscale x 1 x half> %res 1602} 1603 1604define <vscale x 1 x half> @splice_nxv1f16_offset_max(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 { 1605; CHECK-LABEL: splice_nxv1f16_offset_max: 1606; CHECK: # %bb.0: 1607; CHECK-NEXT: csrr a0, vlenb 1608; CHECK-NEXT: srli a0, a0, 3 1609; CHECK-NEXT: addi a0, a0, -1 1610; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu 1611; CHECK-NEXT: vslidedown.vi v8, v8, 1 1612; CHECK-NEXT: vsetvli a1, zero, e16, mf4, tu, mu 1613; CHECK-NEXT: vslideup.vx v8, v9, a0 1614; CHECK-NEXT: ret 1615 %res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 1) 1616 ret <vscale x 1 x half> %res 1617} 1618 1619declare <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>, i32) 1620 1621define <vscale x 2 x half> @splice_nxv2f16_offset_zero(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 { 1622; CHECK-LABEL: splice_nxv2f16_offset_zero: 1623; CHECK: # %bb.0: 1624; CHECK-NEXT: ret 1625 %res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 0) 1626 ret <vscale x 2 x half> %res 1627} 1628 1629define <vscale x 2 x half> @splice_nxv2f16_offset_negone(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 { 1630; CHECK-LABEL: splice_nxv2f16_offset_negone: 1631; CHECK: # %bb.0: 1632; CHECK-NEXT: csrr a0, vlenb 1633; CHECK-NEXT: srli a0, a0, 2 1634; CHECK-NEXT: addi a0, a0, -1 1635; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu 1636; CHECK-NEXT: vslidedown.vx v8, v8, a0 1637; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu 1638; CHECK-NEXT: vslideup.vi v8, v9, 1 1639; CHECK-NEXT: ret 1640 %res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -1) 1641 ret <vscale x 2 x half> %res 1642} 1643 1644define <vscale x 2 x half> @splice_nxv2f16_offset_min(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 { 1645; CHECK-LABEL: splice_nxv2f16_offset_min: 1646; CHECK: # %bb.0: 1647; CHECK-NEXT: csrr a0, vlenb 1648; CHECK-NEXT: srli a0, a0, 2 1649; CHECK-NEXT: addi a0, a0, -4 1650; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu 1651; CHECK-NEXT: vslidedown.vx v8, v8, a0 1652; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu 1653; CHECK-NEXT: vslideup.vi v8, v9, 4 1654; CHECK-NEXT: ret 1655 %res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -4) 1656 ret <vscale x 2 x half> %res 1657} 1658 1659define <vscale x 2 x half> @splice_nxv2f16_offset_max(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 { 1660; CHECK-LABEL: splice_nxv2f16_offset_max: 1661; CHECK: # %bb.0: 1662; CHECK-NEXT: csrr a0, vlenb 1663; CHECK-NEXT: srli a0, a0, 2 1664; CHECK-NEXT: addi a0, a0, -3 1665; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu 1666; CHECK-NEXT: vslidedown.vi v8, v8, 3 1667; CHECK-NEXT: vsetvli a1, zero, e16, mf2, tu, mu 1668; CHECK-NEXT: vslideup.vx v8, v9, a0 1669; CHECK-NEXT: ret 1670 %res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 3) 1671 ret <vscale x 2 x half> %res 1672} 1673 1674declare <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>, i32) 1675 1676define <vscale x 4 x half> @splice_nxv4f16_offset_zero(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 { 1677; CHECK-LABEL: splice_nxv4f16_offset_zero: 1678; CHECK: # %bb.0: 1679; CHECK-NEXT: ret 1680 %res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 0) 1681 ret <vscale x 4 x half> %res 1682} 1683 1684define <vscale x 4 x half> @splice_nxv4f16_offset_negone(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 { 1685; CHECK-LABEL: splice_nxv4f16_offset_negone: 1686; CHECK: # %bb.0: 1687; CHECK-NEXT: csrr a0, vlenb 1688; CHECK-NEXT: srli a0, a0, 1 1689; CHECK-NEXT: addi a0, a0, -1 1690; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu 1691; CHECK-NEXT: vslidedown.vx v8, v8, a0 1692; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu 1693; CHECK-NEXT: vslideup.vi v8, v9, 1 1694; CHECK-NEXT: ret 1695 %res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -1) 1696 ret <vscale x 4 x half> %res 1697} 1698 1699define <vscale x 4 x half> @splice_nxv4f16_offset_min(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 { 1700; CHECK-LABEL: splice_nxv4f16_offset_min: 1701; CHECK: # %bb.0: 1702; CHECK-NEXT: csrr a0, vlenb 1703; CHECK-NEXT: srli a0, a0, 1 1704; CHECK-NEXT: addi a0, a0, -8 1705; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu 1706; CHECK-NEXT: vslidedown.vx v8, v8, a0 1707; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu 1708; CHECK-NEXT: vslideup.vi v8, v9, 8 1709; CHECK-NEXT: ret 1710 %res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -8) 1711 ret <vscale x 4 x half> %res 1712} 1713 1714define <vscale x 4 x half> @splice_nxv4f16_offset_max(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 { 1715; CHECK-LABEL: splice_nxv4f16_offset_max: 1716; CHECK: # %bb.0: 1717; CHECK-NEXT: csrr a0, vlenb 1718; CHECK-NEXT: srli a0, a0, 1 1719; CHECK-NEXT: addi a0, a0, -7 1720; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu 1721; CHECK-NEXT: vslidedown.vi v8, v8, 7 1722; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, mu 1723; CHECK-NEXT: vslideup.vx v8, v9, a0 1724; CHECK-NEXT: ret 1725 %res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 7) 1726 ret <vscale x 4 x half> %res 1727} 1728 1729declare <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32) 1730 1731define <vscale x 8 x half> @splice_nxv8f16_offset_zero(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 { 1732; CHECK-LABEL: splice_nxv8f16_offset_zero: 1733; CHECK: # %bb.0: 1734; CHECK-NEXT: ret 1735 %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 0) 1736 ret <vscale x 8 x half> %res 1737} 1738 1739define <vscale x 8 x half> @splice_nxv8f16_offset_negone(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 { 1740; CHECK-LABEL: splice_nxv8f16_offset_negone: 1741; CHECK: # %bb.0: 1742; CHECK-NEXT: csrr a0, vlenb 1743; CHECK-NEXT: addi a0, a0, -1 1744; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu 1745; CHECK-NEXT: vslidedown.vx v8, v8, a0 1746; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu 1747; CHECK-NEXT: vslideup.vi v8, v10, 1 1748; CHECK-NEXT: ret 1749 %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -1) 1750 ret <vscale x 8 x half> %res 1751} 1752 1753define <vscale x 8 x half> @splice_nxv8f16_offset_min(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 { 1754; CHECK-LABEL: splice_nxv8f16_offset_min: 1755; CHECK: # %bb.0: 1756; CHECK-NEXT: csrr a0, vlenb 1757; CHECK-NEXT: addi a0, a0, -16 1758; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu 1759; CHECK-NEXT: vslidedown.vx v8, v8, a0 1760; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu 1761; CHECK-NEXT: vslideup.vi v8, v10, 16 1762; CHECK-NEXT: ret 1763 %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -16) 1764 ret <vscale x 8 x half> %res 1765} 1766 1767define <vscale x 8 x half> @splice_nxv8f16_offset_max(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 { 1768; CHECK-LABEL: splice_nxv8f16_offset_max: 1769; CHECK: # %bb.0: 1770; CHECK-NEXT: csrr a0, vlenb 1771; CHECK-NEXT: addi a0, a0, -15 1772; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu 1773; CHECK-NEXT: vslidedown.vi v8, v8, 15 1774; CHECK-NEXT: vsetvli a1, zero, e16, m2, tu, mu 1775; CHECK-NEXT: vslideup.vx v8, v10, a0 1776; CHECK-NEXT: ret 1777 %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 15) 1778 ret <vscale x 8 x half> %res 1779} 1780 1781declare <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half>, <vscale x 16 x half>, i32) 1782 1783define <vscale x 16 x half> @splice_nxv16f16_offset_zero(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 { 1784; CHECK-LABEL: splice_nxv16f16_offset_zero: 1785; CHECK: # %bb.0: 1786; CHECK-NEXT: ret 1787 %res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 0) 1788 ret <vscale x 16 x half> %res 1789} 1790 1791define <vscale x 16 x half> @splice_nxv16f16_offset_negone(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 { 1792; CHECK-LABEL: splice_nxv16f16_offset_negone: 1793; CHECK: # %bb.0: 1794; CHECK-NEXT: csrr a0, vlenb 1795; CHECK-NEXT: slli a0, a0, 1 1796; CHECK-NEXT: addi a0, a0, -1 1797; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu 1798; CHECK-NEXT: vslidedown.vx v8, v8, a0 1799; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu 1800; CHECK-NEXT: vslideup.vi v8, v12, 1 1801; CHECK-NEXT: ret 1802 %res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 -1) 1803 ret <vscale x 16 x half> %res 1804} 1805 1806define <vscale x 16 x half> @splice_nxv16f16_offset_min(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 { 1807; CHECK-LABEL: splice_nxv16f16_offset_min: 1808; CHECK: # %bb.0: 1809; CHECK-NEXT: csrr a0, vlenb 1810; CHECK-NEXT: slli a0, a0, 1 1811; CHECK-NEXT: addi a0, a0, -32 1812; CHECK-NEXT: li a1, 32 1813; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu 1814; CHECK-NEXT: vslidedown.vx v8, v8, a0 1815; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu 1816; CHECK-NEXT: vslideup.vx v8, v12, a1 1817; CHECK-NEXT: ret 1818 %res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 -32) 1819 ret <vscale x 16 x half> %res 1820} 1821 1822define <vscale x 16 x half> @splice_nxv16f16_offset_max(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 { 1823; CHECK-LABEL: splice_nxv16f16_offset_max: 1824; CHECK: # %bb.0: 1825; CHECK-NEXT: csrr a0, vlenb 1826; CHECK-NEXT: slli a0, a0, 1 1827; CHECK-NEXT: addi a0, a0, -31 1828; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu 1829; CHECK-NEXT: vslidedown.vi v8, v8, 31 1830; CHECK-NEXT: vsetvli a1, zero, e16, m4, tu, mu 1831; CHECK-NEXT: vslideup.vx v8, v12, a0 1832; CHECK-NEXT: ret 1833 %res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 31) 1834 ret <vscale x 16 x half> %res 1835} 1836 1837declare <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half>, <vscale x 32 x half>, i32) 1838 1839define <vscale x 32 x half> @splice_nxv32f16_offset_zero(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 { 1840; CHECK-LABEL: splice_nxv32f16_offset_zero: 1841; CHECK: # %bb.0: 1842; CHECK-NEXT: ret 1843 %res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 0) 1844 ret <vscale x 32 x half> %res 1845} 1846 1847define <vscale x 32 x half> @splice_nxv32f16_offset_negone(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 { 1848; CHECK-LABEL: splice_nxv32f16_offset_negone: 1849; CHECK: # %bb.0: 1850; CHECK-NEXT: csrr a0, vlenb 1851; CHECK-NEXT: slli a0, a0, 2 1852; CHECK-NEXT: addi a0, a0, -1 1853; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu 1854; CHECK-NEXT: vslidedown.vx v8, v8, a0 1855; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu 1856; CHECK-NEXT: vslideup.vi v8, v16, 1 1857; CHECK-NEXT: ret 1858 %res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 -1) 1859 ret <vscale x 32 x half> %res 1860} 1861 1862define <vscale x 32 x half> @splice_nxv32f16_offset_min(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 { 1863; CHECK-LABEL: splice_nxv32f16_offset_min: 1864; CHECK: # %bb.0: 1865; CHECK-NEXT: csrr a0, vlenb 1866; CHECK-NEXT: slli a0, a0, 2 1867; CHECK-NEXT: addi a0, a0, -64 1868; CHECK-NEXT: li a1, 64 1869; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu 1870; CHECK-NEXT: vslidedown.vx v8, v8, a0 1871; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu 1872; CHECK-NEXT: vslideup.vx v8, v16, a1 1873; CHECK-NEXT: ret 1874 %res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 -64) 1875 ret <vscale x 32 x half> %res 1876} 1877 1878define <vscale x 32 x half> @splice_nxv32f16_offset_max(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 { 1879; CHECK-LABEL: splice_nxv32f16_offset_max: 1880; CHECK: # %bb.0: 1881; CHECK-NEXT: csrr a0, vlenb 1882; CHECK-NEXT: slli a0, a0, 2 1883; CHECK-NEXT: addi a0, a0, -63 1884; CHECK-NEXT: li a1, 63 1885; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu 1886; CHECK-NEXT: vslidedown.vx v8, v8, a1 1887; CHECK-NEXT: vsetvli a1, zero, e16, m8, tu, mu 1888; CHECK-NEXT: vslideup.vx v8, v16, a0 1889; CHECK-NEXT: ret 1890 %res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 63) 1891 ret <vscale x 32 x half> %res 1892} 1893 1894declare <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float>, <vscale x 1 x float>, i32) 1895 1896define <vscale x 1 x float> @splice_nxv1f32_offset_zero(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 { 1897; CHECK-LABEL: splice_nxv1f32_offset_zero: 1898; CHECK: # %bb.0: 1899; CHECK-NEXT: ret 1900 %res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 0) 1901 ret <vscale x 1 x float> %res 1902} 1903 1904define <vscale x 1 x float> @splice_nxv1f32_offset_negone(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 { 1905; CHECK-LABEL: splice_nxv1f32_offset_negone: 1906; CHECK: # %bb.0: 1907; CHECK-NEXT: csrr a0, vlenb 1908; CHECK-NEXT: srli a0, a0, 3 1909; CHECK-NEXT: addi a0, a0, -1 1910; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu 1911; CHECK-NEXT: vslidedown.vx v8, v8, a0 1912; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu 1913; CHECK-NEXT: vslideup.vi v8, v9, 1 1914; CHECK-NEXT: ret 1915 %res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 -1) 1916 ret <vscale x 1 x float> %res 1917} 1918 1919define <vscale x 1 x float> @splice_nxv1f32_offset_min(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 { 1920; CHECK-LABEL: splice_nxv1f32_offset_min: 1921; CHECK: # %bb.0: 1922; CHECK-NEXT: csrr a0, vlenb 1923; CHECK-NEXT: srli a0, a0, 3 1924; CHECK-NEXT: addi a0, a0, -2 1925; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu 1926; CHECK-NEXT: vslidedown.vx v8, v8, a0 1927; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu 1928; CHECK-NEXT: vslideup.vi v8, v9, 2 1929; CHECK-NEXT: ret 1930 %res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 -2) 1931 ret <vscale x 1 x float> %res 1932} 1933 1934define <vscale x 1 x float> @splice_nxv1f32_offset_max(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 { 1935; CHECK-LABEL: splice_nxv1f32_offset_max: 1936; CHECK: # %bb.0: 1937; CHECK-NEXT: csrr a0, vlenb 1938; CHECK-NEXT: srli a0, a0, 3 1939; CHECK-NEXT: addi a0, a0, -1 1940; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu 1941; CHECK-NEXT: vslidedown.vi v8, v8, 1 1942; CHECK-NEXT: vsetvli a1, zero, e32, mf2, tu, mu 1943; CHECK-NEXT: vslideup.vx v8, v9, a0 1944; CHECK-NEXT: ret 1945 %res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 1) 1946 ret <vscale x 1 x float> %res 1947} 1948 1949declare <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, i32) 1950 1951define <vscale x 2 x float> @splice_nxv2f32_offset_zero(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 { 1952; CHECK-LABEL: splice_nxv2f32_offset_zero: 1953; CHECK: # %bb.0: 1954; CHECK-NEXT: ret 1955 %res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 0) 1956 ret <vscale x 2 x float> %res 1957} 1958 1959define <vscale x 2 x float> @splice_nxv2f32_offset_negone(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 { 1960; CHECK-LABEL: splice_nxv2f32_offset_negone: 1961; CHECK: # %bb.0: 1962; CHECK-NEXT: csrr a0, vlenb 1963; CHECK-NEXT: srli a0, a0, 2 1964; CHECK-NEXT: addi a0, a0, -1 1965; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu 1966; CHECK-NEXT: vslidedown.vx v8, v8, a0 1967; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu 1968; CHECK-NEXT: vslideup.vi v8, v9, 1 1969; CHECK-NEXT: ret 1970 %res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -1) 1971 ret <vscale x 2 x float> %res 1972} 1973 1974define <vscale x 2 x float> @splice_nxv2f32_offset_min(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 { 1975; CHECK-LABEL: splice_nxv2f32_offset_min: 1976; CHECK: # %bb.0: 1977; CHECK-NEXT: csrr a0, vlenb 1978; CHECK-NEXT: srli a0, a0, 2 1979; CHECK-NEXT: addi a0, a0, -4 1980; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu 1981; CHECK-NEXT: vslidedown.vx v8, v8, a0 1982; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu 1983; CHECK-NEXT: vslideup.vi v8, v9, 4 1984; CHECK-NEXT: ret 1985 %res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -4) 1986 ret <vscale x 2 x float> %res 1987} 1988 1989define <vscale x 2 x float> @splice_nxv2f32_offset_max(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 { 1990; CHECK-LABEL: splice_nxv2f32_offset_max: 1991; CHECK: # %bb.0: 1992; CHECK-NEXT: csrr a0, vlenb 1993; CHECK-NEXT: srli a0, a0, 2 1994; CHECK-NEXT: addi a0, a0, -3 1995; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu 1996; CHECK-NEXT: vslidedown.vi v8, v8, 3 1997; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, mu 1998; CHECK-NEXT: vslideup.vx v8, v9, a0 1999; CHECK-NEXT: ret 2000 %res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 3) 2001 ret <vscale x 2 x float> %res 2002} 2003 2004declare <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32) 2005 2006define <vscale x 4 x float> @splice_nxv4f32_offset_zero(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 { 2007; CHECK-LABEL: splice_nxv4f32_offset_zero: 2008; CHECK: # %bb.0: 2009; CHECK-NEXT: ret 2010 %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 0) 2011 ret <vscale x 4 x float> %res 2012} 2013 2014define <vscale x 4 x float> @splice_nxv4f32_offset_negone(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 { 2015; CHECK-LABEL: splice_nxv4f32_offset_negone: 2016; CHECK: # %bb.0: 2017; CHECK-NEXT: csrr a0, vlenb 2018; CHECK-NEXT: srli a0, a0, 1 2019; CHECK-NEXT: addi a0, a0, -1 2020; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu 2021; CHECK-NEXT: vslidedown.vx v8, v8, a0 2022; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu 2023; CHECK-NEXT: vslideup.vi v8, v10, 1 2024; CHECK-NEXT: ret 2025 %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -1) 2026 ret <vscale x 4 x float> %res 2027} 2028 2029define <vscale x 4 x float> @splice_nxv4f32_offset_min(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 { 2030; CHECK-LABEL: splice_nxv4f32_offset_min: 2031; CHECK: # %bb.0: 2032; CHECK-NEXT: csrr a0, vlenb 2033; CHECK-NEXT: srli a0, a0, 1 2034; CHECK-NEXT: addi a0, a0, -8 2035; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu 2036; CHECK-NEXT: vslidedown.vx v8, v8, a0 2037; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu 2038; CHECK-NEXT: vslideup.vi v8, v10, 8 2039; CHECK-NEXT: ret 2040 %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -8) 2041 ret <vscale x 4 x float> %res 2042} 2043 2044define <vscale x 4 x float> @splice_nxv4f32_offset_max(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 { 2045; CHECK-LABEL: splice_nxv4f32_offset_max: 2046; CHECK: # %bb.0: 2047; CHECK-NEXT: csrr a0, vlenb 2048; CHECK-NEXT: srli a0, a0, 1 2049; CHECK-NEXT: addi a0, a0, -7 2050; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu 2051; CHECK-NEXT: vslidedown.vi v8, v8, 7 2052; CHECK-NEXT: vsetvli a1, zero, e32, m2, tu, mu 2053; CHECK-NEXT: vslideup.vx v8, v10, a0 2054; CHECK-NEXT: ret 2055 %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 7) 2056 ret <vscale x 4 x float> %res 2057} 2058 2059declare <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float>, <vscale x 8 x float>, i32) 2060 2061define <vscale x 8 x float> @splice_nxv8f32_offset_zero(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 { 2062; CHECK-LABEL: splice_nxv8f32_offset_zero: 2063; CHECK: # %bb.0: 2064; CHECK-NEXT: ret 2065 %res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 0) 2066 ret <vscale x 8 x float> %res 2067} 2068 2069define <vscale x 8 x float> @splice_nxv8f32_offset_negone(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 { 2070; CHECK-LABEL: splice_nxv8f32_offset_negone: 2071; CHECK: # %bb.0: 2072; CHECK-NEXT: csrr a0, vlenb 2073; CHECK-NEXT: addi a0, a0, -1 2074; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu 2075; CHECK-NEXT: vslidedown.vx v8, v8, a0 2076; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu 2077; CHECK-NEXT: vslideup.vi v8, v12, 1 2078; CHECK-NEXT: ret 2079 %res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 -1) 2080 ret <vscale x 8 x float> %res 2081} 2082 2083define <vscale x 8 x float> @splice_nxv8f32_offset_min(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 { 2084; CHECK-LABEL: splice_nxv8f32_offset_min: 2085; CHECK: # %bb.0: 2086; CHECK-NEXT: csrr a0, vlenb 2087; CHECK-NEXT: addi a0, a0, -16 2088; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu 2089; CHECK-NEXT: vslidedown.vx v8, v8, a0 2090; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu 2091; CHECK-NEXT: vslideup.vi v8, v12, 16 2092; CHECK-NEXT: ret 2093 %res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 -16) 2094 ret <vscale x 8 x float> %res 2095} 2096 2097define <vscale x 8 x float> @splice_nxv8f32_offset_max(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 { 2098; CHECK-LABEL: splice_nxv8f32_offset_max: 2099; CHECK: # %bb.0: 2100; CHECK-NEXT: csrr a0, vlenb 2101; CHECK-NEXT: addi a0, a0, -15 2102; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu 2103; CHECK-NEXT: vslidedown.vi v8, v8, 15 2104; CHECK-NEXT: vsetvli a1, zero, e32, m4, tu, mu 2105; CHECK-NEXT: vslideup.vx v8, v12, a0 2106; CHECK-NEXT: ret 2107 %res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 15) 2108 ret <vscale x 8 x float> %res 2109} 2110 2111declare <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float>, <vscale x 16 x float>, i32) 2112 2113define <vscale x 16 x float> @splice_nxv16f32_offset_zero(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 { 2114; CHECK-LABEL: splice_nxv16f32_offset_zero: 2115; CHECK: # %bb.0: 2116; CHECK-NEXT: ret 2117 %res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 0) 2118 ret <vscale x 16 x float> %res 2119} 2120 2121define <vscale x 16 x float> @splice_nxv16f32_offset_negone(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 { 2122; CHECK-LABEL: splice_nxv16f32_offset_negone: 2123; CHECK: # %bb.0: 2124; CHECK-NEXT: csrr a0, vlenb 2125; CHECK-NEXT: slli a0, a0, 1 2126; CHECK-NEXT: addi a0, a0, -1 2127; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu 2128; CHECK-NEXT: vslidedown.vx v8, v8, a0 2129; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu 2130; CHECK-NEXT: vslideup.vi v8, v16, 1 2131; CHECK-NEXT: ret 2132 %res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 -1) 2133 ret <vscale x 16 x float> %res 2134} 2135 2136define <vscale x 16 x float> @splice_nxv16f32_offset_min(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 { 2137; CHECK-LABEL: splice_nxv16f32_offset_min: 2138; CHECK: # %bb.0: 2139; CHECK-NEXT: csrr a0, vlenb 2140; CHECK-NEXT: slli a0, a0, 1 2141; CHECK-NEXT: addi a0, a0, -32 2142; CHECK-NEXT: li a1, 32 2143; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu 2144; CHECK-NEXT: vslidedown.vx v8, v8, a0 2145; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu 2146; CHECK-NEXT: vslideup.vx v8, v16, a1 2147; CHECK-NEXT: ret 2148 %res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 -32) 2149 ret <vscale x 16 x float> %res 2150} 2151 2152define <vscale x 16 x float> @splice_nxv16f32_offset_max(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 { 2153; CHECK-LABEL: splice_nxv16f32_offset_max: 2154; CHECK: # %bb.0: 2155; CHECK-NEXT: csrr a0, vlenb 2156; CHECK-NEXT: slli a0, a0, 1 2157; CHECK-NEXT: addi a0, a0, -31 2158; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu 2159; CHECK-NEXT: vslidedown.vi v8, v8, 31 2160; CHECK-NEXT: vsetvli a1, zero, e32, m8, tu, mu 2161; CHECK-NEXT: vslideup.vx v8, v16, a0 2162; CHECK-NEXT: ret 2163 %res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 31) 2164 ret <vscale x 16 x float> %res 2165} 2166 2167declare <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i32) 2168 2169define <vscale x 1 x double> @splice_nxv1f64_offset_zero(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 { 2170; CHECK-LABEL: splice_nxv1f64_offset_zero: 2171; CHECK: # %bb.0: 2172; CHECK-NEXT: ret 2173 %res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 0) 2174 ret <vscale x 1 x double> %res 2175} 2176 2177define <vscale x 1 x double> @splice_nxv1f64_offset_negone(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 { 2178; CHECK-LABEL: splice_nxv1f64_offset_negone: 2179; CHECK: # %bb.0: 2180; CHECK-NEXT: csrr a0, vlenb 2181; CHECK-NEXT: srli a0, a0, 3 2182; CHECK-NEXT: addi a0, a0, -1 2183; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu 2184; CHECK-NEXT: vslidedown.vx v8, v8, a0 2185; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu 2186; CHECK-NEXT: vslideup.vi v8, v9, 1 2187; CHECK-NEXT: ret 2188 %res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 -1) 2189 ret <vscale x 1 x double> %res 2190} 2191 2192define <vscale x 1 x double> @splice_nxv1f64_offset_min(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 { 2193; CHECK-LABEL: splice_nxv1f64_offset_min: 2194; CHECK: # %bb.0: 2195; CHECK-NEXT: csrr a0, vlenb 2196; CHECK-NEXT: srli a0, a0, 3 2197; CHECK-NEXT: addi a0, a0, -2 2198; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu 2199; CHECK-NEXT: vslidedown.vx v8, v8, a0 2200; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu 2201; CHECK-NEXT: vslideup.vi v8, v9, 2 2202; CHECK-NEXT: ret 2203 %res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 -2) 2204 ret <vscale x 1 x double> %res 2205} 2206 2207define <vscale x 1 x double> @splice_nxv1f64_offset_max(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 { 2208; CHECK-LABEL: splice_nxv1f64_offset_max: 2209; CHECK: # %bb.0: 2210; CHECK-NEXT: csrr a0, vlenb 2211; CHECK-NEXT: srli a0, a0, 3 2212; CHECK-NEXT: addi a0, a0, -1 2213; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu 2214; CHECK-NEXT: vslidedown.vi v8, v8, 1 2215; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, mu 2216; CHECK-NEXT: vslideup.vx v8, v9, a0 2217; CHECK-NEXT: ret 2218 %res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 1) 2219 ret <vscale x 1 x double> %res 2220} 2221 2222declare <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32) 2223 2224define <vscale x 2 x double> @splice_nxv2f64_offset_zero(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 { 2225; CHECK-LABEL: splice_nxv2f64_offset_zero: 2226; CHECK: # %bb.0: 2227; CHECK-NEXT: ret 2228 %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 0) 2229 ret <vscale x 2 x double> %res 2230} 2231 2232define <vscale x 2 x double> @splice_nxv2f64_offset_negone(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 { 2233; CHECK-LABEL: splice_nxv2f64_offset_negone: 2234; CHECK: # %bb.0: 2235; CHECK-NEXT: csrr a0, vlenb 2236; CHECK-NEXT: srli a0, a0, 2 2237; CHECK-NEXT: addi a0, a0, -1 2238; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu 2239; CHECK-NEXT: vslidedown.vx v8, v8, a0 2240; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu 2241; CHECK-NEXT: vslideup.vi v8, v10, 1 2242; CHECK-NEXT: ret 2243 %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -1) 2244 ret <vscale x 2 x double> %res 2245} 2246 2247define <vscale x 2 x double> @splice_nxv2f64_offset_min(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 { 2248; CHECK-LABEL: splice_nxv2f64_offset_min: 2249; CHECK: # %bb.0: 2250; CHECK-NEXT: csrr a0, vlenb 2251; CHECK-NEXT: srli a0, a0, 2 2252; CHECK-NEXT: addi a0, a0, -4 2253; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu 2254; CHECK-NEXT: vslidedown.vx v8, v8, a0 2255; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu 2256; CHECK-NEXT: vslideup.vi v8, v10, 4 2257; CHECK-NEXT: ret 2258 %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -4) 2259 ret <vscale x 2 x double> %res 2260} 2261 2262define <vscale x 2 x double> @splice_nxv2f64_offset_max(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 { 2263; CHECK-LABEL: splice_nxv2f64_offset_max: 2264; CHECK: # %bb.0: 2265; CHECK-NEXT: csrr a0, vlenb 2266; CHECK-NEXT: srli a0, a0, 2 2267; CHECK-NEXT: addi a0, a0, -3 2268; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu 2269; CHECK-NEXT: vslidedown.vi v8, v8, 3 2270; CHECK-NEXT: vsetvli a1, zero, e64, m2, tu, mu 2271; CHECK-NEXT: vslideup.vx v8, v10, a0 2272; CHECK-NEXT: ret 2273 %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 3) 2274 ret <vscale x 2 x double> %res 2275} 2276 2277declare <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double>, <vscale x 4 x double>, i32) 2278 2279define <vscale x 4 x double> @splice_nxv4f64_offset_zero(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 { 2280; CHECK-LABEL: splice_nxv4f64_offset_zero: 2281; CHECK: # %bb.0: 2282; CHECK-NEXT: ret 2283 %res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 0) 2284 ret <vscale x 4 x double> %res 2285} 2286 2287define <vscale x 4 x double> @splice_nxv4f64_offset_negone(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 { 2288; CHECK-LABEL: splice_nxv4f64_offset_negone: 2289; CHECK: # %bb.0: 2290; CHECK-NEXT: csrr a0, vlenb 2291; CHECK-NEXT: srli a0, a0, 1 2292; CHECK-NEXT: addi a0, a0, -1 2293; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu 2294; CHECK-NEXT: vslidedown.vx v8, v8, a0 2295; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu 2296; CHECK-NEXT: vslideup.vi v8, v12, 1 2297; CHECK-NEXT: ret 2298 %res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 -1) 2299 ret <vscale x 4 x double> %res 2300} 2301 2302define <vscale x 4 x double> @splice_nxv4f64_offset_min(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 { 2303; CHECK-LABEL: splice_nxv4f64_offset_min: 2304; CHECK: # %bb.0: 2305; CHECK-NEXT: csrr a0, vlenb 2306; CHECK-NEXT: srli a0, a0, 1 2307; CHECK-NEXT: addi a0, a0, -8 2308; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu 2309; CHECK-NEXT: vslidedown.vx v8, v8, a0 2310; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu 2311; CHECK-NEXT: vslideup.vi v8, v12, 8 2312; CHECK-NEXT: ret 2313 %res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 -8) 2314 ret <vscale x 4 x double> %res 2315} 2316 2317define <vscale x 4 x double> @splice_nxv4f64_offset_max(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 { 2318; CHECK-LABEL: splice_nxv4f64_offset_max: 2319; CHECK: # %bb.0: 2320; CHECK-NEXT: csrr a0, vlenb 2321; CHECK-NEXT: srli a0, a0, 1 2322; CHECK-NEXT: addi a0, a0, -7 2323; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu 2324; CHECK-NEXT: vslidedown.vi v8, v8, 7 2325; CHECK-NEXT: vsetvli a1, zero, e64, m4, tu, mu 2326; CHECK-NEXT: vslideup.vx v8, v12, a0 2327; CHECK-NEXT: ret 2328 %res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 7) 2329 ret <vscale x 4 x double> %res 2330} 2331 2332declare <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double>, <vscale x 8 x double>, i32) 2333 2334define <vscale x 8 x double> @splice_nxv8f64_offset_zero(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 { 2335; CHECK-LABEL: splice_nxv8f64_offset_zero: 2336; CHECK: # %bb.0: 2337; CHECK-NEXT: ret 2338 %res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 0) 2339 ret <vscale x 8 x double> %res 2340} 2341 2342define <vscale x 8 x double> @splice_nxv8f64_offset_negone(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 { 2343; CHECK-LABEL: splice_nxv8f64_offset_negone: 2344; CHECK: # %bb.0: 2345; CHECK-NEXT: csrr a0, vlenb 2346; CHECK-NEXT: addi a0, a0, -1 2347; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu 2348; CHECK-NEXT: vslidedown.vx v8, v8, a0 2349; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu 2350; CHECK-NEXT: vslideup.vi v8, v16, 1 2351; CHECK-NEXT: ret 2352 %res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 -1) 2353 ret <vscale x 8 x double> %res 2354} 2355 2356define <vscale x 8 x double> @splice_nxv8f64_offset_min(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 { 2357; CHECK-LABEL: splice_nxv8f64_offset_min: 2358; CHECK: # %bb.0: 2359; CHECK-NEXT: csrr a0, vlenb 2360; CHECK-NEXT: addi a0, a0, -16 2361; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu 2362; CHECK-NEXT: vslidedown.vx v8, v8, a0 2363; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu 2364; CHECK-NEXT: vslideup.vi v8, v16, 16 2365; CHECK-NEXT: ret 2366 %res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 -16) 2367 ret <vscale x 8 x double> %res 2368} 2369 2370define <vscale x 8 x double> @splice_nxv8f64_offset_max(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 { 2371; CHECK-LABEL: splice_nxv8f64_offset_max: 2372; CHECK: # %bb.0: 2373; CHECK-NEXT: csrr a0, vlenb 2374; CHECK-NEXT: addi a0, a0, -15 2375; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu 2376; CHECK-NEXT: vslidedown.vi v8, v8, 15 2377; CHECK-NEXT: vsetvli a1, zero, e64, m8, tu, mu 2378; CHECK-NEXT: vslideup.vx v8, v16, a0 2379; CHECK-NEXT: ret 2380 %res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 15) 2381 ret <vscale x 8 x double> %res 2382} 2383 2384attributes #0 = { vscale_range(2,2) } 2385 2386