1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 4 5define <vscale x 1 x i8> @vdivu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) { 6; CHECK-LABEL: vdivu_vv_nxv1i8: 7; CHECK: # %bb.0: 8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 9; CHECK-NEXT: vdivu.vv v8, v8, v9 10; CHECK-NEXT: ret 11 %vc = udiv <vscale x 1 x i8> %va, %vb 12 ret <vscale x 1 x i8> %vc 13} 14 15define <vscale x 1 x i8> @vdivu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) { 16; CHECK-LABEL: vdivu_vx_nxv1i8: 17; CHECK: # %bb.0: 18; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 19; CHECK-NEXT: vdivu.vx v8, v8, a0 20; CHECK-NEXT: ret 21 %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0 22 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer 23 %vc = udiv <vscale x 1 x i8> %va, %splat 24 ret <vscale x 1 x i8> %vc 25} 26 27define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) { 28; CHECK-LABEL: vdivu_vi_nxv1i8_0: 29; CHECK: # %bb.0: 30; CHECK-NEXT: addi a0, zero, 33 31; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 32; CHECK-NEXT: vmulhu.vx v8, v8, a0 33; CHECK-NEXT: vsrl.vi v8, v8, 5 34; CHECK-NEXT: ret 35 %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0 36 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer 37 %vc = udiv <vscale x 1 x i8> %va, %splat 38 ret <vscale x 1 x i8> %vc 39} 40 41; Test V/1 to see if we can optimize it away for scalable vectors. 42define <vscale x 1 x i8> @vdivu_vi_nxv1i8_1(<vscale x 1 x i8> %va) { 43; CHECK-LABEL: vdivu_vi_nxv1i8_1: 44; CHECK: # %bb.0: 45; CHECK-NEXT: ret 46 %head = insertelement <vscale x 1 x i8> undef, i8 1, i32 0 47 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer 48 %vc = udiv <vscale x 1 x i8> %va, %splat 49 ret <vscale x 1 x i8> %vc 50} 51 52; Test 0/V to see if we can optimize it away for scalable vectors. 53define <vscale x 1 x i8> @vdivu_iv_nxv1i8_0(<vscale x 1 x i8> %va) { 54; CHECK-LABEL: vdivu_iv_nxv1i8_0: 55; CHECK: # %bb.0: 56; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 57; CHECK-NEXT: vmv.v.i v8, 0 58; CHECK-NEXT: ret 59 %head = insertelement <vscale x 1 x i8> undef, i8 0, i32 0 60 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer 61 %vc = udiv <vscale x 1 x i8> %splat, %va 62 ret <vscale x 1 x i8> %vc 63} 64 65define <vscale x 2 x i8> @vdivu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) { 66; CHECK-LABEL: vdivu_vv_nxv2i8: 67; CHECK: # %bb.0: 68; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu 69; CHECK-NEXT: vdivu.vv v8, v8, v9 70; CHECK-NEXT: ret 71 %vc = udiv <vscale x 2 x i8> %va, %vb 72 ret <vscale x 2 x i8> %vc 73} 74 75define <vscale x 2 x i8> @vdivu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) { 76; CHECK-LABEL: vdivu_vx_nxv2i8: 77; CHECK: # %bb.0: 78; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 79; CHECK-NEXT: vdivu.vx v8, v8, a0 80; CHECK-NEXT: ret 81 %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0 82 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer 83 %vc = udiv <vscale x 2 x i8> %va, %splat 84 ret <vscale x 2 x i8> %vc 85} 86 87define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) { 88; CHECK-LABEL: vdivu_vi_nxv2i8_0: 89; CHECK: # %bb.0: 90; CHECK-NEXT: addi a0, zero, 33 91; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 92; CHECK-NEXT: vmulhu.vx v8, v8, a0 93; CHECK-NEXT: vsrl.vi v8, v8, 5 94; CHECK-NEXT: ret 95 %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0 96 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer 97 %vc = udiv <vscale x 2 x i8> %va, %splat 98 ret <vscale x 2 x i8> %vc 99} 100 101define <vscale x 4 x i8> @vdivu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) { 102; CHECK-LABEL: vdivu_vv_nxv4i8: 103; CHECK: # %bb.0: 104; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 105; CHECK-NEXT: vdivu.vv v8, v8, v9 106; CHECK-NEXT: ret 107 %vc = udiv <vscale x 4 x i8> %va, %vb 108 ret <vscale x 4 x i8> %vc 109} 110 111define <vscale x 4 x i8> @vdivu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) { 112; CHECK-LABEL: vdivu_vx_nxv4i8: 113; CHECK: # %bb.0: 114; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 115; CHECK-NEXT: vdivu.vx v8, v8, a0 116; CHECK-NEXT: ret 117 %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0 118 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer 119 %vc = udiv <vscale x 4 x i8> %va, %splat 120 ret <vscale x 4 x i8> %vc 121} 122 123define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) { 124; CHECK-LABEL: vdivu_vi_nxv4i8_0: 125; CHECK: # %bb.0: 126; CHECK-NEXT: addi a0, zero, 33 127; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 128; CHECK-NEXT: vmulhu.vx v8, v8, a0 129; CHECK-NEXT: vsrl.vi v8, v8, 5 130; CHECK-NEXT: ret 131 %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0 132 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer 133 %vc = udiv <vscale x 4 x i8> %va, %splat 134 ret <vscale x 4 x i8> %vc 135} 136 137define <vscale x 8 x i8> @vdivu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 138; CHECK-LABEL: vdivu_vv_nxv8i8: 139; CHECK: # %bb.0: 140; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 141; CHECK-NEXT: vdivu.vv v8, v8, v9 142; CHECK-NEXT: ret 143 %vc = udiv <vscale x 8 x i8> %va, %vb 144 ret <vscale x 8 x i8> %vc 145} 146 147define <vscale x 8 x i8> @vdivu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) { 148; CHECK-LABEL: vdivu_vx_nxv8i8: 149; CHECK: # %bb.0: 150; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 151; CHECK-NEXT: vdivu.vx v8, v8, a0 152; CHECK-NEXT: ret 153 %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0 154 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer 155 %vc = udiv <vscale x 8 x i8> %va, %splat 156 ret <vscale x 8 x i8> %vc 157} 158 159define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 160; CHECK-LABEL: vdivu_vi_nxv8i8_0: 161; CHECK: # %bb.0: 162; CHECK-NEXT: addi a0, zero, 33 163; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 164; CHECK-NEXT: vmulhu.vx v8, v8, a0 165; CHECK-NEXT: vsrl.vi v8, v8, 5 166; CHECK-NEXT: ret 167 %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0 168 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer 169 %vc = udiv <vscale x 8 x i8> %va, %splat 170 ret <vscale x 8 x i8> %vc 171} 172 173define <vscale x 16 x i8> @vdivu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) { 174; CHECK-LABEL: vdivu_vv_nxv16i8: 175; CHECK: # %bb.0: 176; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu 177; CHECK-NEXT: vdivu.vv v8, v8, v10 178; CHECK-NEXT: ret 179 %vc = udiv <vscale x 16 x i8> %va, %vb 180 ret <vscale x 16 x i8> %vc 181} 182 183define <vscale x 16 x i8> @vdivu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) { 184; CHECK-LABEL: vdivu_vx_nxv16i8: 185; CHECK: # %bb.0: 186; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 187; CHECK-NEXT: vdivu.vx v8, v8, a0 188; CHECK-NEXT: ret 189 %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0 190 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 191 %vc = udiv <vscale x 16 x i8> %va, %splat 192 ret <vscale x 16 x i8> %vc 193} 194 195define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) { 196; CHECK-LABEL: vdivu_vi_nxv16i8_0: 197; CHECK: # %bb.0: 198; CHECK-NEXT: addi a0, zero, 33 199; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 200; CHECK-NEXT: vmulhu.vx v8, v8, a0 201; CHECK-NEXT: vsrl.vi v8, v8, 5 202; CHECK-NEXT: ret 203 %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0 204 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 205 %vc = udiv <vscale x 16 x i8> %va, %splat 206 ret <vscale x 16 x i8> %vc 207} 208 209define <vscale x 32 x i8> @vdivu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) { 210; CHECK-LABEL: vdivu_vv_nxv32i8: 211; CHECK: # %bb.0: 212; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu 213; CHECK-NEXT: vdivu.vv v8, v8, v12 214; CHECK-NEXT: ret 215 %vc = udiv <vscale x 32 x i8> %va, %vb 216 ret <vscale x 32 x i8> %vc 217} 218 219define <vscale x 32 x i8> @vdivu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) { 220; CHECK-LABEL: vdivu_vx_nxv32i8: 221; CHECK: # %bb.0: 222; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 223; CHECK-NEXT: vdivu.vx v8, v8, a0 224; CHECK-NEXT: ret 225 %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0 226 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer 227 %vc = udiv <vscale x 32 x i8> %va, %splat 228 ret <vscale x 32 x i8> %vc 229} 230 231define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) { 232; CHECK-LABEL: vdivu_vi_nxv32i8_0: 233; CHECK: # %bb.0: 234; CHECK-NEXT: addi a0, zero, 33 235; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 236; CHECK-NEXT: vmulhu.vx v8, v8, a0 237; CHECK-NEXT: vsrl.vi v8, v8, 5 238; CHECK-NEXT: ret 239 %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0 240 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer 241 %vc = udiv <vscale x 32 x i8> %va, %splat 242 ret <vscale x 32 x i8> %vc 243} 244 245define <vscale x 64 x i8> @vdivu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) { 246; CHECK-LABEL: vdivu_vv_nxv64i8: 247; CHECK: # %bb.0: 248; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu 249; CHECK-NEXT: vdivu.vv v8, v8, v16 250; CHECK-NEXT: ret 251 %vc = udiv <vscale x 64 x i8> %va, %vb 252 ret <vscale x 64 x i8> %vc 253} 254 255define <vscale x 64 x i8> @vdivu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) { 256; CHECK-LABEL: vdivu_vx_nxv64i8: 257; CHECK: # %bb.0: 258; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 259; CHECK-NEXT: vdivu.vx v8, v8, a0 260; CHECK-NEXT: ret 261 %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0 262 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer 263 %vc = udiv <vscale x 64 x i8> %va, %splat 264 ret <vscale x 64 x i8> %vc 265} 266 267define <vscale x 64 x i8> @vdivu_vi_nxv64i8_0(<vscale x 64 x i8> %va) { 268; CHECK-LABEL: vdivu_vi_nxv64i8_0: 269; CHECK: # %bb.0: 270; CHECK-NEXT: addi a0, zero, 33 271; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 272; CHECK-NEXT: vmulhu.vx v8, v8, a0 273; CHECK-NEXT: vsrl.vi v8, v8, 5 274; CHECK-NEXT: ret 275 %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0 276 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer 277 %vc = udiv <vscale x 64 x i8> %va, %splat 278 ret <vscale x 64 x i8> %vc 279} 280 281define <vscale x 1 x i16> @vdivu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) { 282; CHECK-LABEL: vdivu_vv_nxv1i16: 283; CHECK: # %bb.0: 284; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu 285; CHECK-NEXT: vdivu.vv v8, v8, v9 286; CHECK-NEXT: ret 287 %vc = udiv <vscale x 1 x i16> %va, %vb 288 ret <vscale x 1 x i16> %vc 289} 290 291define <vscale x 1 x i16> @vdivu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) { 292; CHECK-LABEL: vdivu_vx_nxv1i16: 293; CHECK: # %bb.0: 294; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 295; CHECK-NEXT: vdivu.vx v8, v8, a0 296; CHECK-NEXT: ret 297 %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0 298 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer 299 %vc = udiv <vscale x 1 x i16> %va, %splat 300 ret <vscale x 1 x i16> %vc 301} 302 303define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) { 304; RV32-LABEL: vdivu_vi_nxv1i16_0: 305; RV32: # %bb.0: 306; RV32-NEXT: lui a0, 2 307; RV32-NEXT: addi a0, a0, 1 308; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 309; RV32-NEXT: vmulhu.vx v8, v8, a0 310; RV32-NEXT: vsrl.vi v8, v8, 13 311; RV32-NEXT: ret 312; 313; RV64-LABEL: vdivu_vi_nxv1i16_0: 314; RV64: # %bb.0: 315; RV64-NEXT: lui a0, 2 316; RV64-NEXT: addiw a0, a0, 1 317; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 318; RV64-NEXT: vmulhu.vx v8, v8, a0 319; RV64-NEXT: vsrl.vi v8, v8, 13 320; RV64-NEXT: ret 321 %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0 322 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer 323 %vc = udiv <vscale x 1 x i16> %va, %splat 324 ret <vscale x 1 x i16> %vc 325} 326 327define <vscale x 2 x i16> @vdivu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) { 328; CHECK-LABEL: vdivu_vv_nxv2i16: 329; CHECK: # %bb.0: 330; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu 331; CHECK-NEXT: vdivu.vv v8, v8, v9 332; CHECK-NEXT: ret 333 %vc = udiv <vscale x 2 x i16> %va, %vb 334 ret <vscale x 2 x i16> %vc 335} 336 337define <vscale x 2 x i16> @vdivu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) { 338; CHECK-LABEL: vdivu_vx_nxv2i16: 339; CHECK: # %bb.0: 340; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 341; CHECK-NEXT: vdivu.vx v8, v8, a0 342; CHECK-NEXT: ret 343 %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0 344 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer 345 %vc = udiv <vscale x 2 x i16> %va, %splat 346 ret <vscale x 2 x i16> %vc 347} 348 349define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) { 350; RV32-LABEL: vdivu_vi_nxv2i16_0: 351; RV32: # %bb.0: 352; RV32-NEXT: lui a0, 2 353; RV32-NEXT: addi a0, a0, 1 354; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 355; RV32-NEXT: vmulhu.vx v8, v8, a0 356; RV32-NEXT: vsrl.vi v8, v8, 13 357; RV32-NEXT: ret 358; 359; RV64-LABEL: vdivu_vi_nxv2i16_0: 360; RV64: # %bb.0: 361; RV64-NEXT: lui a0, 2 362; RV64-NEXT: addiw a0, a0, 1 363; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 364; RV64-NEXT: vmulhu.vx v8, v8, a0 365; RV64-NEXT: vsrl.vi v8, v8, 13 366; RV64-NEXT: ret 367 %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0 368 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer 369 %vc = udiv <vscale x 2 x i16> %va, %splat 370 ret <vscale x 2 x i16> %vc 371} 372 373define <vscale x 4 x i16> @vdivu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) { 374; CHECK-LABEL: vdivu_vv_nxv4i16: 375; CHECK: # %bb.0: 376; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu 377; CHECK-NEXT: vdivu.vv v8, v8, v9 378; CHECK-NEXT: ret 379 %vc = udiv <vscale x 4 x i16> %va, %vb 380 ret <vscale x 4 x i16> %vc 381} 382 383define <vscale x 4 x i16> @vdivu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) { 384; CHECK-LABEL: vdivu_vx_nxv4i16: 385; CHECK: # %bb.0: 386; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu 387; CHECK-NEXT: vdivu.vx v8, v8, a0 388; CHECK-NEXT: ret 389 %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0 390 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer 391 %vc = udiv <vscale x 4 x i16> %va, %splat 392 ret <vscale x 4 x i16> %vc 393} 394 395define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) { 396; RV32-LABEL: vdivu_vi_nxv4i16_0: 397; RV32: # %bb.0: 398; RV32-NEXT: lui a0, 2 399; RV32-NEXT: addi a0, a0, 1 400; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu 401; RV32-NEXT: vmulhu.vx v8, v8, a0 402; RV32-NEXT: vsrl.vi v8, v8, 13 403; RV32-NEXT: ret 404; 405; RV64-LABEL: vdivu_vi_nxv4i16_0: 406; RV64: # %bb.0: 407; RV64-NEXT: lui a0, 2 408; RV64-NEXT: addiw a0, a0, 1 409; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu 410; RV64-NEXT: vmulhu.vx v8, v8, a0 411; RV64-NEXT: vsrl.vi v8, v8, 13 412; RV64-NEXT: ret 413 %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0 414 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer 415 %vc = udiv <vscale x 4 x i16> %va, %splat 416 ret <vscale x 4 x i16> %vc 417} 418 419define <vscale x 8 x i16> @vdivu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 420; CHECK-LABEL: vdivu_vv_nxv8i16: 421; CHECK: # %bb.0: 422; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu 423; CHECK-NEXT: vdivu.vv v8, v8, v10 424; CHECK-NEXT: ret 425 %vc = udiv <vscale x 8 x i16> %va, %vb 426 ret <vscale x 8 x i16> %vc 427} 428 429define <vscale x 8 x i16> @vdivu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) { 430; CHECK-LABEL: vdivu_vx_nxv8i16: 431; CHECK: # %bb.0: 432; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu 433; CHECK-NEXT: vdivu.vx v8, v8, a0 434; CHECK-NEXT: ret 435 %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0 436 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 437 %vc = udiv <vscale x 8 x i16> %va, %splat 438 ret <vscale x 8 x i16> %vc 439} 440 441define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 442; RV32-LABEL: vdivu_vi_nxv8i16_0: 443; RV32: # %bb.0: 444; RV32-NEXT: lui a0, 2 445; RV32-NEXT: addi a0, a0, 1 446; RV32-NEXT: vsetvli a1, zero, e16, m2, ta, mu 447; RV32-NEXT: vmulhu.vx v8, v8, a0 448; RV32-NEXT: vsrl.vi v8, v8, 13 449; RV32-NEXT: ret 450; 451; RV64-LABEL: vdivu_vi_nxv8i16_0: 452; RV64: # %bb.0: 453; RV64-NEXT: lui a0, 2 454; RV64-NEXT: addiw a0, a0, 1 455; RV64-NEXT: vsetvli a1, zero, e16, m2, ta, mu 456; RV64-NEXT: vmulhu.vx v8, v8, a0 457; RV64-NEXT: vsrl.vi v8, v8, 13 458; RV64-NEXT: ret 459 %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0 460 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 461 %vc = udiv <vscale x 8 x i16> %va, %splat 462 ret <vscale x 8 x i16> %vc 463} 464 465define <vscale x 16 x i16> @vdivu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) { 466; CHECK-LABEL: vdivu_vv_nxv16i16: 467; CHECK: # %bb.0: 468; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 469; CHECK-NEXT: vdivu.vv v8, v8, v12 470; CHECK-NEXT: ret 471 %vc = udiv <vscale x 16 x i16> %va, %vb 472 ret <vscale x 16 x i16> %vc 473} 474 475define <vscale x 16 x i16> @vdivu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) { 476; CHECK-LABEL: vdivu_vx_nxv16i16: 477; CHECK: # %bb.0: 478; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu 479; CHECK-NEXT: vdivu.vx v8, v8, a0 480; CHECK-NEXT: ret 481 %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0 482 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer 483 %vc = udiv <vscale x 16 x i16> %va, %splat 484 ret <vscale x 16 x i16> %vc 485} 486 487define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) { 488; RV32-LABEL: vdivu_vi_nxv16i16_0: 489; RV32: # %bb.0: 490; RV32-NEXT: lui a0, 2 491; RV32-NEXT: addi a0, a0, 1 492; RV32-NEXT: vsetvli a1, zero, e16, m4, ta, mu 493; RV32-NEXT: vmulhu.vx v8, v8, a0 494; RV32-NEXT: vsrl.vi v8, v8, 13 495; RV32-NEXT: ret 496; 497; RV64-LABEL: vdivu_vi_nxv16i16_0: 498; RV64: # %bb.0: 499; RV64-NEXT: lui a0, 2 500; RV64-NEXT: addiw a0, a0, 1 501; RV64-NEXT: vsetvli a1, zero, e16, m4, ta, mu 502; RV64-NEXT: vmulhu.vx v8, v8, a0 503; RV64-NEXT: vsrl.vi v8, v8, 13 504; RV64-NEXT: ret 505 %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0 506 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer 507 %vc = udiv <vscale x 16 x i16> %va, %splat 508 ret <vscale x 16 x i16> %vc 509} 510 511define <vscale x 32 x i16> @vdivu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) { 512; CHECK-LABEL: vdivu_vv_nxv32i16: 513; CHECK: # %bb.0: 514; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu 515; CHECK-NEXT: vdivu.vv v8, v8, v16 516; CHECK-NEXT: ret 517 %vc = udiv <vscale x 32 x i16> %va, %vb 518 ret <vscale x 32 x i16> %vc 519} 520 521define <vscale x 32 x i16> @vdivu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) { 522; CHECK-LABEL: vdivu_vx_nxv32i16: 523; CHECK: # %bb.0: 524; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu 525; CHECK-NEXT: vdivu.vx v8, v8, a0 526; CHECK-NEXT: ret 527 %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0 528 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer 529 %vc = udiv <vscale x 32 x i16> %va, %splat 530 ret <vscale x 32 x i16> %vc 531} 532 533define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) { 534; RV32-LABEL: vdivu_vi_nxv32i16_0: 535; RV32: # %bb.0: 536; RV32-NEXT: lui a0, 2 537; RV32-NEXT: addi a0, a0, 1 538; RV32-NEXT: vsetvli a1, zero, e16, m8, ta, mu 539; RV32-NEXT: vmulhu.vx v8, v8, a0 540; RV32-NEXT: vsrl.vi v8, v8, 13 541; RV32-NEXT: ret 542; 543; RV64-LABEL: vdivu_vi_nxv32i16_0: 544; RV64: # %bb.0: 545; RV64-NEXT: lui a0, 2 546; RV64-NEXT: addiw a0, a0, 1 547; RV64-NEXT: vsetvli a1, zero, e16, m8, ta, mu 548; RV64-NEXT: vmulhu.vx v8, v8, a0 549; RV64-NEXT: vsrl.vi v8, v8, 13 550; RV64-NEXT: ret 551 %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0 552 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer 553 %vc = udiv <vscale x 32 x i16> %va, %splat 554 ret <vscale x 32 x i16> %vc 555} 556 557define <vscale x 1 x i32> @vdivu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) { 558; CHECK-LABEL: vdivu_vv_nxv1i32: 559; CHECK: # %bb.0: 560; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu 561; CHECK-NEXT: vdivu.vv v8, v8, v9 562; CHECK-NEXT: ret 563 %vc = udiv <vscale x 1 x i32> %va, %vb 564 ret <vscale x 1 x i32> %vc 565} 566 567define <vscale x 1 x i32> @vdivu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) { 568; CHECK-LABEL: vdivu_vx_nxv1i32: 569; CHECK: # %bb.0: 570; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 571; CHECK-NEXT: vdivu.vx v8, v8, a0 572; CHECK-NEXT: ret 573 %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0 574 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer 575 %vc = udiv <vscale x 1 x i32> %va, %splat 576 ret <vscale x 1 x i32> %vc 577} 578 579define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) { 580; RV32-LABEL: vdivu_vi_nxv1i32_0: 581; RV32: # %bb.0: 582; RV32-NEXT: lui a0, 131072 583; RV32-NEXT: addi a0, a0, 1 584; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 585; RV32-NEXT: vmulhu.vx v8, v8, a0 586; RV32-NEXT: vsrl.vi v8, v8, 29 587; RV32-NEXT: ret 588; 589; RV64-LABEL: vdivu_vi_nxv1i32_0: 590; RV64: # %bb.0: 591; RV64-NEXT: lui a0, 131072 592; RV64-NEXT: addiw a0, a0, 1 593; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 594; RV64-NEXT: vmulhu.vx v8, v8, a0 595; RV64-NEXT: vsrl.vi v8, v8, 29 596; RV64-NEXT: ret 597 %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0 598 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer 599 %vc = udiv <vscale x 1 x i32> %va, %splat 600 ret <vscale x 1 x i32> %vc 601} 602 603define <vscale x 2 x i32> @vdivu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) { 604; CHECK-LABEL: vdivu_vv_nxv2i32: 605; CHECK: # %bb.0: 606; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu 607; CHECK-NEXT: vdivu.vv v8, v8, v9 608; CHECK-NEXT: ret 609 %vc = udiv <vscale x 2 x i32> %va, %vb 610 ret <vscale x 2 x i32> %vc 611} 612 613define <vscale x 2 x i32> @vdivu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) { 614; CHECK-LABEL: vdivu_vx_nxv2i32: 615; CHECK: # %bb.0: 616; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu 617; CHECK-NEXT: vdivu.vx v8, v8, a0 618; CHECK-NEXT: ret 619 %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0 620 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer 621 %vc = udiv <vscale x 2 x i32> %va, %splat 622 ret <vscale x 2 x i32> %vc 623} 624 625define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) { 626; RV32-LABEL: vdivu_vi_nxv2i32_0: 627; RV32: # %bb.0: 628; RV32-NEXT: lui a0, 131072 629; RV32-NEXT: addi a0, a0, 1 630; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu 631; RV32-NEXT: vmulhu.vx v8, v8, a0 632; RV32-NEXT: vsrl.vi v8, v8, 29 633; RV32-NEXT: ret 634; 635; RV64-LABEL: vdivu_vi_nxv2i32_0: 636; RV64: # %bb.0: 637; RV64-NEXT: lui a0, 131072 638; RV64-NEXT: addiw a0, a0, 1 639; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu 640; RV64-NEXT: vmulhu.vx v8, v8, a0 641; RV64-NEXT: vsrl.vi v8, v8, 29 642; RV64-NEXT: ret 643 %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0 644 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer 645 %vc = udiv <vscale x 2 x i32> %va, %splat 646 ret <vscale x 2 x i32> %vc 647} 648 649define <vscale x 4 x i32> @vdivu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) { 650; CHECK-LABEL: vdivu_vv_nxv4i32: 651; CHECK: # %bb.0: 652; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu 653; CHECK-NEXT: vdivu.vv v8, v8, v10 654; CHECK-NEXT: ret 655 %vc = udiv <vscale x 4 x i32> %va, %vb 656 ret <vscale x 4 x i32> %vc 657} 658 659define <vscale x 4 x i32> @vdivu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) { 660; CHECK-LABEL: vdivu_vx_nxv4i32: 661; CHECK: # %bb.0: 662; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu 663; CHECK-NEXT: vdivu.vx v8, v8, a0 664; CHECK-NEXT: ret 665 %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0 666 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 667 %vc = udiv <vscale x 4 x i32> %va, %splat 668 ret <vscale x 4 x i32> %vc 669} 670 671define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) { 672; RV32-LABEL: vdivu_vi_nxv4i32_0: 673; RV32: # %bb.0: 674; RV32-NEXT: lui a0, 131072 675; RV32-NEXT: addi a0, a0, 1 676; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu 677; RV32-NEXT: vmulhu.vx v8, v8, a0 678; RV32-NEXT: vsrl.vi v8, v8, 29 679; RV32-NEXT: ret 680; 681; RV64-LABEL: vdivu_vi_nxv4i32_0: 682; RV64: # %bb.0: 683; RV64-NEXT: lui a0, 131072 684; RV64-NEXT: addiw a0, a0, 1 685; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, mu 686; RV64-NEXT: vmulhu.vx v8, v8, a0 687; RV64-NEXT: vsrl.vi v8, v8, 29 688; RV64-NEXT: ret 689 %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0 690 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 691 %vc = udiv <vscale x 4 x i32> %va, %splat 692 ret <vscale x 4 x i32> %vc 693} 694 695define <vscale x 8 x i32> @vdivu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 696; CHECK-LABEL: vdivu_vv_nxv8i32: 697; CHECK: # %bb.0: 698; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu 699; CHECK-NEXT: vdivu.vv v8, v8, v12 700; CHECK-NEXT: ret 701 %vc = udiv <vscale x 8 x i32> %va, %vb 702 ret <vscale x 8 x i32> %vc 703} 704 705define <vscale x 8 x i32> @vdivu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) { 706; CHECK-LABEL: vdivu_vx_nxv8i32: 707; CHECK: # %bb.0: 708; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu 709; CHECK-NEXT: vdivu.vx v8, v8, a0 710; CHECK-NEXT: ret 711 %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0 712 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer 713 %vc = udiv <vscale x 8 x i32> %va, %splat 714 ret <vscale x 8 x i32> %vc 715} 716 717define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 718; RV32-LABEL: vdivu_vi_nxv8i32_0: 719; RV32: # %bb.0: 720; RV32-NEXT: lui a0, 131072 721; RV32-NEXT: addi a0, a0, 1 722; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu 723; RV32-NEXT: vmulhu.vx v8, v8, a0 724; RV32-NEXT: vsrl.vi v8, v8, 29 725; RV32-NEXT: ret 726; 727; RV64-LABEL: vdivu_vi_nxv8i32_0: 728; RV64: # %bb.0: 729; RV64-NEXT: lui a0, 131072 730; RV64-NEXT: addiw a0, a0, 1 731; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, mu 732; RV64-NEXT: vmulhu.vx v8, v8, a0 733; RV64-NEXT: vsrl.vi v8, v8, 29 734; RV64-NEXT: ret 735 %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0 736 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer 737 %vc = udiv <vscale x 8 x i32> %va, %splat 738 ret <vscale x 8 x i32> %vc 739} 740 741define <vscale x 16 x i32> @vdivu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) { 742; CHECK-LABEL: vdivu_vv_nxv16i32: 743; CHECK: # %bb.0: 744; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 745; CHECK-NEXT: vdivu.vv v8, v8, v16 746; CHECK-NEXT: ret 747 %vc = udiv <vscale x 16 x i32> %va, %vb 748 ret <vscale x 16 x i32> %vc 749} 750 751define <vscale x 16 x i32> @vdivu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) { 752; CHECK-LABEL: vdivu_vx_nxv16i32: 753; CHECK: # %bb.0: 754; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu 755; CHECK-NEXT: vdivu.vx v8, v8, a0 756; CHECK-NEXT: ret 757 %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0 758 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer 759 %vc = udiv <vscale x 16 x i32> %va, %splat 760 ret <vscale x 16 x i32> %vc 761} 762 763define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) { 764; RV32-LABEL: vdivu_vi_nxv16i32_0: 765; RV32: # %bb.0: 766; RV32-NEXT: lui a0, 131072 767; RV32-NEXT: addi a0, a0, 1 768; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, mu 769; RV32-NEXT: vmulhu.vx v8, v8, a0 770; RV32-NEXT: vsrl.vi v8, v8, 29 771; RV32-NEXT: ret 772; 773; RV64-LABEL: vdivu_vi_nxv16i32_0: 774; RV64: # %bb.0: 775; RV64-NEXT: lui a0, 131072 776; RV64-NEXT: addiw a0, a0, 1 777; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, mu 778; RV64-NEXT: vmulhu.vx v8, v8, a0 779; RV64-NEXT: vsrl.vi v8, v8, 29 780; RV64-NEXT: ret 781 %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0 782 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer 783 %vc = udiv <vscale x 16 x i32> %va, %splat 784 ret <vscale x 16 x i32> %vc 785} 786 787define <vscale x 1 x i64> @vdivu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) { 788; CHECK-LABEL: vdivu_vv_nxv1i64: 789; CHECK: # %bb.0: 790; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 791; CHECK-NEXT: vdivu.vv v8, v8, v9 792; CHECK-NEXT: ret 793 %vc = udiv <vscale x 1 x i64> %va, %vb 794 ret <vscale x 1 x i64> %vc 795} 796 797define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { 798; RV32-LABEL: vdivu_vx_nxv1i64: 799; RV32: # %bb.0: 800; RV32-NEXT: addi sp, sp, -16 801; RV32-NEXT: .cfi_def_cfa_offset 16 802; RV32-NEXT: sw a1, 12(sp) 803; RV32-NEXT: sw a0, 8(sp) 804; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu 805; RV32-NEXT: addi a0, sp, 8 806; RV32-NEXT: vlse64.v v9, (a0), zero 807; RV32-NEXT: vdivu.vv v8, v8, v9 808; RV32-NEXT: addi sp, sp, 16 809; RV32-NEXT: ret 810; 811; RV64-LABEL: vdivu_vx_nxv1i64: 812; RV64: # %bb.0: 813; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu 814; RV64-NEXT: vdivu.vx v8, v8, a0 815; RV64-NEXT: ret 816 %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0 817 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 818 %vc = udiv <vscale x 1 x i64> %va, %splat 819 ret <vscale x 1 x i64> %vc 820} 821 822define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) { 823; RV32-LABEL: vdivu_vi_nxv1i64_0: 824; RV32: # %bb.0: 825; RV32-NEXT: addi sp, sp, -16 826; RV32-NEXT: .cfi_def_cfa_offset 16 827; RV32-NEXT: lui a0, 131072 828; RV32-NEXT: sw a0, 12(sp) 829; RV32-NEXT: addi a0, zero, 1 830; RV32-NEXT: sw a0, 8(sp) 831; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu 832; RV32-NEXT: addi a0, sp, 8 833; RV32-NEXT: vlse64.v v9, (a0), zero 834; RV32-NEXT: vmulhu.vv v8, v8, v9 835; RV32-NEXT: addi a0, zero, 61 836; RV32-NEXT: vsrl.vx v8, v8, a0 837; RV32-NEXT: addi sp, sp, 16 838; RV32-NEXT: ret 839; 840; RV64-LABEL: vdivu_vi_nxv1i64_0: 841; RV64: # %bb.0: 842; RV64-NEXT: addi a0, zero, 1 843; RV64-NEXT: slli a0, a0, 61 844; RV64-NEXT: addi a0, a0, 1 845; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu 846; RV64-NEXT: vmulhu.vx v8, v8, a0 847; RV64-NEXT: addi a0, zero, 61 848; RV64-NEXT: vsrl.vx v8, v8, a0 849; RV64-NEXT: ret 850 %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0 851 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 852 %vc = udiv <vscale x 1 x i64> %va, %splat 853 ret <vscale x 1 x i64> %vc 854} 855 856define <vscale x 1 x i64> @vdivu_vi_nxv1i64_1(<vscale x 1 x i64> %va) { 857; CHECK-LABEL: vdivu_vi_nxv1i64_1: 858; CHECK: # %bb.0: 859; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 860; CHECK-NEXT: vsrl.vi v8, v8, 1 861; CHECK-NEXT: ret 862 %head = insertelement <vscale x 1 x i64> undef, i64 2, i32 0 863 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 864 %vc = udiv <vscale x 1 x i64> %va, %splat 865 ret <vscale x 1 x i64> %vc 866} 867 868; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 869define <vscale x 1 x i64> @vdivu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) { 870; CHECK-LABEL: vdivu_vi_nxv1i64_2: 871; CHECK: # %bb.0: 872; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 873; CHECK-NEXT: vadd.vi v9, v9, 4 874; CHECK-NEXT: vsrl.vv v8, v8, v9 875; CHECK-NEXT: ret 876 %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0 877 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 878 %vc = shl <vscale x 1 x i64> %splat, %vb 879 %vd = udiv <vscale x 1 x i64> %va, %vc 880 ret <vscale x 1 x i64> %vd 881} 882 883define <vscale x 2 x i64> @vdivu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) { 884; CHECK-LABEL: vdivu_vv_nxv2i64: 885; CHECK: # %bb.0: 886; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 887; CHECK-NEXT: vdivu.vv v8, v8, v10 888; CHECK-NEXT: ret 889 %vc = udiv <vscale x 2 x i64> %va, %vb 890 ret <vscale x 2 x i64> %vc 891} 892 893define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { 894; RV32-LABEL: vdivu_vx_nxv2i64: 895; RV32: # %bb.0: 896; RV32-NEXT: addi sp, sp, -16 897; RV32-NEXT: .cfi_def_cfa_offset 16 898; RV32-NEXT: sw a1, 12(sp) 899; RV32-NEXT: sw a0, 8(sp) 900; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu 901; RV32-NEXT: addi a0, sp, 8 902; RV32-NEXT: vlse64.v v10, (a0), zero 903; RV32-NEXT: vdivu.vv v8, v8, v10 904; RV32-NEXT: addi sp, sp, 16 905; RV32-NEXT: ret 906; 907; RV64-LABEL: vdivu_vx_nxv2i64: 908; RV64: # %bb.0: 909; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu 910; RV64-NEXT: vdivu.vx v8, v8, a0 911; RV64-NEXT: ret 912 %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0 913 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 914 %vc = udiv <vscale x 2 x i64> %va, %splat 915 ret <vscale x 2 x i64> %vc 916} 917 918define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) { 919; RV32-LABEL: vdivu_vi_nxv2i64_0: 920; RV32: # %bb.0: 921; RV32-NEXT: addi sp, sp, -16 922; RV32-NEXT: .cfi_def_cfa_offset 16 923; RV32-NEXT: lui a0, 131072 924; RV32-NEXT: sw a0, 12(sp) 925; RV32-NEXT: addi a0, zero, 1 926; RV32-NEXT: sw a0, 8(sp) 927; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu 928; RV32-NEXT: addi a0, sp, 8 929; RV32-NEXT: vlse64.v v10, (a0), zero 930; RV32-NEXT: vmulhu.vv v8, v8, v10 931; RV32-NEXT: addi a0, zero, 61 932; RV32-NEXT: vsrl.vx v8, v8, a0 933; RV32-NEXT: addi sp, sp, 16 934; RV32-NEXT: ret 935; 936; RV64-LABEL: vdivu_vi_nxv2i64_0: 937; RV64: # %bb.0: 938; RV64-NEXT: addi a0, zero, 1 939; RV64-NEXT: slli a0, a0, 61 940; RV64-NEXT: addi a0, a0, 1 941; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu 942; RV64-NEXT: vmulhu.vx v8, v8, a0 943; RV64-NEXT: addi a0, zero, 61 944; RV64-NEXT: vsrl.vx v8, v8, a0 945; RV64-NEXT: ret 946 %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0 947 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 948 %vc = udiv <vscale x 2 x i64> %va, %splat 949 ret <vscale x 2 x i64> %vc 950} 951 952define <vscale x 2 x i64> @vdivu_vi_nxv2i64_1(<vscale x 2 x i64> %va) { 953; CHECK-LABEL: vdivu_vi_nxv2i64_1: 954; CHECK: # %bb.0: 955; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 956; CHECK-NEXT: vsrl.vi v8, v8, 1 957; CHECK-NEXT: ret 958 %head = insertelement <vscale x 2 x i64> undef, i64 2, i32 0 959 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 960 %vc = udiv <vscale x 2 x i64> %va, %splat 961 ret <vscale x 2 x i64> %vc 962} 963 964; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 965define <vscale x 2 x i64> @vdivu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) { 966; CHECK-LABEL: vdivu_vi_nxv2i64_2: 967; CHECK: # %bb.0: 968; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 969; CHECK-NEXT: vadd.vi v10, v10, 4 970; CHECK-NEXT: vsrl.vv v8, v8, v10 971; CHECK-NEXT: ret 972 %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0 973 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 974 %vc = shl <vscale x 2 x i64> %splat, %vb 975 %vd = udiv <vscale x 2 x i64> %va, %vc 976 ret <vscale x 2 x i64> %vd 977} 978 979define <vscale x 4 x i64> @vdivu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) { 980; CHECK-LABEL: vdivu_vv_nxv4i64: 981; CHECK: # %bb.0: 982; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 983; CHECK-NEXT: vdivu.vv v8, v8, v12 984; CHECK-NEXT: ret 985 %vc = udiv <vscale x 4 x i64> %va, %vb 986 ret <vscale x 4 x i64> %vc 987} 988 989define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { 990; RV32-LABEL: vdivu_vx_nxv4i64: 991; RV32: # %bb.0: 992; RV32-NEXT: addi sp, sp, -16 993; RV32-NEXT: .cfi_def_cfa_offset 16 994; RV32-NEXT: sw a1, 12(sp) 995; RV32-NEXT: sw a0, 8(sp) 996; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu 997; RV32-NEXT: addi a0, sp, 8 998; RV32-NEXT: vlse64.v v12, (a0), zero 999; RV32-NEXT: vdivu.vv v8, v8, v12 1000; RV32-NEXT: addi sp, sp, 16 1001; RV32-NEXT: ret 1002; 1003; RV64-LABEL: vdivu_vx_nxv4i64: 1004; RV64: # %bb.0: 1005; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1006; RV64-NEXT: vdivu.vx v8, v8, a0 1007; RV64-NEXT: ret 1008 %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0 1009 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 1010 %vc = udiv <vscale x 4 x i64> %va, %splat 1011 ret <vscale x 4 x i64> %vc 1012} 1013 1014define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) { 1015; RV32-LABEL: vdivu_vi_nxv4i64_0: 1016; RV32: # %bb.0: 1017; RV32-NEXT: addi sp, sp, -16 1018; RV32-NEXT: .cfi_def_cfa_offset 16 1019; RV32-NEXT: lui a0, 131072 1020; RV32-NEXT: sw a0, 12(sp) 1021; RV32-NEXT: addi a0, zero, 1 1022; RV32-NEXT: sw a0, 8(sp) 1023; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1024; RV32-NEXT: addi a0, sp, 8 1025; RV32-NEXT: vlse64.v v12, (a0), zero 1026; RV32-NEXT: vmulhu.vv v8, v8, v12 1027; RV32-NEXT: addi a0, zero, 61 1028; RV32-NEXT: vsrl.vx v8, v8, a0 1029; RV32-NEXT: addi sp, sp, 16 1030; RV32-NEXT: ret 1031; 1032; RV64-LABEL: vdivu_vi_nxv4i64_0: 1033; RV64: # %bb.0: 1034; RV64-NEXT: addi a0, zero, 1 1035; RV64-NEXT: slli a0, a0, 61 1036; RV64-NEXT: addi a0, a0, 1 1037; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1038; RV64-NEXT: vmulhu.vx v8, v8, a0 1039; RV64-NEXT: addi a0, zero, 61 1040; RV64-NEXT: vsrl.vx v8, v8, a0 1041; RV64-NEXT: ret 1042 %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0 1043 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 1044 %vc = udiv <vscale x 4 x i64> %va, %splat 1045 ret <vscale x 4 x i64> %vc 1046} 1047 1048define <vscale x 4 x i64> @vdivu_vi_nxv4i64_1(<vscale x 4 x i64> %va) { 1049; CHECK-LABEL: vdivu_vi_nxv4i64_1: 1050; CHECK: # %bb.0: 1051; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1052; CHECK-NEXT: vsrl.vi v8, v8, 1 1053; CHECK-NEXT: ret 1054 %head = insertelement <vscale x 4 x i64> undef, i64 2, i32 0 1055 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 1056 %vc = udiv <vscale x 4 x i64> %va, %splat 1057 ret <vscale x 4 x i64> %vc 1058} 1059 1060; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 1061define <vscale x 4 x i64> @vdivu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) { 1062; CHECK-LABEL: vdivu_vi_nxv4i64_2: 1063; CHECK: # %bb.0: 1064; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1065; CHECK-NEXT: vadd.vi v12, v12, 4 1066; CHECK-NEXT: vsrl.vv v8, v8, v12 1067; CHECK-NEXT: ret 1068 %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0 1069 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 1070 %vc = shl <vscale x 4 x i64> %splat, %vb 1071 %vd = udiv <vscale x 4 x i64> %va, %vc 1072 ret <vscale x 4 x i64> %vd 1073} 1074 1075define <vscale x 8 x i64> @vdivu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 1076; CHECK-LABEL: vdivu_vv_nxv8i64: 1077; CHECK: # %bb.0: 1078; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1079; CHECK-NEXT: vdivu.vv v8, v8, v16 1080; CHECK-NEXT: ret 1081 %vc = udiv <vscale x 8 x i64> %va, %vb 1082 ret <vscale x 8 x i64> %vc 1083} 1084 1085define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 1086; RV32-LABEL: vdivu_vx_nxv8i64: 1087; RV32: # %bb.0: 1088; RV32-NEXT: addi sp, sp, -16 1089; RV32-NEXT: .cfi_def_cfa_offset 16 1090; RV32-NEXT: sw a1, 12(sp) 1091; RV32-NEXT: sw a0, 8(sp) 1092; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1093; RV32-NEXT: addi a0, sp, 8 1094; RV32-NEXT: vlse64.v v16, (a0), zero 1095; RV32-NEXT: vdivu.vv v8, v8, v16 1096; RV32-NEXT: addi sp, sp, 16 1097; RV32-NEXT: ret 1098; 1099; RV64-LABEL: vdivu_vx_nxv8i64: 1100; RV64: # %bb.0: 1101; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1102; RV64-NEXT: vdivu.vx v8, v8, a0 1103; RV64-NEXT: ret 1104 %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0 1105 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 1106 %vc = udiv <vscale x 8 x i64> %va, %splat 1107 ret <vscale x 8 x i64> %vc 1108} 1109 1110define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 1111; RV32-LABEL: vdivu_vi_nxv8i64_0: 1112; RV32: # %bb.0: 1113; RV32-NEXT: addi sp, sp, -16 1114; RV32-NEXT: .cfi_def_cfa_offset 16 1115; RV32-NEXT: lui a0, 131072 1116; RV32-NEXT: sw a0, 12(sp) 1117; RV32-NEXT: addi a0, zero, 1 1118; RV32-NEXT: sw a0, 8(sp) 1119; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1120; RV32-NEXT: addi a0, sp, 8 1121; RV32-NEXT: vlse64.v v16, (a0), zero 1122; RV32-NEXT: vmulhu.vv v8, v8, v16 1123; RV32-NEXT: addi a0, zero, 61 1124; RV32-NEXT: vsrl.vx v8, v8, a0 1125; RV32-NEXT: addi sp, sp, 16 1126; RV32-NEXT: ret 1127; 1128; RV64-LABEL: vdivu_vi_nxv8i64_0: 1129; RV64: # %bb.0: 1130; RV64-NEXT: addi a0, zero, 1 1131; RV64-NEXT: slli a0, a0, 61 1132; RV64-NEXT: addi a0, a0, 1 1133; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1134; RV64-NEXT: vmulhu.vx v8, v8, a0 1135; RV64-NEXT: addi a0, zero, 61 1136; RV64-NEXT: vsrl.vx v8, v8, a0 1137; RV64-NEXT: ret 1138 %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0 1139 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 1140 %vc = udiv <vscale x 8 x i64> %va, %splat 1141 ret <vscale x 8 x i64> %vc 1142} 1143 1144define <vscale x 8 x i64> @vdivu_vi_nxv8i64_1(<vscale x 8 x i64> %va) { 1145; CHECK-LABEL: vdivu_vi_nxv8i64_1: 1146; CHECK: # %bb.0: 1147; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1148; CHECK-NEXT: vsrl.vi v8, v8, 1 1149; CHECK-NEXT: ret 1150 %head = insertelement <vscale x 8 x i64> undef, i64 2, i32 0 1151 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 1152 %vc = udiv <vscale x 8 x i64> %va, %splat 1153 ret <vscale x 8 x i64> %vc 1154} 1155 1156; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 1157define <vscale x 8 x i64> @vdivu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 1158; CHECK-LABEL: vdivu_vi_nxv8i64_2: 1159; CHECK: # %bb.0: 1160; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1161; CHECK-NEXT: vadd.vi v16, v16, 4 1162; CHECK-NEXT: vsrl.vv v8, v8, v16 1163; CHECK-NEXT: ret 1164 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 1165 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 1166 %vc = shl <vscale x 8 x i64> %splat, %vb 1167 %vd = udiv <vscale x 8 x i64> %va, %vc 1168 ret <vscale x 8 x i64> %vd 1169} 1170