1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-V 3; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVE64X 4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-V 5; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVE64X 6 7define <vscale x 1 x i8> @vdivu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) { 8; CHECK-LABEL: vdivu_vv_nxv1i8: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 11; CHECK-NEXT: vdivu.vv v8, v8, v9 12; CHECK-NEXT: ret 13 %vc = udiv <vscale x 1 x i8> %va, %vb 14 ret <vscale x 1 x i8> %vc 15} 16 17define <vscale x 1 x i8> @vdivu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) { 18; CHECK-LABEL: vdivu_vx_nxv1i8: 19; CHECK: # %bb.0: 20; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 21; CHECK-NEXT: vdivu.vx v8, v8, a0 22; CHECK-NEXT: ret 23 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0 24 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 25 %vc = udiv <vscale x 1 x i8> %va, %splat 26 ret <vscale x 1 x i8> %vc 27} 28 29define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) { 30; CHECK-LABEL: vdivu_vi_nxv1i8_0: 31; CHECK: # %bb.0: 32; CHECK-NEXT: li a0, 33 33; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 34; CHECK-NEXT: vmulhu.vx v8, v8, a0 35; CHECK-NEXT: vsrl.vi v8, v8, 5 36; CHECK-NEXT: ret 37 %head = insertelement <vscale x 1 x i8> poison, i8 -7, i32 0 38 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 39 %vc = udiv <vscale x 1 x i8> %va, %splat 40 ret <vscale x 1 x i8> %vc 41} 42 43; Test V/1 to see if we can optimize it away for scalable vectors. 44define <vscale x 1 x i8> @vdivu_vi_nxv1i8_1(<vscale x 1 x i8> %va) { 45; CHECK-LABEL: vdivu_vi_nxv1i8_1: 46; CHECK: # %bb.0: 47; CHECK-NEXT: ret 48 %head = insertelement <vscale x 1 x i8> poison, i8 1, i32 0 49 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 50 %vc = udiv <vscale x 1 x i8> %va, %splat 51 ret <vscale x 1 x i8> %vc 52} 53 54; Test 0/V to see if we can optimize it away for scalable vectors. 55define <vscale x 1 x i8> @vdivu_iv_nxv1i8_0(<vscale x 1 x i8> %va) { 56; CHECK-LABEL: vdivu_iv_nxv1i8_0: 57; CHECK: # %bb.0: 58; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 59; CHECK-NEXT: vmv.v.i v8, 0 60; CHECK-NEXT: ret 61 %head = insertelement <vscale x 1 x i8> poison, i8 0, i32 0 62 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 63 %vc = udiv <vscale x 1 x i8> %splat, %va 64 ret <vscale x 1 x i8> %vc 65} 66 67define <vscale x 2 x i8> @vdivu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) { 68; CHECK-LABEL: vdivu_vv_nxv2i8: 69; CHECK: # %bb.0: 70; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu 71; CHECK-NEXT: vdivu.vv v8, v8, v9 72; CHECK-NEXT: ret 73 %vc = udiv <vscale x 2 x i8> %va, %vb 74 ret <vscale x 2 x i8> %vc 75} 76 77define <vscale x 2 x i8> @vdivu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) { 78; CHECK-LABEL: vdivu_vx_nxv2i8: 79; CHECK: # %bb.0: 80; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 81; CHECK-NEXT: vdivu.vx v8, v8, a0 82; CHECK-NEXT: ret 83 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0 84 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer 85 %vc = udiv <vscale x 2 x i8> %va, %splat 86 ret <vscale x 2 x i8> %vc 87} 88 89define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) { 90; CHECK-LABEL: vdivu_vi_nxv2i8_0: 91; CHECK: # %bb.0: 92; CHECK-NEXT: li a0, 33 93; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 94; CHECK-NEXT: vmulhu.vx v8, v8, a0 95; CHECK-NEXT: vsrl.vi v8, v8, 5 96; CHECK-NEXT: ret 97 %head = insertelement <vscale x 2 x i8> poison, i8 -7, i32 0 98 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer 99 %vc = udiv <vscale x 2 x i8> %va, %splat 100 ret <vscale x 2 x i8> %vc 101} 102 103define <vscale x 4 x i8> @vdivu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) { 104; CHECK-LABEL: vdivu_vv_nxv4i8: 105; CHECK: # %bb.0: 106; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 107; CHECK-NEXT: vdivu.vv v8, v8, v9 108; CHECK-NEXT: ret 109 %vc = udiv <vscale x 4 x i8> %va, %vb 110 ret <vscale x 4 x i8> %vc 111} 112 113define <vscale x 4 x i8> @vdivu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) { 114; CHECK-LABEL: vdivu_vx_nxv4i8: 115; CHECK: # %bb.0: 116; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 117; CHECK-NEXT: vdivu.vx v8, v8, a0 118; CHECK-NEXT: ret 119 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0 120 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer 121 %vc = udiv <vscale x 4 x i8> %va, %splat 122 ret <vscale x 4 x i8> %vc 123} 124 125define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) { 126; CHECK-LABEL: vdivu_vi_nxv4i8_0: 127; CHECK: # %bb.0: 128; CHECK-NEXT: li a0, 33 129; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 130; CHECK-NEXT: vmulhu.vx v8, v8, a0 131; CHECK-NEXT: vsrl.vi v8, v8, 5 132; CHECK-NEXT: ret 133 %head = insertelement <vscale x 4 x i8> poison, i8 -7, i32 0 134 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer 135 %vc = udiv <vscale x 4 x i8> %va, %splat 136 ret <vscale x 4 x i8> %vc 137} 138 139define <vscale x 8 x i8> @vdivu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 140; CHECK-LABEL: vdivu_vv_nxv8i8: 141; CHECK: # %bb.0: 142; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 143; CHECK-NEXT: vdivu.vv v8, v8, v9 144; CHECK-NEXT: ret 145 %vc = udiv <vscale x 8 x i8> %va, %vb 146 ret <vscale x 8 x i8> %vc 147} 148 149define <vscale x 8 x i8> @vdivu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) { 150; CHECK-LABEL: vdivu_vx_nxv8i8: 151; CHECK: # %bb.0: 152; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 153; CHECK-NEXT: vdivu.vx v8, v8, a0 154; CHECK-NEXT: ret 155 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 156 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 157 %vc = udiv <vscale x 8 x i8> %va, %splat 158 ret <vscale x 8 x i8> %vc 159} 160 161define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 162; CHECK-LABEL: vdivu_vi_nxv8i8_0: 163; CHECK: # %bb.0: 164; CHECK-NEXT: li a0, 33 165; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 166; CHECK-NEXT: vmulhu.vx v8, v8, a0 167; CHECK-NEXT: vsrl.vi v8, v8, 5 168; CHECK-NEXT: ret 169 %head = insertelement <vscale x 8 x i8> poison, i8 -7, i32 0 170 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 171 %vc = udiv <vscale x 8 x i8> %va, %splat 172 ret <vscale x 8 x i8> %vc 173} 174 175define <vscale x 16 x i8> @vdivu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) { 176; CHECK-LABEL: vdivu_vv_nxv16i8: 177; CHECK: # %bb.0: 178; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu 179; CHECK-NEXT: vdivu.vv v8, v8, v10 180; CHECK-NEXT: ret 181 %vc = udiv <vscale x 16 x i8> %va, %vb 182 ret <vscale x 16 x i8> %vc 183} 184 185define <vscale x 16 x i8> @vdivu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) { 186; CHECK-LABEL: vdivu_vx_nxv16i8: 187; CHECK: # %bb.0: 188; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 189; CHECK-NEXT: vdivu.vx v8, v8, a0 190; CHECK-NEXT: ret 191 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0 192 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer 193 %vc = udiv <vscale x 16 x i8> %va, %splat 194 ret <vscale x 16 x i8> %vc 195} 196 197define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) { 198; CHECK-LABEL: vdivu_vi_nxv16i8_0: 199; CHECK: # %bb.0: 200; CHECK-NEXT: li a0, 33 201; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 202; CHECK-NEXT: vmulhu.vx v8, v8, a0 203; CHECK-NEXT: vsrl.vi v8, v8, 5 204; CHECK-NEXT: ret 205 %head = insertelement <vscale x 16 x i8> poison, i8 -7, i32 0 206 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer 207 %vc = udiv <vscale x 16 x i8> %va, %splat 208 ret <vscale x 16 x i8> %vc 209} 210 211define <vscale x 32 x i8> @vdivu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) { 212; CHECK-LABEL: vdivu_vv_nxv32i8: 213; CHECK: # %bb.0: 214; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu 215; CHECK-NEXT: vdivu.vv v8, v8, v12 216; CHECK-NEXT: ret 217 %vc = udiv <vscale x 32 x i8> %va, %vb 218 ret <vscale x 32 x i8> %vc 219} 220 221define <vscale x 32 x i8> @vdivu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) { 222; CHECK-LABEL: vdivu_vx_nxv32i8: 223; CHECK: # %bb.0: 224; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 225; CHECK-NEXT: vdivu.vx v8, v8, a0 226; CHECK-NEXT: ret 227 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0 228 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer 229 %vc = udiv <vscale x 32 x i8> %va, %splat 230 ret <vscale x 32 x i8> %vc 231} 232 233define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) { 234; CHECK-LABEL: vdivu_vi_nxv32i8_0: 235; CHECK: # %bb.0: 236; CHECK-NEXT: li a0, 33 237; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 238; CHECK-NEXT: vmulhu.vx v8, v8, a0 239; CHECK-NEXT: vsrl.vi v8, v8, 5 240; CHECK-NEXT: ret 241 %head = insertelement <vscale x 32 x i8> poison, i8 -7, i32 0 242 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer 243 %vc = udiv <vscale x 32 x i8> %va, %splat 244 ret <vscale x 32 x i8> %vc 245} 246 247define <vscale x 64 x i8> @vdivu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) { 248; CHECK-LABEL: vdivu_vv_nxv64i8: 249; CHECK: # %bb.0: 250; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu 251; CHECK-NEXT: vdivu.vv v8, v8, v16 252; CHECK-NEXT: ret 253 %vc = udiv <vscale x 64 x i8> %va, %vb 254 ret <vscale x 64 x i8> %vc 255} 256 257define <vscale x 64 x i8> @vdivu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) { 258; CHECK-LABEL: vdivu_vx_nxv64i8: 259; CHECK: # %bb.0: 260; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 261; CHECK-NEXT: vdivu.vx v8, v8, a0 262; CHECK-NEXT: ret 263 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0 264 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer 265 %vc = udiv <vscale x 64 x i8> %va, %splat 266 ret <vscale x 64 x i8> %vc 267} 268 269define <vscale x 64 x i8> @vdivu_vi_nxv64i8_0(<vscale x 64 x i8> %va) { 270; CHECK-LABEL: vdivu_vi_nxv64i8_0: 271; CHECK: # %bb.0: 272; CHECK-NEXT: li a0, 33 273; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 274; CHECK-NEXT: vmulhu.vx v8, v8, a0 275; CHECK-NEXT: vsrl.vi v8, v8, 5 276; CHECK-NEXT: ret 277 %head = insertelement <vscale x 64 x i8> poison, i8 -7, i32 0 278 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer 279 %vc = udiv <vscale x 64 x i8> %va, %splat 280 ret <vscale x 64 x i8> %vc 281} 282 283define <vscale x 1 x i16> @vdivu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) { 284; CHECK-LABEL: vdivu_vv_nxv1i16: 285; CHECK: # %bb.0: 286; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu 287; CHECK-NEXT: vdivu.vv v8, v8, v9 288; CHECK-NEXT: ret 289 %vc = udiv <vscale x 1 x i16> %va, %vb 290 ret <vscale x 1 x i16> %vc 291} 292 293define <vscale x 1 x i16> @vdivu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) { 294; CHECK-LABEL: vdivu_vx_nxv1i16: 295; CHECK: # %bb.0: 296; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 297; CHECK-NEXT: vdivu.vx v8, v8, a0 298; CHECK-NEXT: ret 299 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0 300 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer 301 %vc = udiv <vscale x 1 x i16> %va, %splat 302 ret <vscale x 1 x i16> %vc 303} 304 305define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) { 306; RV32-LABEL: vdivu_vi_nxv1i16_0: 307; RV32: # %bb.0: 308; RV32-NEXT: lui a0, 2 309; RV32-NEXT: addi a0, a0, 1 310; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 311; RV32-NEXT: vmulhu.vx v8, v8, a0 312; RV32-NEXT: vsrl.vi v8, v8, 13 313; RV32-NEXT: ret 314; 315; RV64-LABEL: vdivu_vi_nxv1i16_0: 316; RV64: # %bb.0: 317; RV64-NEXT: lui a0, 2 318; RV64-NEXT: addiw a0, a0, 1 319; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 320; RV64-NEXT: vmulhu.vx v8, v8, a0 321; RV64-NEXT: vsrl.vi v8, v8, 13 322; RV64-NEXT: ret 323 %head = insertelement <vscale x 1 x i16> poison, i16 -7, i32 0 324 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer 325 %vc = udiv <vscale x 1 x i16> %va, %splat 326 ret <vscale x 1 x i16> %vc 327} 328 329define <vscale x 2 x i16> @vdivu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) { 330; CHECK-LABEL: vdivu_vv_nxv2i16: 331; CHECK: # %bb.0: 332; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu 333; CHECK-NEXT: vdivu.vv v8, v8, v9 334; CHECK-NEXT: ret 335 %vc = udiv <vscale x 2 x i16> %va, %vb 336 ret <vscale x 2 x i16> %vc 337} 338 339define <vscale x 2 x i16> @vdivu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) { 340; CHECK-LABEL: vdivu_vx_nxv2i16: 341; CHECK: # %bb.0: 342; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 343; CHECK-NEXT: vdivu.vx v8, v8, a0 344; CHECK-NEXT: ret 345 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0 346 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer 347 %vc = udiv <vscale x 2 x i16> %va, %splat 348 ret <vscale x 2 x i16> %vc 349} 350 351define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) { 352; RV32-LABEL: vdivu_vi_nxv2i16_0: 353; RV32: # %bb.0: 354; RV32-NEXT: lui a0, 2 355; RV32-NEXT: addi a0, a0, 1 356; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 357; RV32-NEXT: vmulhu.vx v8, v8, a0 358; RV32-NEXT: vsrl.vi v8, v8, 13 359; RV32-NEXT: ret 360; 361; RV64-LABEL: vdivu_vi_nxv2i16_0: 362; RV64: # %bb.0: 363; RV64-NEXT: lui a0, 2 364; RV64-NEXT: addiw a0, a0, 1 365; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 366; RV64-NEXT: vmulhu.vx v8, v8, a0 367; RV64-NEXT: vsrl.vi v8, v8, 13 368; RV64-NEXT: ret 369 %head = insertelement <vscale x 2 x i16> poison, i16 -7, i32 0 370 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer 371 %vc = udiv <vscale x 2 x i16> %va, %splat 372 ret <vscale x 2 x i16> %vc 373} 374 375define <vscale x 4 x i16> @vdivu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) { 376; CHECK-LABEL: vdivu_vv_nxv4i16: 377; CHECK: # %bb.0: 378; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu 379; CHECK-NEXT: vdivu.vv v8, v8, v9 380; CHECK-NEXT: ret 381 %vc = udiv <vscale x 4 x i16> %va, %vb 382 ret <vscale x 4 x i16> %vc 383} 384 385define <vscale x 4 x i16> @vdivu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) { 386; CHECK-LABEL: vdivu_vx_nxv4i16: 387; CHECK: # %bb.0: 388; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu 389; CHECK-NEXT: vdivu.vx v8, v8, a0 390; CHECK-NEXT: ret 391 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0 392 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer 393 %vc = udiv <vscale x 4 x i16> %va, %splat 394 ret <vscale x 4 x i16> %vc 395} 396 397define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) { 398; RV32-LABEL: vdivu_vi_nxv4i16_0: 399; RV32: # %bb.0: 400; RV32-NEXT: lui a0, 2 401; RV32-NEXT: addi a0, a0, 1 402; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu 403; RV32-NEXT: vmulhu.vx v8, v8, a0 404; RV32-NEXT: vsrl.vi v8, v8, 13 405; RV32-NEXT: ret 406; 407; RV64-LABEL: vdivu_vi_nxv4i16_0: 408; RV64: # %bb.0: 409; RV64-NEXT: lui a0, 2 410; RV64-NEXT: addiw a0, a0, 1 411; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu 412; RV64-NEXT: vmulhu.vx v8, v8, a0 413; RV64-NEXT: vsrl.vi v8, v8, 13 414; RV64-NEXT: ret 415 %head = insertelement <vscale x 4 x i16> poison, i16 -7, i32 0 416 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer 417 %vc = udiv <vscale x 4 x i16> %va, %splat 418 ret <vscale x 4 x i16> %vc 419} 420 421define <vscale x 8 x i16> @vdivu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 422; CHECK-LABEL: vdivu_vv_nxv8i16: 423; CHECK: # %bb.0: 424; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu 425; CHECK-NEXT: vdivu.vv v8, v8, v10 426; CHECK-NEXT: ret 427 %vc = udiv <vscale x 8 x i16> %va, %vb 428 ret <vscale x 8 x i16> %vc 429} 430 431define <vscale x 8 x i16> @vdivu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) { 432; CHECK-LABEL: vdivu_vx_nxv8i16: 433; CHECK: # %bb.0: 434; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu 435; CHECK-NEXT: vdivu.vx v8, v8, a0 436; CHECK-NEXT: ret 437 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 438 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 439 %vc = udiv <vscale x 8 x i16> %va, %splat 440 ret <vscale x 8 x i16> %vc 441} 442 443define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 444; RV32-LABEL: vdivu_vi_nxv8i16_0: 445; RV32: # %bb.0: 446; RV32-NEXT: lui a0, 2 447; RV32-NEXT: addi a0, a0, 1 448; RV32-NEXT: vsetvli a1, zero, e16, m2, ta, mu 449; RV32-NEXT: vmulhu.vx v8, v8, a0 450; RV32-NEXT: vsrl.vi v8, v8, 13 451; RV32-NEXT: ret 452; 453; RV64-LABEL: vdivu_vi_nxv8i16_0: 454; RV64: # %bb.0: 455; RV64-NEXT: lui a0, 2 456; RV64-NEXT: addiw a0, a0, 1 457; RV64-NEXT: vsetvli a1, zero, e16, m2, ta, mu 458; RV64-NEXT: vmulhu.vx v8, v8, a0 459; RV64-NEXT: vsrl.vi v8, v8, 13 460; RV64-NEXT: ret 461 %head = insertelement <vscale x 8 x i16> poison, i16 -7, i32 0 462 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 463 %vc = udiv <vscale x 8 x i16> %va, %splat 464 ret <vscale x 8 x i16> %vc 465} 466 467define <vscale x 16 x i16> @vdivu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) { 468; CHECK-LABEL: vdivu_vv_nxv16i16: 469; CHECK: # %bb.0: 470; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 471; CHECK-NEXT: vdivu.vv v8, v8, v12 472; CHECK-NEXT: ret 473 %vc = udiv <vscale x 16 x i16> %va, %vb 474 ret <vscale x 16 x i16> %vc 475} 476 477define <vscale x 16 x i16> @vdivu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) { 478; CHECK-LABEL: vdivu_vx_nxv16i16: 479; CHECK: # %bb.0: 480; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu 481; CHECK-NEXT: vdivu.vx v8, v8, a0 482; CHECK-NEXT: ret 483 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0 484 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 485 %vc = udiv <vscale x 16 x i16> %va, %splat 486 ret <vscale x 16 x i16> %vc 487} 488 489define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) { 490; RV32-LABEL: vdivu_vi_nxv16i16_0: 491; RV32: # %bb.0: 492; RV32-NEXT: lui a0, 2 493; RV32-NEXT: addi a0, a0, 1 494; RV32-NEXT: vsetvli a1, zero, e16, m4, ta, mu 495; RV32-NEXT: vmulhu.vx v8, v8, a0 496; RV32-NEXT: vsrl.vi v8, v8, 13 497; RV32-NEXT: ret 498; 499; RV64-LABEL: vdivu_vi_nxv16i16_0: 500; RV64: # %bb.0: 501; RV64-NEXT: lui a0, 2 502; RV64-NEXT: addiw a0, a0, 1 503; RV64-NEXT: vsetvli a1, zero, e16, m4, ta, mu 504; RV64-NEXT: vmulhu.vx v8, v8, a0 505; RV64-NEXT: vsrl.vi v8, v8, 13 506; RV64-NEXT: ret 507 %head = insertelement <vscale x 16 x i16> poison, i16 -7, i32 0 508 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 509 %vc = udiv <vscale x 16 x i16> %va, %splat 510 ret <vscale x 16 x i16> %vc 511} 512 513define <vscale x 32 x i16> @vdivu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) { 514; CHECK-LABEL: vdivu_vv_nxv32i16: 515; CHECK: # %bb.0: 516; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu 517; CHECK-NEXT: vdivu.vv v8, v8, v16 518; CHECK-NEXT: ret 519 %vc = udiv <vscale x 32 x i16> %va, %vb 520 ret <vscale x 32 x i16> %vc 521} 522 523define <vscale x 32 x i16> @vdivu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) { 524; CHECK-LABEL: vdivu_vx_nxv32i16: 525; CHECK: # %bb.0: 526; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu 527; CHECK-NEXT: vdivu.vx v8, v8, a0 528; CHECK-NEXT: ret 529 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0 530 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer 531 %vc = udiv <vscale x 32 x i16> %va, %splat 532 ret <vscale x 32 x i16> %vc 533} 534 535define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) { 536; RV32-LABEL: vdivu_vi_nxv32i16_0: 537; RV32: # %bb.0: 538; RV32-NEXT: lui a0, 2 539; RV32-NEXT: addi a0, a0, 1 540; RV32-NEXT: vsetvli a1, zero, e16, m8, ta, mu 541; RV32-NEXT: vmulhu.vx v8, v8, a0 542; RV32-NEXT: vsrl.vi v8, v8, 13 543; RV32-NEXT: ret 544; 545; RV64-LABEL: vdivu_vi_nxv32i16_0: 546; RV64: # %bb.0: 547; RV64-NEXT: lui a0, 2 548; RV64-NEXT: addiw a0, a0, 1 549; RV64-NEXT: vsetvli a1, zero, e16, m8, ta, mu 550; RV64-NEXT: vmulhu.vx v8, v8, a0 551; RV64-NEXT: vsrl.vi v8, v8, 13 552; RV64-NEXT: ret 553 %head = insertelement <vscale x 32 x i16> poison, i16 -7, i32 0 554 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer 555 %vc = udiv <vscale x 32 x i16> %va, %splat 556 ret <vscale x 32 x i16> %vc 557} 558 559define <vscale x 1 x i32> @vdivu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) { 560; CHECK-LABEL: vdivu_vv_nxv1i32: 561; CHECK: # %bb.0: 562; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu 563; CHECK-NEXT: vdivu.vv v8, v8, v9 564; CHECK-NEXT: ret 565 %vc = udiv <vscale x 1 x i32> %va, %vb 566 ret <vscale x 1 x i32> %vc 567} 568 569define <vscale x 1 x i32> @vdivu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) { 570; CHECK-LABEL: vdivu_vx_nxv1i32: 571; CHECK: # %bb.0: 572; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 573; CHECK-NEXT: vdivu.vx v8, v8, a0 574; CHECK-NEXT: ret 575 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 576 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer 577 %vc = udiv <vscale x 1 x i32> %va, %splat 578 ret <vscale x 1 x i32> %vc 579} 580 581define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) { 582; RV32-LABEL: vdivu_vi_nxv1i32_0: 583; RV32: # %bb.0: 584; RV32-NEXT: lui a0, 131072 585; RV32-NEXT: addi a0, a0, 1 586; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 587; RV32-NEXT: vmulhu.vx v8, v8, a0 588; RV32-NEXT: vsrl.vi v8, v8, 29 589; RV32-NEXT: ret 590; 591; RV64-LABEL: vdivu_vi_nxv1i32_0: 592; RV64: # %bb.0: 593; RV64-NEXT: lui a0, 131072 594; RV64-NEXT: addiw a0, a0, 1 595; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 596; RV64-NEXT: vmulhu.vx v8, v8, a0 597; RV64-NEXT: vsrl.vi v8, v8, 29 598; RV64-NEXT: ret 599 %head = insertelement <vscale x 1 x i32> poison, i32 -7, i32 0 600 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer 601 %vc = udiv <vscale x 1 x i32> %va, %splat 602 ret <vscale x 1 x i32> %vc 603} 604 605define <vscale x 2 x i32> @vdivu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) { 606; CHECK-LABEL: vdivu_vv_nxv2i32: 607; CHECK: # %bb.0: 608; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu 609; CHECK-NEXT: vdivu.vv v8, v8, v9 610; CHECK-NEXT: ret 611 %vc = udiv <vscale x 2 x i32> %va, %vb 612 ret <vscale x 2 x i32> %vc 613} 614 615define <vscale x 2 x i32> @vdivu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) { 616; CHECK-LABEL: vdivu_vx_nxv2i32: 617; CHECK: # %bb.0: 618; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu 619; CHECK-NEXT: vdivu.vx v8, v8, a0 620; CHECK-NEXT: ret 621 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 622 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer 623 %vc = udiv <vscale x 2 x i32> %va, %splat 624 ret <vscale x 2 x i32> %vc 625} 626 627define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) { 628; RV32-LABEL: vdivu_vi_nxv2i32_0: 629; RV32: # %bb.0: 630; RV32-NEXT: lui a0, 131072 631; RV32-NEXT: addi a0, a0, 1 632; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu 633; RV32-NEXT: vmulhu.vx v8, v8, a0 634; RV32-NEXT: vsrl.vi v8, v8, 29 635; RV32-NEXT: ret 636; 637; RV64-LABEL: vdivu_vi_nxv2i32_0: 638; RV64: # %bb.0: 639; RV64-NEXT: lui a0, 131072 640; RV64-NEXT: addiw a0, a0, 1 641; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu 642; RV64-NEXT: vmulhu.vx v8, v8, a0 643; RV64-NEXT: vsrl.vi v8, v8, 29 644; RV64-NEXT: ret 645 %head = insertelement <vscale x 2 x i32> poison, i32 -7, i32 0 646 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer 647 %vc = udiv <vscale x 2 x i32> %va, %splat 648 ret <vscale x 2 x i32> %vc 649} 650 651define <vscale x 4 x i32> @vdivu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) { 652; CHECK-LABEL: vdivu_vv_nxv4i32: 653; CHECK: # %bb.0: 654; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu 655; CHECK-NEXT: vdivu.vv v8, v8, v10 656; CHECK-NEXT: ret 657 %vc = udiv <vscale x 4 x i32> %va, %vb 658 ret <vscale x 4 x i32> %vc 659} 660 661define <vscale x 4 x i32> @vdivu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) { 662; CHECK-LABEL: vdivu_vx_nxv4i32: 663; CHECK: # %bb.0: 664; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu 665; CHECK-NEXT: vdivu.vx v8, v8, a0 666; CHECK-NEXT: ret 667 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 668 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 669 %vc = udiv <vscale x 4 x i32> %va, %splat 670 ret <vscale x 4 x i32> %vc 671} 672 673define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) { 674; RV32-LABEL: vdivu_vi_nxv4i32_0: 675; RV32: # %bb.0: 676; RV32-NEXT: lui a0, 131072 677; RV32-NEXT: addi a0, a0, 1 678; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu 679; RV32-NEXT: vmulhu.vx v8, v8, a0 680; RV32-NEXT: vsrl.vi v8, v8, 29 681; RV32-NEXT: ret 682; 683; RV64-LABEL: vdivu_vi_nxv4i32_0: 684; RV64: # %bb.0: 685; RV64-NEXT: lui a0, 131072 686; RV64-NEXT: addiw a0, a0, 1 687; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, mu 688; RV64-NEXT: vmulhu.vx v8, v8, a0 689; RV64-NEXT: vsrl.vi v8, v8, 29 690; RV64-NEXT: ret 691 %head = insertelement <vscale x 4 x i32> poison, i32 -7, i32 0 692 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 693 %vc = udiv <vscale x 4 x i32> %va, %splat 694 ret <vscale x 4 x i32> %vc 695} 696 697define <vscale x 8 x i32> @vdivu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 698; CHECK-LABEL: vdivu_vv_nxv8i32: 699; CHECK: # %bb.0: 700; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu 701; CHECK-NEXT: vdivu.vv v8, v8, v12 702; CHECK-NEXT: ret 703 %vc = udiv <vscale x 8 x i32> %va, %vb 704 ret <vscale x 8 x i32> %vc 705} 706 707define <vscale x 8 x i32> @vdivu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) { 708; CHECK-LABEL: vdivu_vx_nxv8i32: 709; CHECK: # %bb.0: 710; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu 711; CHECK-NEXT: vdivu.vx v8, v8, a0 712; CHECK-NEXT: ret 713 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 714 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 715 %vc = udiv <vscale x 8 x i32> %va, %splat 716 ret <vscale x 8 x i32> %vc 717} 718 719define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 720; RV32-LABEL: vdivu_vi_nxv8i32_0: 721; RV32: # %bb.0: 722; RV32-NEXT: lui a0, 131072 723; RV32-NEXT: addi a0, a0, 1 724; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu 725; RV32-NEXT: vmulhu.vx v8, v8, a0 726; RV32-NEXT: vsrl.vi v8, v8, 29 727; RV32-NEXT: ret 728; 729; RV64-LABEL: vdivu_vi_nxv8i32_0: 730; RV64: # %bb.0: 731; RV64-NEXT: lui a0, 131072 732; RV64-NEXT: addiw a0, a0, 1 733; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, mu 734; RV64-NEXT: vmulhu.vx v8, v8, a0 735; RV64-NEXT: vsrl.vi v8, v8, 29 736; RV64-NEXT: ret 737 %head = insertelement <vscale x 8 x i32> poison, i32 -7, i32 0 738 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 739 %vc = udiv <vscale x 8 x i32> %va, %splat 740 ret <vscale x 8 x i32> %vc 741} 742 743define <vscale x 16 x i32> @vdivu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) { 744; CHECK-LABEL: vdivu_vv_nxv16i32: 745; CHECK: # %bb.0: 746; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 747; CHECK-NEXT: vdivu.vv v8, v8, v16 748; CHECK-NEXT: ret 749 %vc = udiv <vscale x 16 x i32> %va, %vb 750 ret <vscale x 16 x i32> %vc 751} 752 753define <vscale x 16 x i32> @vdivu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) { 754; CHECK-LABEL: vdivu_vx_nxv16i32: 755; CHECK: # %bb.0: 756; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu 757; CHECK-NEXT: vdivu.vx v8, v8, a0 758; CHECK-NEXT: ret 759 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0 760 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 761 %vc = udiv <vscale x 16 x i32> %va, %splat 762 ret <vscale x 16 x i32> %vc 763} 764 765define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) { 766; RV32-LABEL: vdivu_vi_nxv16i32_0: 767; RV32: # %bb.0: 768; RV32-NEXT: lui a0, 131072 769; RV32-NEXT: addi a0, a0, 1 770; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, mu 771; RV32-NEXT: vmulhu.vx v8, v8, a0 772; RV32-NEXT: vsrl.vi v8, v8, 29 773; RV32-NEXT: ret 774; 775; RV64-LABEL: vdivu_vi_nxv16i32_0: 776; RV64: # %bb.0: 777; RV64-NEXT: lui a0, 131072 778; RV64-NEXT: addiw a0, a0, 1 779; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, mu 780; RV64-NEXT: vmulhu.vx v8, v8, a0 781; RV64-NEXT: vsrl.vi v8, v8, 29 782; RV64-NEXT: ret 783 %head = insertelement <vscale x 16 x i32> poison, i32 -7, i32 0 784 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 785 %vc = udiv <vscale x 16 x i32> %va, %splat 786 ret <vscale x 16 x i32> %vc 787} 788 789define <vscale x 1 x i64> @vdivu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) { 790; CHECK-LABEL: vdivu_vv_nxv1i64: 791; CHECK: # %bb.0: 792; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 793; CHECK-NEXT: vdivu.vv v8, v8, v9 794; CHECK-NEXT: ret 795 %vc = udiv <vscale x 1 x i64> %va, %vb 796 ret <vscale x 1 x i64> %vc 797} 798 799define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { 800; RV32-LABEL: vdivu_vx_nxv1i64: 801; RV32: # %bb.0: 802; RV32-NEXT: addi sp, sp, -16 803; RV32-NEXT: .cfi_def_cfa_offset 16 804; RV32-NEXT: sw a1, 12(sp) 805; RV32-NEXT: sw a0, 8(sp) 806; RV32-NEXT: addi a0, sp, 8 807; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu 808; RV32-NEXT: vlse64.v v9, (a0), zero 809; RV32-NEXT: vdivu.vv v8, v8, v9 810; RV32-NEXT: addi sp, sp, 16 811; RV32-NEXT: ret 812; 813; RV64-LABEL: vdivu_vx_nxv1i64: 814; RV64: # %bb.0: 815; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu 816; RV64-NEXT: vdivu.vx v8, v8, a0 817; RV64-NEXT: ret 818 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 819 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 820 %vc = udiv <vscale x 1 x i64> %va, %splat 821 ret <vscale x 1 x i64> %vc 822} 823 824define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) { 825; RV32-V-LABEL: vdivu_vi_nxv1i64_0: 826; RV32-V: # %bb.0: 827; RV32-V-NEXT: addi sp, sp, -16 828; RV32-V-NEXT: .cfi_def_cfa_offset 16 829; RV32-V-NEXT: lui a0, 131072 830; RV32-V-NEXT: sw a0, 12(sp) 831; RV32-V-NEXT: li a0, 1 832; RV32-V-NEXT: sw a0, 8(sp) 833; RV32-V-NEXT: addi a0, sp, 8 834; RV32-V-NEXT: vsetvli a1, zero, e64, m1, ta, mu 835; RV32-V-NEXT: vlse64.v v9, (a0), zero 836; RV32-V-NEXT: vmulhu.vv v8, v8, v9 837; RV32-V-NEXT: li a0, 61 838; RV32-V-NEXT: vsrl.vx v8, v8, a0 839; RV32-V-NEXT: addi sp, sp, 16 840; RV32-V-NEXT: ret 841; 842; ZVE64X-LABEL: vdivu_vi_nxv1i64_0: 843; ZVE64X: # %bb.0: 844; ZVE64X-NEXT: li a0, -7 845; ZVE64X-NEXT: vsetvli a1, zero, e64, m1, ta, mu 846; ZVE64X-NEXT: vdivu.vx v8, v8, a0 847; ZVE64X-NEXT: ret 848; 849; RV64-V-LABEL: vdivu_vi_nxv1i64_0: 850; RV64-V: # %bb.0: 851; RV64-V-NEXT: li a0, 1 852; RV64-V-NEXT: slli a0, a0, 61 853; RV64-V-NEXT: addi a0, a0, 1 854; RV64-V-NEXT: vsetvli a1, zero, e64, m1, ta, mu 855; RV64-V-NEXT: vmulhu.vx v8, v8, a0 856; RV64-V-NEXT: li a0, 61 857; RV64-V-NEXT: vsrl.vx v8, v8, a0 858; RV64-V-NEXT: ret 859 %head = insertelement <vscale x 1 x i64> poison, i64 -7, i32 0 860 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 861 %vc = udiv <vscale x 1 x i64> %va, %splat 862 ret <vscale x 1 x i64> %vc 863} 864 865define <vscale x 1 x i64> @vdivu_vi_nxv1i64_1(<vscale x 1 x i64> %va) { 866; CHECK-LABEL: vdivu_vi_nxv1i64_1: 867; CHECK: # %bb.0: 868; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 869; CHECK-NEXT: vsrl.vi v8, v8, 1 870; CHECK-NEXT: ret 871 %head = insertelement <vscale x 1 x i64> poison, i64 2, i32 0 872 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 873 %vc = udiv <vscale x 1 x i64> %va, %splat 874 ret <vscale x 1 x i64> %vc 875} 876 877; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 878define <vscale x 1 x i64> @vdivu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) { 879; CHECK-LABEL: vdivu_vi_nxv1i64_2: 880; CHECK: # %bb.0: 881; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 882; CHECK-NEXT: vadd.vi v9, v9, 4 883; CHECK-NEXT: vsrl.vv v8, v8, v9 884; CHECK-NEXT: ret 885 %head = insertelement <vscale x 1 x i64> poison, i64 16, i32 0 886 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 887 %vc = shl <vscale x 1 x i64> %splat, %vb 888 %vd = udiv <vscale x 1 x i64> %va, %vc 889 ret <vscale x 1 x i64> %vd 890} 891 892define <vscale x 2 x i64> @vdivu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) { 893; CHECK-LABEL: vdivu_vv_nxv2i64: 894; CHECK: # %bb.0: 895; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 896; CHECK-NEXT: vdivu.vv v8, v8, v10 897; CHECK-NEXT: ret 898 %vc = udiv <vscale x 2 x i64> %va, %vb 899 ret <vscale x 2 x i64> %vc 900} 901 902define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { 903; RV32-LABEL: vdivu_vx_nxv2i64: 904; RV32: # %bb.0: 905; RV32-NEXT: addi sp, sp, -16 906; RV32-NEXT: .cfi_def_cfa_offset 16 907; RV32-NEXT: sw a1, 12(sp) 908; RV32-NEXT: sw a0, 8(sp) 909; RV32-NEXT: addi a0, sp, 8 910; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu 911; RV32-NEXT: vlse64.v v10, (a0), zero 912; RV32-NEXT: vdivu.vv v8, v8, v10 913; RV32-NEXT: addi sp, sp, 16 914; RV32-NEXT: ret 915; 916; RV64-LABEL: vdivu_vx_nxv2i64: 917; RV64: # %bb.0: 918; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu 919; RV64-NEXT: vdivu.vx v8, v8, a0 920; RV64-NEXT: ret 921 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 922 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 923 %vc = udiv <vscale x 2 x i64> %va, %splat 924 ret <vscale x 2 x i64> %vc 925} 926 927define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) { 928; RV32-V-LABEL: vdivu_vi_nxv2i64_0: 929; RV32-V: # %bb.0: 930; RV32-V-NEXT: addi sp, sp, -16 931; RV32-V-NEXT: .cfi_def_cfa_offset 16 932; RV32-V-NEXT: lui a0, 131072 933; RV32-V-NEXT: sw a0, 12(sp) 934; RV32-V-NEXT: li a0, 1 935; RV32-V-NEXT: sw a0, 8(sp) 936; RV32-V-NEXT: addi a0, sp, 8 937; RV32-V-NEXT: vsetvli a1, zero, e64, m2, ta, mu 938; RV32-V-NEXT: vlse64.v v10, (a0), zero 939; RV32-V-NEXT: vmulhu.vv v8, v8, v10 940; RV32-V-NEXT: li a0, 61 941; RV32-V-NEXT: vsrl.vx v8, v8, a0 942; RV32-V-NEXT: addi sp, sp, 16 943; RV32-V-NEXT: ret 944; 945; ZVE64X-LABEL: vdivu_vi_nxv2i64_0: 946; ZVE64X: # %bb.0: 947; ZVE64X-NEXT: li a0, -7 948; ZVE64X-NEXT: vsetvli a1, zero, e64, m2, ta, mu 949; ZVE64X-NEXT: vdivu.vx v8, v8, a0 950; ZVE64X-NEXT: ret 951; 952; RV64-V-LABEL: vdivu_vi_nxv2i64_0: 953; RV64-V: # %bb.0: 954; RV64-V-NEXT: li a0, 1 955; RV64-V-NEXT: slli a0, a0, 61 956; RV64-V-NEXT: addi a0, a0, 1 957; RV64-V-NEXT: vsetvli a1, zero, e64, m2, ta, mu 958; RV64-V-NEXT: vmulhu.vx v8, v8, a0 959; RV64-V-NEXT: li a0, 61 960; RV64-V-NEXT: vsrl.vx v8, v8, a0 961; RV64-V-NEXT: ret 962 %head = insertelement <vscale x 2 x i64> poison, i64 -7, i32 0 963 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 964 %vc = udiv <vscale x 2 x i64> %va, %splat 965 ret <vscale x 2 x i64> %vc 966} 967 968define <vscale x 2 x i64> @vdivu_vi_nxv2i64_1(<vscale x 2 x i64> %va) { 969; CHECK-LABEL: vdivu_vi_nxv2i64_1: 970; CHECK: # %bb.0: 971; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 972; CHECK-NEXT: vsrl.vi v8, v8, 1 973; CHECK-NEXT: ret 974 %head = insertelement <vscale x 2 x i64> poison, i64 2, i32 0 975 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 976 %vc = udiv <vscale x 2 x i64> %va, %splat 977 ret <vscale x 2 x i64> %vc 978} 979 980; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 981define <vscale x 2 x i64> @vdivu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) { 982; CHECK-LABEL: vdivu_vi_nxv2i64_2: 983; CHECK: # %bb.0: 984; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 985; CHECK-NEXT: vadd.vi v10, v10, 4 986; CHECK-NEXT: vsrl.vv v8, v8, v10 987; CHECK-NEXT: ret 988 %head = insertelement <vscale x 2 x i64> poison, i64 16, i32 0 989 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 990 %vc = shl <vscale x 2 x i64> %splat, %vb 991 %vd = udiv <vscale x 2 x i64> %va, %vc 992 ret <vscale x 2 x i64> %vd 993} 994 995define <vscale x 4 x i64> @vdivu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) { 996; CHECK-LABEL: vdivu_vv_nxv4i64: 997; CHECK: # %bb.0: 998; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 999; CHECK-NEXT: vdivu.vv v8, v8, v12 1000; CHECK-NEXT: ret 1001 %vc = udiv <vscale x 4 x i64> %va, %vb 1002 ret <vscale x 4 x i64> %vc 1003} 1004 1005define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { 1006; RV32-LABEL: vdivu_vx_nxv4i64: 1007; RV32: # %bb.0: 1008; RV32-NEXT: addi sp, sp, -16 1009; RV32-NEXT: .cfi_def_cfa_offset 16 1010; RV32-NEXT: sw a1, 12(sp) 1011; RV32-NEXT: sw a0, 8(sp) 1012; RV32-NEXT: addi a0, sp, 8 1013; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1014; RV32-NEXT: vlse64.v v12, (a0), zero 1015; RV32-NEXT: vdivu.vv v8, v8, v12 1016; RV32-NEXT: addi sp, sp, 16 1017; RV32-NEXT: ret 1018; 1019; RV64-LABEL: vdivu_vx_nxv4i64: 1020; RV64: # %bb.0: 1021; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1022; RV64-NEXT: vdivu.vx v8, v8, a0 1023; RV64-NEXT: ret 1024 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 1025 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 1026 %vc = udiv <vscale x 4 x i64> %va, %splat 1027 ret <vscale x 4 x i64> %vc 1028} 1029 1030define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) { 1031; RV32-V-LABEL: vdivu_vi_nxv4i64_0: 1032; RV32-V: # %bb.0: 1033; RV32-V-NEXT: addi sp, sp, -16 1034; RV32-V-NEXT: .cfi_def_cfa_offset 16 1035; RV32-V-NEXT: lui a0, 131072 1036; RV32-V-NEXT: sw a0, 12(sp) 1037; RV32-V-NEXT: li a0, 1 1038; RV32-V-NEXT: sw a0, 8(sp) 1039; RV32-V-NEXT: addi a0, sp, 8 1040; RV32-V-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1041; RV32-V-NEXT: vlse64.v v12, (a0), zero 1042; RV32-V-NEXT: vmulhu.vv v8, v8, v12 1043; RV32-V-NEXT: li a0, 61 1044; RV32-V-NEXT: vsrl.vx v8, v8, a0 1045; RV32-V-NEXT: addi sp, sp, 16 1046; RV32-V-NEXT: ret 1047; 1048; ZVE64X-LABEL: vdivu_vi_nxv4i64_0: 1049; ZVE64X: # %bb.0: 1050; ZVE64X-NEXT: li a0, -7 1051; ZVE64X-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1052; ZVE64X-NEXT: vdivu.vx v8, v8, a0 1053; ZVE64X-NEXT: ret 1054; 1055; RV64-V-LABEL: vdivu_vi_nxv4i64_0: 1056; RV64-V: # %bb.0: 1057; RV64-V-NEXT: li a0, 1 1058; RV64-V-NEXT: slli a0, a0, 61 1059; RV64-V-NEXT: addi a0, a0, 1 1060; RV64-V-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1061; RV64-V-NEXT: vmulhu.vx v8, v8, a0 1062; RV64-V-NEXT: li a0, 61 1063; RV64-V-NEXT: vsrl.vx v8, v8, a0 1064; RV64-V-NEXT: ret 1065 %head = insertelement <vscale x 4 x i64> poison, i64 -7, i32 0 1066 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 1067 %vc = udiv <vscale x 4 x i64> %va, %splat 1068 ret <vscale x 4 x i64> %vc 1069} 1070 1071define <vscale x 4 x i64> @vdivu_vi_nxv4i64_1(<vscale x 4 x i64> %va) { 1072; CHECK-LABEL: vdivu_vi_nxv4i64_1: 1073; CHECK: # %bb.0: 1074; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1075; CHECK-NEXT: vsrl.vi v8, v8, 1 1076; CHECK-NEXT: ret 1077 %head = insertelement <vscale x 4 x i64> poison, i64 2, i32 0 1078 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 1079 %vc = udiv <vscale x 4 x i64> %va, %splat 1080 ret <vscale x 4 x i64> %vc 1081} 1082 1083; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 1084define <vscale x 4 x i64> @vdivu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) { 1085; CHECK-LABEL: vdivu_vi_nxv4i64_2: 1086; CHECK: # %bb.0: 1087; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1088; CHECK-NEXT: vadd.vi v12, v12, 4 1089; CHECK-NEXT: vsrl.vv v8, v8, v12 1090; CHECK-NEXT: ret 1091 %head = insertelement <vscale x 4 x i64> poison, i64 16, i32 0 1092 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 1093 %vc = shl <vscale x 4 x i64> %splat, %vb 1094 %vd = udiv <vscale x 4 x i64> %va, %vc 1095 ret <vscale x 4 x i64> %vd 1096} 1097 1098define <vscale x 8 x i64> @vdivu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 1099; CHECK-LABEL: vdivu_vv_nxv8i64: 1100; CHECK: # %bb.0: 1101; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1102; CHECK-NEXT: vdivu.vv v8, v8, v16 1103; CHECK-NEXT: ret 1104 %vc = udiv <vscale x 8 x i64> %va, %vb 1105 ret <vscale x 8 x i64> %vc 1106} 1107 1108define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 1109; RV32-LABEL: vdivu_vx_nxv8i64: 1110; RV32: # %bb.0: 1111; RV32-NEXT: addi sp, sp, -16 1112; RV32-NEXT: .cfi_def_cfa_offset 16 1113; RV32-NEXT: sw a1, 12(sp) 1114; RV32-NEXT: sw a0, 8(sp) 1115; RV32-NEXT: addi a0, sp, 8 1116; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1117; RV32-NEXT: vlse64.v v16, (a0), zero 1118; RV32-NEXT: vdivu.vv v8, v8, v16 1119; RV32-NEXT: addi sp, sp, 16 1120; RV32-NEXT: ret 1121; 1122; RV64-LABEL: vdivu_vx_nxv8i64: 1123; RV64: # %bb.0: 1124; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1125; RV64-NEXT: vdivu.vx v8, v8, a0 1126; RV64-NEXT: ret 1127 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 1128 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 1129 %vc = udiv <vscale x 8 x i64> %va, %splat 1130 ret <vscale x 8 x i64> %vc 1131} 1132 1133define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 1134; RV32-V-LABEL: vdivu_vi_nxv8i64_0: 1135; RV32-V: # %bb.0: 1136; RV32-V-NEXT: addi sp, sp, -16 1137; RV32-V-NEXT: .cfi_def_cfa_offset 16 1138; RV32-V-NEXT: lui a0, 131072 1139; RV32-V-NEXT: sw a0, 12(sp) 1140; RV32-V-NEXT: li a0, 1 1141; RV32-V-NEXT: sw a0, 8(sp) 1142; RV32-V-NEXT: addi a0, sp, 8 1143; RV32-V-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1144; RV32-V-NEXT: vlse64.v v16, (a0), zero 1145; RV32-V-NEXT: vmulhu.vv v8, v8, v16 1146; RV32-V-NEXT: li a0, 61 1147; RV32-V-NEXT: vsrl.vx v8, v8, a0 1148; RV32-V-NEXT: addi sp, sp, 16 1149; RV32-V-NEXT: ret 1150; 1151; ZVE64X-LABEL: vdivu_vi_nxv8i64_0: 1152; ZVE64X: # %bb.0: 1153; ZVE64X-NEXT: li a0, -7 1154; ZVE64X-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1155; ZVE64X-NEXT: vdivu.vx v8, v8, a0 1156; ZVE64X-NEXT: ret 1157; 1158; RV64-V-LABEL: vdivu_vi_nxv8i64_0: 1159; RV64-V: # %bb.0: 1160; RV64-V-NEXT: li a0, 1 1161; RV64-V-NEXT: slli a0, a0, 61 1162; RV64-V-NEXT: addi a0, a0, 1 1163; RV64-V-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1164; RV64-V-NEXT: vmulhu.vx v8, v8, a0 1165; RV64-V-NEXT: li a0, 61 1166; RV64-V-NEXT: vsrl.vx v8, v8, a0 1167; RV64-V-NEXT: ret 1168 %head = insertelement <vscale x 8 x i64> poison, i64 -7, i32 0 1169 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 1170 %vc = udiv <vscale x 8 x i64> %va, %splat 1171 ret <vscale x 8 x i64> %vc 1172} 1173 1174define <vscale x 8 x i64> @vdivu_vi_nxv8i64_1(<vscale x 8 x i64> %va) { 1175; CHECK-LABEL: vdivu_vi_nxv8i64_1: 1176; CHECK: # %bb.0: 1177; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1178; CHECK-NEXT: vsrl.vi v8, v8, 1 1179; CHECK-NEXT: ret 1180 %head = insertelement <vscale x 8 x i64> poison, i64 2, i32 0 1181 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 1182 %vc = udiv <vscale x 8 x i64> %va, %splat 1183 ret <vscale x 8 x i64> %vc 1184} 1185 1186; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 1187define <vscale x 8 x i64> @vdivu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 1188; CHECK-LABEL: vdivu_vi_nxv8i64_2: 1189; CHECK: # %bb.0: 1190; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1191; CHECK-NEXT: vadd.vi v16, v16, 4 1192; CHECK-NEXT: vsrl.vv v8, v8, v16 1193; CHECK-NEXT: ret 1194 %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0 1195 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 1196 %vc = shl <vscale x 8 x i64> %splat, %vb 1197 %vd = udiv <vscale x 8 x i64> %va, %vc 1198 ret <vscale x 8 x i64> %vd 1199} 1200